ISSN (Online) 2321 – 2004
ISSN (Print) 2321 – 5526
INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 2, Issue 4, April 2014
Phase Locked Loop using VLSI Technology For
Wireless Communication
Chaitali P.Charjan1, Asso.Prof.Atul S.Joshi2
PG student, Department of Electronics & Telecommunication, Sipna’s college of Engineering & Technology,
Amravati, Maharashtra, India1
Associate Professor, Department of Electronics & Telecommunication, Sipna’s college of Engineering & Technology,
Amravati, Maharashtra, India2
Abstract: Literature survey of Phase Locked Loop reflects that many researchers have applied different techniques like
digital and analog simulation by applying mathematical/logical relations to design the Phase Locked Loop (PLL).
Researchers have undertaken different systems, processes or phenomena with regard to design and attempted to find the
unknown parameters and analysed PLL. Since in the real world today VLSI/CMOS is in very much in demand, it is
observed that very few researchers have undertaken the work for designing PLL using CMOS/VLSI technology. The
PLL is designed using 45 nm CMOS/VLSI technology in microwind 3.1. The main novelties related to the 45 nm
technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate length
required for 45 nm technology is 25nm.
Keywords: Phase locked loop (PLL), voltage-controlled oscillator (VCO), 45nm technology, VLSI technology, low
power
I. INTRODUCTION
A phase locked loop (PLL) is widely applied for different microwave range they are used in frequency synthesis and
purposes in various domains such as communication and phase recovering among others. To maintain a well-
instrumentation. In the microwave range they have been defined phase and hence frequency relation between two
applied in frequency synthesis and phase recovering independent signal sources, phase-locked loop can be
among others. Phase-locked loop can be used to maintain used. Basic PLL consists of three elements: a phase
a well-defined phase, and hence frequency relation detector, a loop filter and a voltage controlled oscillator
between two independent signal sources. Due to their (VCO) as shown in figure.
versatility, PLLs are usually preferred over other methods
of maintaining phase lock such as injection locking.
Monolithic phase locked loops have been used for clock-
&-data recovery in communication system, clock
generation & distribution in microprocessor and frequency
synthesis in wireless application. Until DSP technology is
capable of directly processing and generating the RF Figure 1.1: Block diagram of PLL
signals used to transmit wireless data, traditional RF
engineering will remain a fundamental part of wireless The output voltage of phase detector is proportional to the
communication systems design. phase difference between the VCO’s output signal and the
reference. The phase detector’s output produces a regular
As it stands, wireless transceivers must still be able to square oscillation when the clock input and signal input
generate a wide range of frequencies in order to up convert
have one quarter of period shift or 900 ( /2). For angles
the outgoing data for transmission and down convert the other than 900, the output is not regular. The phase error
received signal for processing. Monolithic phase locked voltage controls the VCO’s frequency after being filtered
loops have been used for clock-&-data recovery in by the loop filter. The filter used in PLL transforms the
communication system, clock generation and distribution phase difference into an analog control voltage which is
in microprocessor and frequency synthesis in wireless same as the average output of phase detector. The filter
application. The Phase locked loop is a feedback system converts rapid variations of the phase detector output into
as can be seen in the figure. It is a basic building block a slow varying signal, which later controls the voltage
which is widely used in communications system such as controlled oscillator.
mobile phones, which may contain up to 5 PLL’s. Another
important application are in motor speed control and for The most vital part of PLL is VCO which is used to
optical disk drive (ODD’s) as found in DVD’s and CD produce clock in phase locked loop circuits. This unit
players. The basic PLL can be analog or digital. A phase ingests most of the power in the system in addition to
locked loop (PLL) is used for different purposes in various operating at highest frequency i.e. the VCO reduces power
sectors such as communication and instrumentation. In the
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ISSN (Online) 2321 – 2004
ISSN (Print) 2321 – 5526
INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 2, Issue 4, April 2014
consumption. Although there are a variety of frequency
synthesis techniques, phase locked loop (PLL) represent
the dominant method in the wireless communications
industry. PLL, like most wireless communication
technologies, is relatively new and has matured only in the
last decade.
The ability to execute all PLL functions on a single
integrated circuit (IC) has created an economical, mass
production solution to meet the needs of industry. Current
PLL ICs are highly integrated digital and mixed signal Fig: 1.3 -Simulation result of Phase locked loop
circuits that operate on low supply voltages and consume (Frequency vs. Time)
very low power. To have very low power consumption,
this work is decided to be implemented using VLSI IV. CONCLUSION
technology. The main problem with PLL design using deep submicron
technology is to gain low power consumption which may
II. SIMULATION SETUP be due to the uncertainty in the value of threshold or
This paper describes the use of CMOS 45nm technology
supply voltage. As PLLs are extensively used in
and the implementation of this technology in Microwind communication application such as frequency synthesis
3.1. In 45nm technology, required effective gate length is
for missile tracking, noise stability is the most important
25nm with metal gate and SiON gate dielectric. This factor which can be analysed with the components of
technology is called “High speed technology” as it is filter. The Software microwind 3.1 used in this paper
devoted to applications for which the highest speed is the allows us to design and simulate an integrated circuit at
primary objective: fast microprocessors, fast DSP, etc.
physical description level.
The use of Software Microwind 3.1 is done in this paper We can gain access to Circuit Simulation by pressing one
which allows us to design and simulate an integrated single key. The electric extraction of the circuit is
circuit at physical description level. We can gain access to
automatically performed and the analog simulator
the Circuit Simulation by pressing one single key in this
produces voltage and current curves immediately. The
software .The electric extraction of the circuit is performed
layout of PLL which is developed in this paper is a
automatically and the voltage and current curves are modified design of low power high performance VCO.
produced by the analog simulator immediately. This is an optimum design for use in industries at 45 nm
technology. In the estimated design, more emphasis is
III. EXPERIMENTAL RESULTS given on power consumption and layout design. This PLL
Figure1.2. shows the layout of phase locked loop using consumes a very low power.
45nm technology. This PLL is designed with microwind
3.1 software using 45 nm design rule. Fig 1.3 shows the REFERENCES
simulation result of Phase Locked Loop. [1] J. C. Li and G. C. Hsieh, "A phase/frequency-locked controller for
stepping servo systems", IEEE Trans. Ind. Electron., vol. 39,
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[2] B. Razavi, “Design of monolithic phase-locked-loops and clock
recovery circuits-a tutorial,” Monolithic Phase-Locked Loops and
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[3] M. Mansuri, D. Liu, and C. Yang, “Fast frequency acquisition
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IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 138–452, Oct.
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[4] Chih-Ming Hung and Kenneth K. O, “A Fully Integrated 1.5-V 5.5-
GHz CMOS Phase-Locked Loop,” IEEE J. Solid-State Circuits
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[5] P. Hanumolu, M. Brownlee, K. Mayaram, and U. Moon, “Analysis
of charge-pump phase-locked loops,” IEEE Trans. Circuits Syst. I,
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[6] Fernando Rangel De Sousa, “A reconfigurable high frequency
phase-locked loop” IEEE transactions on instrumentation &
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[7] M. Brownlee, P. Hanumolu, K. Mayaram, and U. Moon, “A 0.5 to
Fig 1.2 – Layout of PLL Using 45nm Technology 2.5 GHz PLL with fully differential supply regulated tuning,” IEEE
ISSCC Dig. Tech. Papers, pp. 588–589, Feb. 2006.
The simulation of a low power PLL is shown fallowing [8] Navid Azizi, Student Member, IEEE, Muhammad M. Khellah,
figure 1.3 .This shows the simulation of a high Member, IEEE, Vivek K. De, Senior Member, IEEE, and Farid N.
Najm, Fellow, IEEE, “Variations-Aware Low-Power Design And
performance PLL circuit, frequency versus time .The Block Clustering With Voltage Scaling,” IEEE TRANSACTIONS
frequency is 5GHz. for which power consumed is 50.243 ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
microwatt. Vol. 15 No.7, July 2007.
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ISSN (Online) 2321 – 2004
ISSN (Print) 2321 – 5526
INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 2, Issue 4, April 2014
BIOGRAPHIES
Chaitali P.Charjan received the bachelor’s
degree in Electronics and
Telecommunication Engineering from Prof.
Ram Meghe College of Technology &
Research, Amravati, Maharashtra, India and currently
pursuing M.E in Electronics &Telecommunication from
Sipna College of Engineering & Technology, Amravati,
Maharashtra, India.
Asso.Prof.Atul S.Joshi is currently working
as an Associate Professor in Electronics and
Telecommunication Engineering Department,
Sipna College of Engineering & Technology,
Amravati, Maharashtra, India.
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