CS 1104-01 - AY2023-T3 - Unit 1 Assignment
CS 1104-01 - AY2023-T3 - Unit 1 Assignment
Unit 1 Assignment
For your first assignment download and install both the TECS software and the Logism software. Execute each tool to ensure that they
will execute. Keep in mind that the Logism, Assembler, and CPU Emulator tools are required for this course. You are welcome to use
the hardware simulator to follow along with the exercises in Chapters 1,2, and 3 but this is not required. If you have issues getting the
software installed correctly or getting the tools to execute, please refer to the instructions and help in the respective web sites for both
Logism and TECS.
The lab requires that you use a computer that has a Java 1.5 JRE installed, but will not require the installation of any other software.
When you have successfully been able to install and execute these tools, use Logism to simulate each of the following gates. What this
means is that create the gate within logism, assign both input and output pins to it and then experiment with the gate to understand
its' properties.
In this example we see the behavior of the NAND gate which has an output of 1 until both of the inputs are 1 at which time the output
becomes 0. As part of your assignment simulate each of the following gates and validate their truth tables using the logism
simulation. Please note that by clicking on the input pins you can change their value from 0 to 1 or back to 0 when in simulation
mode. Logism is in simulation mode when the Red Hand (see upper left part of the screen in the figure above) has been selected. In
order to build the circuit the arrow ( just to the right of the red hand) must be selected. In order wire the logic gate into a circuit, you
can select input pins and place them on the screen. You can place the gates in the same manner by selecting a gate from the menu
and clicking on the white portion of the screen to place it there. By clicking on a component (input pin, gate, or other component) and
dragging, a wire will be created connecting the components together. A short video lecture in the Unit 1 optional videos section of the
course page will show exactly how this is done.
The preceding diagram details most of the common logic gates along with their functional definitions and their respective truth ables.
Using Logism, simulate each of these gates and verify that their operation matches the truth tables in the graphic.
All activities close on Wednesdays at 11:55 PM, except for Learning Journals/Portfolios which close on Thursdays at 11:55 PM always
following the clock at the top of the page.
Due dates/times displayed in activities will vary with your chosen time zone, however you are still bound to the 11:55 PM GMT-5
deadline.
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