Unit 4
Unit 4
Let us consider the negative-feedback system shown in Fig. 10.1(a), where β is assumed constant. Writing
the closed-loop transfer function as
we note that if βH(s = jω1) = −1 at ω1 _= 0, then the closed-loop “gain” goes to infinity, and the circuit can amplify
its own noise until it eventually begins to oscillate. In other words, if the loop gain at ω1, βH( jω1), is equal to −1,
then the circuit may oscillate at frequency ω1. This condition can be expressed as
|βH( jω1)| = 1
βH( jω1) = −180◦
which are called “Barkhausen’s Criteria.” Note that (1) these equations relate only to the loop gain (more precisely,
the loop transmission and are independent of where the input and output are located, and (2) the total phase shift
around the loop at ω1 is 360◦ because negative feedback itself introduces 180◦ of phase shift [Fig. 10.1(b)]. The 360
◦ phase shift is necessary for oscillation since the feedback signal must add in phase to the original noise to allow
oscillation buildup. By the same token, a loop gain of unity (or greater) is also required to enable growth of the
oscillation amplitude. The key point here is that the loop transmission, which can often be found from the open-loop
system, reveals the stability of the closed-loop system.
In summary, a negative-feedback system may oscillate at ω1 if (1) the phase shift around the loop at this
frequency is so great that the feedback becomes positive and (2) the loop gain is still enough to allow signal buildup.
Illustrated in Fig. 10.2(a), the situation can be viewed as excessive loop gain at the frequency at which the phase
shift reaches −180◦ or, equivalently, excessive phase at the frequency at which the loop gain drops to unity. Thus, to
avoid instability, we must minimize the total phase shift so that if |βH| = 1, then _ βH is still more positive than −
180◦ [Fig. 10.2(b)]. In this chapter, we assume that β is less than or equal to unity and does not depend on the
frequency.
The frequencies at which the magnitude and phase of the loop gain are equal to unity and −180◦
,respectively, play a critical role in the stability and are called the “gain crossover frequency” and the “phase
crossover frequency,” respectively. In a stable system, the gain crossover must occur well before the phase
crossover. For the sake of brevity, we denote the gain crossover by GX and the phase crossover by PX. It is helpful
to note that the gain crossover frequency is the same as the unity-gain bandwidth of the loop transmission.
A few basic rules for constructing Bode plots. A Bode plot illustrates the asymptotic behavior of the
magnitude and phase of a complex function according to the magnitude of the poles and zeros. The following two
rules are used. (1) The slope of the magnitude plot changes by+20 dB/dec at every zero frequency and by−20 dB/dec
at every pole frequency. (2) For a pole (zero) frequency of ωm, the phase begins to fall (rise) at approximately
0.1ωm, experiences a change of −45◦ (+45◦) at ωm, and approaches a change of −90◦ (+90◦) at approximately 10ωm.
The key point here is that the phase is much more significantly affected by high-frequency poles and zeros than the
magnitude is.
It is also instructive to plot the location of the poles of a closed-loop system on a complex plane.
Expressing each pole frequency as sp = jωp + σp and noting that the impulse response of the system includes a term
exp( jωp + σp)t, we observe that if sp falls in the right half plane (RHP), i.e., if σp > 0, then the system oscillates
because its time-domain response exhibits a growing exponential [Fig. 10.4(a)]. Even if σp = 0, the system sustains
oscillations [Fig. 10.4(b)]. Conversely, if the poles lie in the left half plane (LHP), all time-domain exponential
terms decay to zero [Fig. 10.4(c)].2 In practice, we plot the location of the poles as the loop gain varies, thereby
revealing how close to oscillation the system may come. Such a plot is called a “root locus.”
We now study a feedback system incorporating a one-pole forward amplifier. Assuming H(s) =
A0/(1 + s/ω0), we have from (10.1)
In order to analyze the stability behavior, we plot |βH(s = jω)| and _ βH(s = jω) (Fig. 10.5), observing
that a single pole cannot contribute a phase shift greater than 90 ◦ and the system is unconditionally stable
for all nonnegative values of β. Note that _ βH is independent of β.
1. Multipole Systems
In two stage op amps, for example, each gain stage introduces a “dominant” pole. It is therefore important
to study a feedback system whose core amplifier exhibits more than one pole.
Let us consider a two-pole system first. For stability considerations, we plot |βH| and _ βH as a function
of the frequency. Shown in Fig. 10.7, the magnitude begins to drop at 20 dB/dec at ω = ωp1 and at 40 dB/dec at ω =
ωp2. Also, the phase begins to change at ω = 0.1ωp1, reaches −45◦ at ω = ωp1 and −90◦ at ω = 10ωp1, begins to
change again at ω = 0.1ωp2 (if 0.1ωp2 > 10ωp1), reaches −135◦ at ω = ωp2, and asymptotically approaches −180◦.
The system is therefore stable because |βH| drops to below unity at a frequency where _ βH < −180◦.
if the feedback is made “weaker”? To reduce the amount of feedback, we decrease β,obtaining the gray magnitude
plot in Fig. 10.7. As the feedback becomes weaker, the gain crossover point moves toward the origin while the phase
crossover point remains constant, resulting in a more stable system. The stability is obtained at the cost of weaker
feedback.
A three-pole system. shown in Fig. 10.9(a) are the Bode plots of the magnitude and phase of the loop gain. The third
pole gives rise to additional phase shift, possibly moving the phase crossover to frequencies lower than the gain
crossover and leading to oscillation. Since the third pole also decreases the magnitude of the loop gain at a greater
rate, the reader may wonder why the gain crossover does not move as much as the phase crossover does. As
mentioned before, the phase begins to change at approximately one-tenth of the pole frequency, whereas the
magnitude begins to drop only near the pole frequency. For this reason, additional poles (and zeros) affect the phase
to a much greater extent than they do the magnitude.
2. Phase Margin
We have seen that to ensure stability, |βH| must drop to unity before _ βH crosses −180◦. We may
naturally ask: How far should PX be from GX? Let us first consider a “marginal” case where, as depicted in Fig.
10.10(a), GX is only slightly below PX; for example, at GX, the phase equals −175◦. How does the closed-loop
system respond in this case? Noting that at GX, βH( jω1) = 1×exp(−j175◦), we have for the closed-loop system
Since at low frequencies, |Y/X| ≈ 1/β, the closed-loop frequency response exhibits a sharp peak in the
vicinity of ω = ω1. In other words, the closed-loop system is near oscillation, and its step response, y(t), exhibits a
very underdamped behavior. This point also reveals that a second-order system may suffer from ringing although it
is stable.
As shown in Fig. 10.10(b), GX precedes PX by a greater margin. Then, we expect a relatively “well-
behaved” closed-loop response in both the frequency domain and the time domain. It is therefore plausible to
conclude that the greater the spacing between GX and PX (while GX remains below PX), the more stable the
feedback system. Alternatively, the phase of βH at the gain crossover frequency can serve as a measure of stability:
the smaller |_ βH| at this point, the more stable the system.
This observation leads us to the concept of “phase margin” (PM), defined as PM = 180◦ +_ βH(ω =ω1),
where ω1 is the gain crossover frequency. We see that stability calls for a positive and large PM. The concept of
phase margin is well suited to the design of circuits that process small signals. In practice, the large-signal step
response of feedback amplifiers does not follow the illustration of Fig. 10.13. This is not only due to slewing but
also because of the nonlinear behavior resulting from large excursions in the bias voltages and currents of the
amplifier. Such excursions in fact cause the pole and zero frequencies to vary during the transient, leading to a
complicated time response. Thus, for large-signal applications, time-domain simulations of the closed-loop system
prove more relevant and useful than small-signal ac computations of the open-loop amplifier.
A feedback circuit exhibiting a reasonable phase margin but poor settling behavior, consider the unity-gain
amplifier of Fig. 10.14, where the aspect ratio of all transistors is equal to 50 μm /0.6 μm.With the choice of the
device dimensions, bias currents, and capacitor values shown here, SPICE yields a phase margin of approximately
65◦ and a unity-gain frequency of 150 MHz. The large-signal step response, however, suffers from significant
ringing.
3. Frequency Compensation
Op amp circuits contain many poles. In a folded-cascode topology, for example, both the folding node and
the output node contribute poles. For this reason, op amps must usually be “compensated,” that is, their open-loop
transfer function must be modified such that the closed-loop circuit is stable and the time response is well behaved.
The need for compensation arises because |βH| does not drop to unity well before _ βH reaches −180◦.
We then postulate that stability can be achieved by (1) minimizing the overall phase shift, thus pushing the phase
crossover out [Fig. 10.15(a)]; or (2) dropping the gain with frequency, thereby pushing the gain crossover in [Fig.
10.15(b)]. The first approach requires that we attempt to minimize the number of poles in the signal path by proper
design. Since each additional stage contributes at least one pole, this means that the number of stages must be
minimized, a remedy that yields low voltage gain and/or limited output swings .The second approach, on the other
hand, retains the low-frequency gain and the output swings, but it reduces the bandwidth by forcing the gain to fall
at lower frequencies.
To design an op amp so as to minimize the number of poles while meeting other requirements. Since the resulting
circuit may still suffer from insufficient phase margin, we then compensate the op amp, i.e., modify the design so as
to move the gain crossover toward the origin. These efforts proceed with the β value chosen according to the final
design requirements. For example, a closed-loop gain of 4 in some cases translates to β ≈ 0.25 if the loop gain is
large.3 In other words, we need not compensate the circuit for β = 1 if the closed-loop gain is always higher.
Let us apply the above concepts to the telescopic-cascode op amp shown in Fig. 10.16, where a PMOS
current mirror performs differential to single-ended conversion. We identify a number of poles in the signal paths:
path 1 contains a high-frequency pole at the source of M3, a mirror pole at node A, and another high-frequency pole
at the source of M7, whereas path 2 contains a high-frequency pole at the source of M4. The two paths share a pole at
the output.
It is instructive to estimate the relative position of these poles. Since the output resistance of the op amp is much
higher than the small-signal resistances seen at the other nodes in the circuit, we expect that, even with a moderate
load capacitance, the output pole, ωp,out , is the closest to the origin. Called the “dominant pole,” ωp,out usually sets
the open-loop 3-dB bandwidth.
To compensate the telescopic-cascode op amp is to ensure a loop gain sufficiently less than unity at the
phase crossover frequency. Let us assume that the number and location of the non dominant poles and hence the
phase plot at frequencies higher than roughly 10ωp,out , remain constant.We begin with the original response shown
in Fig. 10.19,which has a negative phase margin.We must force the loop gain to drop such that the gain crossover
point moves toward the origin.
To accomplish this, we simply lower the frequency of the dominant pole, ωp1, by increasing the load
capacitance. The key point is that the phase contribution of the dominant pole in the vicinity of the gain or phase
crossover point is close to 90◦ and relatively independent of the location of the pole. That is, as illustrated in Fig.
10.19, translating the dominant pole toward the origin affects the magnitude plot, but not the critical part of the
phase plot. If ωp1 is lowered sufficiently, the PM reaches an acceptable value, but at the cost of bandwidth.
To compensate the circuit, we begin from _ βH(ω) = −180◦ + PM = −135◦ and identify the corresponding gain
crossover frequency, in this case, ωp,A (Fig. 10.20). Since the dominant pole must drop the gain to unity at ωp,A with
a slope of 20 dB/dec, we draw a straight line from ωp,A toward the origin with such a slope, thus obtaining the new
magnitude of the dominant pole, ω_p,out . Therefore, the load capacitance must be increased by a factor of
ωp,out/ω_p,out .
From the new magnitude plot, we note that the unity-gain bandwidth of the compensated (open-loop)op amp is
equal to the frequency of the first nondominant pole (of course with a phase margin of 45◦).This is a fundamental
result, indicating that to achieve a wide bandwidth in a feedback system employing a multipole op amp, the first
nondominant pole must be as far as possible. For this reason, the mirror pole proves undesirable.
We should also mention that although ωp,out = (RoutCL )−1, increasing Rout does not compensate the op amp. As
shown in Fig. 10.21, a higher Rout results in a greater low-frequency loop gain, only affecting the low-frequency
portion of the characteristics.
From these observations, we can construct the magnitude and phase plots shown in Fig. 10.26. Here, ωp,E is assumed
more dominant, but the relative positions of ωp,E and ωp,A depend on the design and the load capacitance. Note that,
since the poles at E and A are relatively close to the origin, the phase approaches −180◦ well below the third pole. In
other words, the phase margin may be close to zero even before the third pole contributes significant phase shift.
Let us now investigate the frequency compensation of two-stage op amps. In Fig. 10.26, one of the
dominant poles must be moved toward the origin so as to place the gain crossover well below the phase crossover.
However, that the unity-gain bandwidth after compensation cannot exceed the frequency of the second pole of the
open-loop system for PM > 45◦. Thus, if in Fig. 10.26 the magnitude of ωp,E is to be reduced, the available
bandwidth is limited to approximately ωp,A, a low value. Furthermore, the very small magnitude of the new
dominant pole translates to a large compensation capacitor. Fortunately, a more efficient method of compensation
can be applied to the circuit of Fig. 10.25.
To arrive at this method, we note that, as illustrated in Fig. 10.27(a), the first stage exhibits a high output
impedance, Rout1, and the second stage provides a moderate gain, Av2, thereby creating a suitable environment for
Miller multiplication of capacitors. Shown in Fig. 10.27(b), the idea is to create a large capacitance at node E, equal
to (1+Av2)CC, moving the corresponding pole to R−1 out1[CE+(1+Av2)CC]−1,where CE denotes the capacitance at node E
before CC is added. As a result, a low-frequency pole can be established with a moderate capacitor value, saving
considerable chip area. This technique is called “Miller compensation.”
In addition to lowering the required capacitor value, Miller compensation entails a very important property: it moves
the output pole away from the origin. Illustrated in Fig. 10.28, this effect is called “pole splitting.” To understand the
underlying principle, we simplify the output stage of Fig. 10.25 as in Fig. 10.29, where RS denotes the output
resistance of the first stage and RL = rO9||rO11. The compensated circuit contains two poles:
To better understand the foregoing discussion, let us construct the Bode plots for a third-order system containing a
dominant pole ωp1, two non dominant poles ωp2 and ωp3, and a zero in the right half plane ωz . For two-stage op
amps, typically |ωp1| < |ωz | < |ωp2|. As shown in Fig. 10.31, the zero introduces significant phase shift while
preventing the gain from falling sufficiently.
The right-half-plane zero in two-stage CMOS op amps, given by gm/(CC + CGD), is a serious issue because gm is
relatively small and CC is chosen large enough to position the dominant pole properly. Various techniques for
eliminating or moving the zero have been invented. In Fig. 10.32, places a resistor in series with the compensation
capacitor, thereby modifying the zero frequency. The output stage now exhibits three poles, but for moderate values
of Rz , the third pole is located at high frequencies and the first two poles are close to the values calculated with Rz =
0. Moreover, that the zero frequency is given by
5.
6. Other Compensation Techniques
The difficulty in compensating two-stage CMOS op amps arises from the feedforward path
formed by the compensation capacitor [Fig. 10.41(a)]. If CC could conduct current from the output node
to node X but not vice versa, then the zero would move to a very high frequency. As shown in Fig.
10.41(b), this can be accomplished by inserting a source follower in series with the capacitor. Since the
gate-source capacitance of M2 is typically much less than CC, we expect the right-half-plane zero to occur
at high frequencies.
Assuming that γ = λ = 0 for the source follower, neglecting some of the device capacitances, and
simplifying the circuit as shown in Fig. 10.42, we can write −gm1V1 = Vout R−1L+ CL s), and hence
Thus, the circuit contains a zero in the left half plane, which can be chosen to cancel one of the poles.The
zero can also be derived as illustrated in Fig. 6.18. We can also compute the magnitudes of the two poles,
assuming that they are widely separated. Since typically 1 + gm2RS _ 1 and (1 + gm1gm2RL RS)CC _ gm2RLCL,
we have
Thus, the new values of ωp1 and ωp2 are similar to those obtained by simple Miller approximation. For
example, the output pole has moved from (RLCL )−1 to gm1/CL .
The primary issue in the circuit of Fig. 10.41(b) is that the source follower limits the lower end of the
output voltage to VGS2 + VI 2, where VI 2 is the voltage required across I2. For this reason, it is desirable to
utilize the compensation capacitor to isolate the dc levels in the active feedback stage from that at the
output. Such a topology is depicted in Fig. 10.43, where CC and the common-gate stage M2 convert the
output voltage swing to a current, returning the result to the gate of M1 . If V1 changes by _V and Vout by
Av_V, then the current through the capacitor is nearly equal to Av_VCCs because 1/gm2 can be relatively
small. Thus, a change_V at the gate of M1 creates a current change of Av_VCCs, providing a capacitor
multiplication factor equal to Av. Assuming that λ = γ = 0 for the common-gate stage, we redraw the
circuit of Fig. 10.43 in Fig. 10.44, where we have