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Verilog Sequential

verilog slides

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Tasnim Chaviwala
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6 views

Verilog Sequential

verilog slides

Uploaded by

Tasnim Chaviwala
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital Design

(ECE/EEE/INSTR F215 )

Verilog-Sequential

Prof. Anita Agrawal


BITS-Pilani,K.K.Birla Goa campus

13th Sept, 2024

1
Behavioral modeling

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 2


D-FF

module dff(q,d,clk,reset);

input d,clk,reset;
output q;
reg q;

always@(negedge clk)
if(reset)
q <=1'b0;
else
q <=d;
endmodule

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 3


Behavioral modeling

◉ The designers do not unnecessarily think in terms


of logic gates or data flow, but in terms of the
algorithm that they wish to implement in the
hardware.

◉They are more concerned about the behavior of


the algorithm and its performance

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 4


Behavioral modeling

◉ Uses two structured procedure statements:


- initial
- always
◉The statements initial and always cannot be
nested

◉It is a concurrent programming language .

◉Each activity flow starts at simulation time 0.

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 5


initial

◉All statements inside an initial statement constitute


an initial block

◉Executes exactly once during simulation.

◉Starts at time 0.

◉Multiple initial blocks: All start executing


concurrently at time 0

◉Each block finishes execution independently of


another
9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 6
◉If more than one statement, should be grouped
using ‘begin’ and ‘end’ keywords

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 7


module example_initial;
reg a,b,c,x,y;

initial
x= 1’b0; //single statement does not need to be grouped

initial
begin
#5 a=1’b1; // multiple statements need to be grouped
#20 b=2’b01;
end

initial
begin
#10 x=1’b1;
#20 y=1’b0;
end
9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 8
Initial…..contd

initial

#50 $finish;

endmodule

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 9


always statement

◉All behavioral statements inside an always


statement constitute an always block.

◉It starts at time 0 and executes all the statements


continuously in a looping fashion

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 10


always syntax

module example_always (output reg clk);


// initialise clk at time 0
initial
clk = 1’b0;

always
#20 clk = ~clk;

initial
#500 $finish;
endmodule

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 11


always contd…..
◉Two operators:
delay control
event control

◉Delay control waits for certain time


◉Event control waits for certain event

◉General form of event control is:


always@ (event control expression)
begin
//procedural statements
end
9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 12
◉A procedural statement is an assignment of a
logic value to a variable within an initial or always
statement.

◉Statements within an always block execute


sequentially from top to bottom

◉ always @ (A or B or C)
will initiate execution if a change appears in A or
B or C.

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 13


◉A procedural assignment is made only when an
assignment statement is executed within a
behavioral statement

◉In data flow, it has an implicit level sensitivity list,


consisting of all the variables on the R.H.S of the
assign statement

◉always@ (posedge clock)

◉ always@ (negedge clock)

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 14


Types of procedural statements

◉Blocking (=)

◉Non-Blocking (<=)

◉Blocking: executed sequentially in the order in


which they are listed in a block of statements

◉Non-Blocking: executed concurrently by


evaluating the set of expressions on the RHS of the
list of assignments.
◉They do not make assignments to their LHS until
all the expressions are evaluated
9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 15
Examples

◉B=A
◉ C = B+1

◉B<= A
◉C<=B+1

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 16


Port declarations

◉All port declarations are implicitly declared as wire


in Verilog.
◉Three types of ports: input, output, inout
◉Input or inout port is normally declared as wire.
◉But if output ports hold their value, they must be
declared as reg.
◉For ex. In case of d –ff, we want the output q to
retain its value till the next positive edge of the
clock.
◉ so the declaration is as follows:
◉ output q;
◉ reg q;
9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 17
◉Ports of the type input or inout cannot be declared
as wires, because they are not suppose to store the
values but only reflect the changes in the external
signals they are connected to.

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 18


◉Refer section 5.6 DD fourth edition

9/14/2024 Anita Agrawal CS/ECE/EEE/INSTR F215 19

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