Chapter 3

Basic elements of digital protection

3.1 Introduction

Operating voltages and currents flowing through a power system are usually at kilo-
volt and kiloampere levels. However, for digital processing, it is necessary to reduce
the primary measurands to manageable levels. Therefore, the analogue signals are
converted to digital form, thereby allowing subsequent digital processing to be per-
formed to determine the circuit state.
In this chapter, the basic principles underlying the conversion of analogue sig-
nals into equivalent digital forms will be explained. We shall also explain the essen-
tial common features of various digital relaying schemes, other detailed aspects
being discussed in later chapters.

3.2 Basic components of a digital relay

Any digital relay can be thought of as comprising three fundamental subsystems

(Figure 3.1):

i. a signal conditioning subsystem

ii. a conversion subsystem
iii. a digital processing relay subsystem

The first two subsystems are generally common to all digital protective schemes,
while the third varies according to the application of a particular scheme. Each of the
three subsystems is built up of a number of components and circuits, as discussed in
detail in the following sections.

3.3 Signal conditioning subsystem

3.3.1 Transducers
Primary power system currents and voltages are usually relatively high. Before it is
possible to bring these signals to protective relays, they must therefore be reduced to
much lower levels [1–5]. Conventionally, currents are reduced either to 5 or 1 A and
62 Digital protection for power systems

voltages are reduced to 110 or 120 V. This is normally achieved by using primary
current and voltage transducers (CTs and VTs). In digital relays, however, current
and voltage magnitudes are both further reduced using auxiliary transducers and/
or mimic impedances within the relays to suit the requirements of the components
used.
Ideally, the current transformer would reproduce a perfectly scaled-­down ver-
sion of the primary signal on its secondary side. Practical transformers reproduce
the secondary current with some error because these devices incorporate ‘non-­ideal’
elements. The worst condition occurs when the iron core saturates during faults.
The degree of signal distortion and the time after a fault at which it occurs are
heavily dependent on the total burden connected to the primary current transducers.
However, in most modern practical applications, the overall burden is such that the
current signal distortion is small during the measuring period. In cases where this
is not so, it is desirable to establish the effect on performance and, if necessary,
incorporate means within the relay software to ensure that the integrity of measure-
ment is maintained. Some work on compensating for current transducer saturation
is to be found in the literature, although, in most applications, this is unnecessary. In
what follows, the effect of current transducer saturation will, for brevity, be assumed
negligible.
Electromagnetic VTs generally produce a very high-­fidelity voltage signal,
though in fact these are rarely used at system voltages typically above 100 kV. At
higher voltages, the use of capacitor voltage transformers (CVTs) is commonplace.
Unfortunately, the transient response of CVTs varies widely according to the type
of transducer involved and the nature of the total connected burden. In high-­speed
relaying applications, in particular, account needs to be taken of the rather poor fidel-
ity of the voltage signals that emanate from CVTs, there being many examples in
the literature of which the digital algorithm compensates for such effects. A detailed
consideration of such techniques is not necessary in a text of this type.

3.3.2 Surge protection circuits

The current and voltage from the secondaries of the CTs and VTs are connected to
surge protective circuits, which typically consist of capacitors and isolating trans-
formers (Figure 3.2). Zener diodes are also commonly used to protect electronic
circuits against surges, though their placement depends on the exact physical circuit
arrangement used. In practice, it is common to convert the secondary current meas-
urands into low-­level voltage signals by means of a suitably connected burden and/
or current-­to-­voltage amplifier arrangement. The latter normally uses careful screen-
ing techniques and is often accommodated inside separately screened self-­contained
modules separated from the digital signal processing hardware.

3.3.3 Analogue filtering

It is normally necessary to perform analogue filtering of the signals received from the
CTs and VTs. In practice, the amount of filtering depends on the data requirements
of a particular digital relay. Such filtering is usually performed using low-­pass filters
 Basic elements of digital protection 63

Figure 3.1   Basic components of a digital relay

64 Digital protection for power systems

Figure 3.2   Simple surge protective circuit, where LP = low pass

to remove unwanted high frequencies before sampling. In fact, as will be shown in

section 3.4, the sampling theorem requires that analogue signal components above
a certain frequency (which in turn is related to the digital sampling frequency) be
attenuated to avoid errors in subsequent digital processing. It is this ‘anti-­aliasing’
function that is importantly fulfilled by the analogue low-­pass filters, which must be
designed with a cut-­off frequency (fc) that performs satisfactory signal component
rejection above a given frequency. Figure 3.3(a) shows the characteristics of an ideal
low-­pass filter, which transfers signal components of frequencies below the cut-­off
frequency with zero attenuation, while components above the cut-­off frequency are
attenuated to zero. The effect of introducing a practical low-­pass filter is shown in
Figure 3.3(b), from which it can be seen that in practice it is not possible to achieve
such a pronounced transition between the pass and stop bands.
The dynamic characteristics of the low-­pass filters, as well as their steady-­state
characteristics, are important. Among the more important factors are

i. the rise time, which gives an indication of how long it takes the
output of a low-­pass filter to traverse its final value following a
step input
ii. the overshoot, which indicates by how much the filter output will
exceed its steady-­state value on the initial response to a unit step
input
 Basic elements of digital protection 65

iii. the settling time, which is an indication of how long it takes a given
filter to settle at its steady-­state output value

All the above features play a part in the overall dynamic response of digital relay
systems. In particular, in systems where a very high-­speed decision is required, it is
particularly important to ensure that the low-­pass filter is designed to have a cut-­off fre-
quency that gives an overall performance that is not degraded by long filter delays [6].

3.3.4 Analogue multiplexers
In digital relaying applications, it is usually necessary to use an analogue multi-
plexer. The concept of multiplexing has its origins in communications engineering.
An analogue multiplexer is a device that selects a signal from one of a number of
input channels and transfers it to its output channel, thereby permitting the transmis-
sion of several signals in a serial manner over a single communication channel [7].

Figure 3.3 Characteristic of low-­pass filters: (a) ideal filter response and
(b) practical filter response
66 Digital protection for power systems

Figure 3.4   Principle of multiplexing

The principles of multiplexing are thus as shown in Figure 3.4, in which the solid-­
state multiplexer is likened to a multiterminal rotary switch.

3.4 Conversion subsystem

3.4.1 The sampling theorem

The sampling theorem states that a band-­limited signal can be uniquely specified
by its sampled values if and only if the sampling frequency is at least twice the
maximum frequency component contained within the original signal [8]. This can
be expressed mathematically as follows:

‍ fs  2fm‍ (3.1)

where fs is the sampling frequency and fm is the maximum significant frequency

within the signal sampled.
The frequency component at half the sampling frequency is known as the
Nyquist frequency fN, or

‍ fN = fs /2‍ (3.2)

The sampling process is effectively achieved by connecting an analogue signal f(t)

to the data acquisition system by means of a fast acting switch, which closes for
a very short time but remains open for the rest of the period (Figure 3.5(a)). This
operation can be modelled by a multiplier (Figure 3.5(b)), where f(t) is the band-­
limited analogue signal to be sampled, and s(t) is known as a sampling function. The
sampling function is, therefore, made of a train of pulses alternating between a value
of +1 and 0. It is thus defined as follows:
 P
1  
s t = ı t  nTs (3.3)
‍ n=1 ‍
The output of the multiplier fs(t) is as follows:
 Basic elements of digital protection 67

Figure 3.5 Sampling processes: (a) the sampler, (b) representation of the
sampler, (c) functions f(t), s(t) and fs(t) and (d) Fourier transforms of
f(t), s(t) and fs(t)

  P
1  
fs t =f t ı t  nTs
n=1
P
1     (3.4)
= f nTs ı t  nTs
‍ n=1 ‍
Figure 3.5(c) shows the three time functions f(t), s(t) and fs(t). It can be seen that the
sampling function fs(t) consists of a train of pulses spaced equally by a period equal
to the sampling interval Ts. The amplitude of each sample is the same as that of the
original signal at the respective sample time nTs. Therefore, the resulting samples
are included within the original signal envelope, as shown in Figure 3.5(c).
To show how and under what conditions f(t) can be uniquely reconstructed from
fs(t), let us examine the spectra of the three time functions f(t), s(t) and f(t). This is
shown in Figure 3.5(d), in which it is assumed that the function F(ω) contains no
frequency above ωm. The spectrum of the sampling function is thus given by
68 Digital protection for power systems

  P
1  
Fs ! = ! s S !  n!s (3.5)
‍ n=1 ‍
where ωs is the angular sampling frequency, given by ωs = 2πfs = 2π/Ts.
It will be noted that, in accordance with the convolution theorem, multiplica-
tion of two functions in the time domain is equivalent to their convolution in the
frequency domain. Therefore,
  1    
Fs ! = F ! S ! (3.6)
‍ 2 ‍
The convolution of F(ω) with each pulse of S(ω) produces Fs(ω) displaced in fre-
quency steps equal to nωs. Thus,
  1 P 1  
Fs ! = F !  n!s (3.7)
‍ Ts n=1 ‍
As illustrated in Figure 3.5(d), it is important to note that there will be no overlap of
adjacent parts of Fs(ω) as long as
‍ !s  2!m‍ (3.8)
If this condition is fulfilled, the passing of the signal fs(t) through a low-­pass filter
(see Figure 3.5(d)) with a bandwidth such that its cut-­off frequency ωc is given in
(3.9) results in a perfect digital reconstruction of the analogue signal f(t).
‍ !m  !c  !s  !m‍ (3.9)

3.4.2 Signal aliasing error

If the sampling rate is chosen so that the sampling frequency is less than twice
the maximum significant frequency contained in the original signal, that is, (3.1)
is not satisfied, then it can be seen from Figure 3.5(d) that there will be an over-
lap between adjacent parts of Fs(ω). This leads to what is commonly known as
an ‘aliasing error’, which in turn causes an error in the analysis as a result of the
difficulty in distinguishing between low- and high-­frequency components [9]. In
other words, if the sampling rate does not satisfy (3.1), a low-­frequency com-
ponent that does not actually exist in the original signal, would nevertheless be
apparent within the sampled signal. Figure 3.6 gives an illustration of the alias-
ing phenomenon, in which the dotted line represents a low frequency that does
not actually exist in the original signal.

3.4.3 Sample and hold circuit

If the sampling switch of Figure 3.5(a) is replaced by a switch–capacitor combina-
tion, each sample can be stored or held until the next sample is taken. This process
allows sufficient time to elapse for the subsequent process of analogue-­to-­digital
(A/D) conversion to be completed. Figure 3.7 shows the principles of a simple sam-
ple and hold circuit applied to the signal derived from the output of the signal-­
conditioning subsystem [10–12] (see Figure 3.1).
 Basic elements of digital protection 69

Figure 3.6   Simple illustration of aliasing phenomenon

Figure 3.7(a) shows a basic sample and hold circuit. The input is the analogue
signal f(t), which is sampled at a rate of 1/Ts. Sampling is controlled by the control
waveform Vc, which closes and opens the switch. During the closing time Tc, the
capacitor is charged to the value f(t), while during the hold time Th = Ts − Tc, the
capacitor holds the sample value. The process of sample and hold is best understood
by referring to Figure 3.7(b), (c) and (d). There are a variety of sample and hold
circuits available in integrated circuit form. However, virtually all commercially
available devices work on the principle outlined, their performance being defined
largely in terms of accuracy and sampling rates.

3.4.4 Digital multiplexing
A digital multiplexer is a network with a number of input ports channelled to a single
output [13–15]. The input to these ports consists of digital words of information of
one or more bits.
Figure 3.8 shows a general representation of a digital multiplexer that allows
one of its three inputs to pass to the output side, such that
   
YN = 0 if A, B = 0, 0
   
YN = I1 if A, B = 0, 1
    (3.10)
YN = I2 if A, B = 1, 0
   
‍ YN = I3 if A, B = 1, 1 ‍
70 Digital protection for power systems

Figure 3.7 Sample and hold circuit principle: (a) switching circuit, (b) analogue
input, (c) control waveform and (d) circuit output
 Basic elements of digital protection 71

Figure 3.8   Digital multiplexer arrangement

where
 
YN = Y0 , Y1 , : : : Yn is the output
 
I1 = Y01 , Y11 , : : : Yn1 is the first input
 
I2 = Y02 , Y12 , : : : Yn2 is the second input
 
‍ I3 = Y03 , Y13 , : : : Yn3 is the third input ‍

Figure 3.9 shows a typical logic diagram for a two-­input-­to-­one-­output multiplexer.

The input word ‍ Y1 ‍, which consists in this case of four bits (Y01, Y11, Y21, Y31), is
transferred to the output ‍YN ‍  if the control signal (address) A is low. On the other hand,
when the address signal A is high, then the input ‍ Y2 ‍ is transferred to the output‍Y. N‍

3.4.5 Digital-to-analogue conversion
Consider first the method of converting a digital representation to analogue form.
The reason for this is that digital-­to-­analogue (D/A) converters are frequently used
in A/D converters. The principles involved are well illustrated by considering the
circuit of Figure 3.10 [12–16]. This may be used to convert a four-­bit binary parallel
digital word W3W2W1W0, where any Wi is either 0 or 1, to an analogue voltage that is
proportional to the binary number represented by the digital word. The logic voltages
that represent any individual bit Wi, are, as a matter of fact, not connected to the con-
verter but rather are used to control the switches S0, S1, S2 and S3. Therefore, if Wi = 1,
then Si is connected to VR while if Wi = 0, then Si is connected to ground.
The values of the circuit elements are chosen so that successive resistors on the
input side are related in powers of 2, and the individual resistors are inversely pro-
portional to the numerical significance of the appropriate binary digit (Figure 3.10).
72 Digital protection for power systems

Figure 3.9 Logic circuit for two input/one output multiplexer

Remembering that the input impedance of the operational amplifier is very high,
the currents Is and If are roughly equal to each other. The relationship between the
output voltage of the operational amplifier (Vo) and the digital input can be found
as follows:
 
‍ IS = 23 W3 + 22 W2 + 21 W1 + 20 W0 VR /R‍ (3.11)
Vo = If Rf = Is Rf
  (3.12)
‍ =  23 W3 + 22 W2 + 21 W1 + 20 W0 VR Rf /R‍

It is clear from (3.12) that the output signal voltage Vo is directly proportional to the
binary number W3W2W1W0. For illustrative purposes, assume that the binary input
array corresponds to 15 (decimal), that is, W3W2W1W0 = 1111; in this case, the out-
put is proportional to (23 + 22 + 21 + 20) = 15 as required. Similarly, an input word
of 0011 would give an output proportional to (0 + 0 + 21 + 20), corresponding to the
input number 3.
 Basic elements of digital protection 73

Figure 3.10 Basis of simple D/A converter arrangement

3.4.6 A/D conversion

The block schematic of an A/D converter is shown in Figure 3.11, where Va is the
analogue voltage input and W ‍N ‍is the digital output array. For simplicity, a four-­bit
word converter giving an output array W3W2W1W0 is shown. In the field of digital
integrated electronics, many methods have been developed for converting analogue
signals to digital form, the most commonly used being counter-­controlled convert-
ers, dual-­slope converters and parallel-­comparator converters.

Figure 3.11 Block diagram of A/D converter

74 Digital protection for power systems

Figure 3.12 Counter-­controlled converter: (a) circuit arrangement and

(b) illustrative response

3.4.6.1 Counter-controlled converter
This technique represents one of the simplest methods of A/D conversion. Figure 3.12
shows the basic arrangement involved. It consists of three main components: a
 Basic elements of digital protection 75

counter, a D/A converter and an analogue comparator. Its operating principles may
be summarised as follows. The counter is set to zero at the beginning of each cycle,
which causes the output of the D/A converter Vc to be zero. This latter voltage is
compared with the input voltage Vi fed by the sample and hold circuit, using the
comparator whose output will be either 1 or 0 depending on the relative magnitudes
of Vi and Vc. If Vi > Vc, then the comparator output will be 1, which is used to enable
the AND gate. This in turn allows the clock pulses to enter the counter.
Each pulse entered in the counter causes the output voltage of the A/D con-
verter to increase by a single step of 1 V, as shown in Figure 3.12(b). As soon as Vc
becomes greater than Vi, that is, Vi < Vc, the output of the comparator will be zero.
This disables the AND gate, and the clock pulses are thereafter prevented from
reaching the counter, which then stops. The output of the A/D converter is then read
from the output terminals of the counter. The example illustrated in Figure 3.12
involves an analogue input voltage that is marginally above five quantum levels and
is identified as the equivalent binary number 0101. The resolution of the counter
is controlled by the gain on the D/A converter, while the dynamic range is largely
dictated by the number of binary stages within the counter. In relay applications,
quantum levels between 5 and 300 μV are fairly common, the precise level being
a function of dynamic range requirements. This type of counter is useful in some
applications but has limited speed for a given resolution.

3.4.6.2 Dual-slope converter
This converter basically consists of an analogue integrator, a comparator and a coun-
ter. Its operating principle is best understood by reference to Figure 3.13.
At time t = 0, the switch S1 is connected to A, and the sample and hold voltage
Va is applied to the analogue integrator, which integrates Va for a fixed time T1. After
that the switch S1 is thrown to B, which in turn connects a negative reference volt-
age −Vr to the integrator. Therefore, the reference voltage will be integrated, and the
output of the integrator starts to move in the positive direction (Figure 3.13(b)). As
soon as the integrator output voltage Vc reaches zero, the gate G is disabled, and
this in turn stops the clock pulses from reaching the counter, thereby stopping the
count. The number of clock pulses admitted to the counter is thus proportional to the
magnitude of the input voltage Va which is thereby converted to a digital representa-
tion. In practice, the reset voltage Vr is arranged to stop the count quickly. This type
of converter is characterised by a high accuracy, but it does have a relatively slow
conversion rate, which limits its application in some digital relaying devices.

3.4.6.3 Parallel-comparator converter
Figure 3.14 illustrates a three-­bit parallel-­comparator A/D converter. It consists of
comparators C1–C7, a register of seven flipflops and a decoder.
The input ranges from 0 to Vo and is divided into eight reference segments, six
of which have a value of Vo/7 and the two end segments having a value of Vo/14
each. If an input voltage Vi, with magnitude ranging from 0 to Vo/14, is applied to the
converter, then the outputs of all comparators C1–C7 are set to logical 0. The digital
76 Digital protection for power systems

Figure 3.13   Dual-­slope converter

representation of this at the output of the converter is seen to be 000. This is equiva-
lent, as required, to a zero analogue voltage. It will be noted that an error of Vo/14
is introduced on account of the input being equal to one level of resolution (Vo/14).
This is often called a ‘quantisation’ error.
If the input voltage magnitude is between Vo/14 and 3Vo/14, then the output of all
the comparators is zero, except the first one which will be 1, that is, C1C2C3C4C5C6C7 =
1000000. The output of the comparators is transferred to the register flipflops at the
occurrence of a clock pulse and the register output is converted by the decoder to a
three-­bit unipolar binary code.
 Basic elements of digital protection 77

Figure 3.14 Parallel-­comparator converter, where LSB = least significant bit

and MSB = most significant bit

3.5 Digital relay subsystem

The digital relay subsystem comprises both hardware and software [5, 6, 17]. The
hardware largely consists of a central processor unit, memory, data input and output.
The software is influenced by two major factors. The first of these is the operating
78 Digital protection for power systems

Figure 3.15  Flow chart for the software of a digital protective relay, where DI =
digital data input

principles and performance required, which either leads to the development of a spe-
cial algorithm or the implementation of an existing one. This factor greatly affects
the determination of the sampling frequency, type of hardware structure and the data
input hardware system.
The second factor is the digital filtering. Subharmonics, as well as high-­harmonic
components, can cause false tripping, failure to trip and variation in protective relay
performance. The operating principle and digital filtering must, in general, provide
for a wide application range and requirements relating to speed of response to sys-
tem faults, the latter being influenced by the necessary computation time.
Figure 3.15 shows an example of a flow chart for the software of a typical digital
protective relay. The algorithms used and the software required vary significantly
according to the application, and much of the work of later chapters will be con-
cerned with specific algorithms for meeting a variety of protection performance and
application requirements.

3.6 Microprocessor-based digital relay

Figure 3.16 shows the block diagram of a microprocessor-­based digital relay [18,
19]. As the figure shows, the relay basically is a microcomputer, whose voltage and
current signals are fed from the electric power system through voltage and current
transducers. These transducers reduce the magnitudes of voltage and current signals
 Basic elements of digital protection 79

Figure 3.16 A block diagram of a microprocessor-­based digital relay, where

RAM = random access memory, and ROM = read-­only memory

from their primary values, which could be in the range of kilovolts and kiloamperes,
respectively, to the standard secondary voltage values of 110 or 67 V and standard
secondary current values of 5 or 1 A.
The outputs of instrument transformers are fed to the analogue input subsystem
of the relay, which acts as an electrical buffer between the relay and the power sys-
tem. This subsystem also reduces the level of input voltages, converts currents to
equivalent voltages and removes high-­frequency components from the signals using
analogue filters. The output of the analogue filter subsystem is fed to the analogue
80 Digital protection for power systems

interface of the microcomputer, as seen in Figure 3.16. The reduced level analogue
signals are then sampled and converted to binary numbers that are stored in memory.
The obtained information is processed by an appropriate relaying algorithm,
which constitutes the part of the software. The type of the algorithm used depends
on the required function of the relay. For example, in case of an impedance relay, the
algorithm is designed to determine the impedance of line, protected by the relay, to
the fault point. In case of a fault on the line, the relay sends a trip signal to open one
or more circuit breakers (CBs) to isolate the faulted zone of power system. The trip
signal is sent to the relevant CBs through the digital output subsystem.
The relay settings and other vital information are stored in non-­volatile memory
of the relay. Random access memory is used to temporarily store data.
It is vitally important to make sure that the power supply to the relay is made
available even when the system supply is interrupted. This is achieved by providing
an arrangement that ensures the provision of energy to the relay during normal and
abnormal operating conditions of the power system. This arrangement is represented
by the independent ‘power supply’ shown in Figure 3.16.
The relay is provided by communication capability with other devices, as it can
be seen in Figure 3.16.

3.7 Summary

The basic elements of a digital protection are discussed in this chapter. Power sys-
tem operating voltages and currents are first reduced to acceptable level before feed-
ing them to the relay. This is followed by converting the analogue signals to digital
form, which allows subsequent digital processing to be performed to determine the
state of the protected circuit.
The basic components of a digital relay are highlighted in section 3.2. Signal
conditioning subsystems are discussed in section 3.3. These subsystems include
transducers, surge protection circuits, analogue filtering and analogue multiplexers.
This is followed by discussing conversion subsystem in section 3.4, which includes
the sampling theorem, signal aliasing error, sample and hold circuit, digital multi-
plexing, D/A conversion and A/D conversion. The digital relay subsystem is dis-
cussed in section 3.5, which comprises both hardware and software. Finally, the
block diagram of a microprocessor-­based digital relay is presented and discussed in
section 3.6.

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