ASIC & FPGA Chip Design:

Synthesis
Outline

 Introduction to Synthesis
 Digital Logic Basics
 Logic Optimization
 Two‐level logic synthesis
 Multi‐level logic synthesis
 Technology Mapping
 Boolean Satisfiability
 ASIC/FPGA‐oriented Te hnology Mapping

2
Outline

 Introduction to Synthesis
 Digital Logic Basics
 Logic Optimization
 Two‐level logic synthesis
 Multi‐level logic synthesis
 Technology Mapping
 Boolean Satisfiability
 ASIC/FPGA‐oriented Te hnology Mapping

3
Synthesis
 Synthesis = Translation + Logic O ptimization + Technology Mapping
 Translation: going from RTL to Boolean function
 Logic Optimization : Optimizing and minimizing Boolean function
 Technology Mapping (TM): Map the Boolean function to the target library
Synthesis
 Synthesis = Translation + Logic O ptimization + Technology Mapping

Translation

always @ (a, b) FPGA

case ({a,b}) out  ab  ab  a b
2’b00: out = 1;
2’b01: out = 1;
2’b11: out = 1; Logic
default: out = 0; Optimization
endcase
Technology
out  a b Mapping

ASIC
Outline

 Introduction to Synthesis
 Digital Logic Basics
 Logic Optimization
 Two‐level logic synthesis
 Multi‐level logic synthesis
 Technology Mapping
 Boolean Satisfiability
 ASIC/FPGA‐oriented Te hnology Mapping

6
Digital Logic Basics : Bool ean Function
 Digital Logic Basics
 A Boolean function can be represented by:
 A truth table

 A logic expression
 We use logic variables and operat rs (AND, OR, NOT, XOR, XNOR, NAND, NOR)
to express a logical relation b/w input variables and the output function

f  x1 x2
Digital Logic Basics : SOP
 Sum of Products (SOP):
 A logic function that is represented as an OR of product (AND) terms :

f(x1 ,x 2 ,x 3 )  x1  x2x3  x1x2x3

Literal
cube minterm

 A literal is a function input (e.g., x1 ,x2 ).

 A product term is formed using an AND operation and literals in either true
or complemented form.
 A cube is the AND of set of literals
 A minterm is a cube that contains all literals of a logic function
o A function with K variables has 2K possible K‐literal minterms
 A cover of “f” is a set of cubes that represent the logic function “f”
o (e.g., C  {x1 ,x 2 x 3 , x1x2x3 } )
Digital Logic Basics : POS
 Product of Sums (POS):
 A logic function that is represented as an AND of sum (OR) terms :

f  (x1  x2 )( 3  x2 )
 A sum term is formed using an OR operation and literals in either true
or complemented form.
 A maxterm is a sum term that contains all literals of a logic function

 POS can be derived from SOP by DeMorgan’s Theorem and double complementation
Digital Logic Basics : Karn augh Map
 Karnaugh Map:
 Variables assigned to rows and columns.
 Adjacent valuations differ by 1 posit on.
 Form product terms by creating groups with 2k 1s that are adjacent to one another

f bd ab acd bcd
Digital Logic Basics : Impl ementation Cost
 Cost of an Implementation:

Cost of implementation = # of i puts + # of gates (except NOTs)

 Example:
f  bd  ab c  acd  bcd
3 4 4 4

 Cost = 3 + 4 + 4 + 4 + 5 = 20
Digital Logic Basics : Canonical Form
 Canonical Form:
 A form of Boolean logic function representation is said to be canonical if and only if
for each logic function there exists a unique representation in the given form
 Function is described using its equivalent minterms
 Example:
 Canonical f(a,b,c)  abc  abc

 Non‐canonical f(a,b,c)  bc  abc  bc

 Because it has a cube that does not include all the literals

 Any Boolean logic can be represented in a canonical form

Outline

 Introduction to Synthesis
 Digital Logic Basics
 Logic Optimization
 Two‐level logic synthesis
 Multi‐level logic synthesis
 Technology Mapping
 Boolean Satisfiability
 ASIC/FPGA‐oriented Te hnology Mapping

14
Two‐Level Logic Synthesis : Cubical Notation
 Cubical Notation:
 A different way to represent a product term
 “0” : to represent inverted varia le
 “1” : to represent a variable in true form
 “X” : to represent a variable not used in the product term

bd f = {X1X1, 100X, 0X10, X010}

abc
acd
(Easier to implement in a computer program)
bcd
Two‐Level Logic Synthesis : Cubical Notation
 Cubical Notation:
 A different way to represent a product term
 “0” : to represent inverted varia le
 “1” : to represent a variable in true form
 “X” : to represent a variable not used in the product term

bd f = {X1X1, 100X, 0X10, X010}

abc
acd
(Easier to implement in a computer program)
bcd
Two‐Level Logic Synthesis: Quine‐McCluskey Method
 How do we use cubical notation to synthesize logic functions?
 Quine‐McCluskey method
 Willard Quine (1908‐2000)) and Edward McCluskey (1928‐present)

 Quine‐McCluskey method: (2 Stages)

Stage I : Take minterms for a function (Canonical) and form Prime Implicants (PIs).
Stage II : Pick minimum Prime Implica nts to generate a cover.

A cover of a function is a set of cu es that

represent that logic function Quine‐McCluskey

Stage I Stage II

Step 1 Step 2 Step 3 Step 4

Q-M Tabular Minimization Method
Q-M Tabular Minimization Method
Quine‐McCluskey Method :

f(a,b,c,d)=  m(2,4,6,8,9,10,12,13,15)

cd
ab 00 01 11 10

00 1

01 1 1

11 1 1 1

10 1 1 1
Q-M Tabular Minimization Method

Minterms abcd
2 0010
4 0100 Group 1 (a single 1)
8 1000
6 0110
9 1001 Group 2 (two 1’s)
10 1010
12 1100
13 1101 Group 3 (three 1’s)
15 1111 Group 4 (four 1’s)
Q-M Tabular Minimization Method
Minterms abcd Minterms abcd Minterms abcd
2 0010 2,6 0-10 PI2 8,9,12,13 1-0- PI1
4 0100 2,10 -010 PI3
8 1000 4,6 01-0 PI4
6 0110 4,12 -100 PI5
9 1001 8,9 100-
10 1010 8,10 10-0 PI6
12 1100 8,12 1-00
13 1101 9,13 1-01
15 1111 12,13 110-
13,15 11-1 PI7
Q-M Tabular Minimization Method

2 4 6 8 9 10 12 13 15
PI1 * * * *
PI2 * *
PI3 * *
PI4 * *
PI5 * *
PI6 * *
PI7 * *
Q-M Tabular Minimization Method

2 4 6 10
PI2 * *
PI3 * *
PI4 * *
PI5 *
PI6 *
Q-M Tabular Minimization Method

f(a,b,c,d)= PI1 + PI3 +PI4 + PI7

=1-0- + -010 + 01-0 + 11-1

= a.c’ + b’.c.d’+ a’.b.d’+ a.b.d

 Quine‐McCluskey Method : Summary

1. Generate all PIs starting with minterms

2. Create a prime implicant covering tab e. List PIs in the rows and function
minterms in the columns.
3. For each PI indicate which minterms it covers by putting a checkmark
in the corresponding column.
4. For each column covered by exactly one PI add the corresponding PI to your cover,
removing the PI from the table, as well as any columns it covers.
5. Apply concepts of row and column dominance to reduce the table.
6. Repeat steps 4‐6 until the table cannot be further reduced.
Outline

 Introduction to Synthesis
 Digital Logic Basics
 Logic Optimization
 Two‐level logic synthesis
 Multi‐level logic synthesis
 Technology Mapping
 Boolean Satisfiability
 ASIC/FPGA‐oriented Te hnology Mapping

35
Multi‐Level Logic Synthesi s
 Two‐level logic synthesis is effective and mature
 Two‐level logic synthesis is directly applicable to PLAs and PLDs

However, …
 There are many functions that are too expensive to implement in
two‐level forms (too many product terms!)
 Two‐level implementation constrains layout (AND‐plane, OR‐plane)
Multi‐level logic synthesis may be employed

 Rule of thumb:
 Two‐level logic is good for contr ol logic
 Multi‐level logic is good for data path or random logic
Multi‐Level Logic Synthesi s
 Multi‐level logic synthesis:
 Decompose a logic function into smaller functions
 A simple tool to do this is called Shannon’s Decomposition
 Claude Shannon 1916‐2001
 Shannon’s Expansion Theorem:

Any logic function f(x1, x2, …, xn) can be expanded in the form of:
xk . f(x1 , x2 , xk‐1 ,1,x k1 ,, x n )  xk . f(x1 , x2 , xk‐1 ,0,x k1 ,, xn )
 xk . fX  xk . f
K XK

fx  f(xk  1,...) : 1‐ cofactor

k

 fx
k
 f(xk  0,...): 0‐ cofactor
 Multi‐Level Logic Synthesi s
 Example:
 F(A, B, C) = A’B + ABC’ + A’B’C
= A(BC’) + A’(B+B’C) = A. 1 + A’.F2

 F2 = B+B’C = B.1 + B’.C

 F1 = BC’ = BC’ + B’.0

 Multi‐Level Logic Synthesi s
x3 x3x4
 Example: x4 0
0
x3+x4 f
1
1
x1
x2

 We found out that logic expression (x +x4) appears in multiple places. Hence,
this knowledge could be used to simplify the implementation of this circuit.
 Keeping track of this type of relationships in a logic function can be tedious in a
large expression.
 Can we represent this information in a better way?
 Yes, we can use Binary Decision Diagrams (BDDs)
Binary Decision Decomposition (BDD)
 Let us decompose a function “f=x1x2” with respect to x1:

f  x1 . fX  x1 . fX
1 1

 x1 .(x 2 )  x1 . (0)
 x1 . x2 (1  x2 (0  x1 . (0 x1
1‐cofactor
0 1
0‐cofactor

0 x2
0 1
0‐cofactor

0 1

1‐cofactor
Binary Decision Decomposition (BDD)
 To derive the function from BDD, start from the bottom to top
 Start only with terminal nodes 1
 If see edge “1” use the variable otherwise its complement

x1 x1
0 1
0 1

0 x2 0 x2
0 1
0 1

1 1 0
0

f = x1x2 f  x1 x2
 Binary Decision Decomposition (BDD)
 A binary decision diagram represents a logic function by using Shannon’s
decomposition to decompose a function into cofactors, one variable at a
time:
f  x k . fX  xk. fX
k k

 The decomposition steps are then represented as a directed graph

G = (V,E), where:
 V is a set of vertices. Each verte is associated with a variable or a
constant 0/1.
 E is a set of directed edges. Each edge is assigned a label of 0 or 1. A
0 edge always points to a 0‐cofa ctor and a 1 edge points to a 1‐cofactor.
Binary Decision Decomposition (BDD)
 BDD of some basic logic functions:

x1 x1 x1
0 1 1 0 1 0

0 x2 1 x2 x2 x2
1 0 0
0 1 0 1 1

0 1 0 1 0 1

f = x1x2 f = x1+x2 f  x1  x2
 BDD: Decomposition Order Matters
 Example: f  x1  x 2 x 3  x1 (1)  x1 x2x3

x1 → x2 →x3

x1

Cost : 4 + 3 = 7
 BDD: Decomposition Order Matters
 Example: f  x1  x2x3  x2 (x1  x3 )  x2 (x1 )

x2 → x3 →x1

x2

Cost : 3 + 3 + 3 + 3 = 12

Different order of decompo ition => different size/cost of the diagram

 Ordered Binary Decision Decomposition (OBDD)
 We could impose a decomposition ord er by fixing the sequence of variable with
respect to which we decompose a function (Ordered BDD = OBDD)
 Let us consider the following function:

f  x2 (x3  x 4 )  x2 x1 (x3x4 )  x1 (x3  x 4 )

 Reducing OBDDs
 Similar structure can be used to reduce the OBDD

Two edges means it is

being used two times
 Reducing OBDDs
 Cost of this OBDD:

f  x4x3x1x2  (x4  x3)(x1  x2)

Cost : 5 + 3 + 3 + 3 + 3 = 17
 Reduced Ordered BDD (ROBDD)
 Bottom‐up merging of the isomorphic graphs together to simplify the OBDD
into a Reduced Ordered BDD (ROBDD)
Reduced Ordered BDD (ROBDD)
 Thus, bottom‐up merging the graphs together will reduce the cost

(x1 + x2 )

f  x4 x3 x1 x2  (x3  x4 )(x1  x2 )
x4x3x1x2
Cost : 5 + 3 + 3 + 3 + 3 = 17

(x4 + x3 )
Reduced Ordered BDD (ROBDD)
 Example: f  x1  x2  x3
Reduced Ordered BDD (ROBDD)
 Example: f  x1  x2  x3

15 nodes 7 nodes
 BDD of f <op> g
 Goal: take BDDs for functions “f” and “ g ” and produce a BDD for f <op> g.
 Case 1: functions f and g have distinct support (i.e., sup(f)  sup(g)  φ )
 Example:

f  ab g  cd

a c
0 1

1 0
b d
1 0 0 1

1 0 1 0
BDD of (f . g)
 BDD of h = f.g?
a
0

a 1
b
0
1
1 0
b c
1 0
1

0 0
g d
0 1

1 0
BDD of (f + g)
 BDD of h = f+g?
a
0

a 1
b
0 0
1
1
b c
1 0 1

0
1 g d
1
0

1 0
BDD of (h  f  g )
 BDD of h  f  g  fg  fg ? a
0

a 1
b
0 0
1
1
b c c
1 1
1 0
0 0
d d
g g
1
0 1 0

0 1 0

When the support of “f” and the support of “g” are disjoint, then
replace terminals of f with 0, 1, g, or g
Boolean Satisfiability: Theory
 Boolean Satisfiability: (a.k.a SAT Problem)
 A Boolean expression in a conjunctive normal form (CNF):
f(x1 , x2 ,, xn) (x 1  x2  x3 )(x 4  x5  x6 )(x7  x1  x8 )()
is satisfiable if and only if there exists a valuation for variables
(x1, x2, …, xn) such that f=1.
 Example: Is the following function satisfiable?
f (x1 x2 ) (x1 x3 (x1 x3 )(x1 x3 )

Try: x1=1 1 1 x3=1 x3=0 × Conflict!

Try: x1=0 x2=1 x3=1 1 1 🗸Satisfiable!

“f” is satisfiable.
Boolean Satisfiability: Theory
 2‐SAT:
 Boolean satisfiability problem w here each sum term consists of no more
than 2 literals
 3‐SAT:
 Boolean satisfiability problem w here each sum term consists of no more
than 3 literals
 If there are n variables in “f”, (i.e., (x 1, x2, …, xn) ), we have to search over 2n
possible cases to verify satisfiability!
NP‐complete problem, i.e., non‐deterministic polynomial time complete

 Is there any better way?

 YES using dynamic programming algorithm based on Implication graphs.
 Boolean Satisfiability: Implication Graph
 Implication Graph:
 An implication graph consists of
 Nodes: which represent a variable and its assignments
 Edges: which indicate an implication

 Example:
f  (a  b  c)(a  c  d)(a  c  d)(a  c  d)(a  c  d)(b  c  d)(a  b  c)(a  b  c)
🗸 🗸 🗸 🗸 🗸 🗸 🗸 🗸

Satisfiable!
(SAT)
 Boolean Satisfiability: Implication Graph
 Implication Graph:

f  (a  b  c)(a  c  d)(a  c  d)(a  c  d)(  c  d)(b  c  d)(a  b  c)(a  b  c)

🗸 🗸 🗸 🗸 🗸 🗸 🗸 🗸

Conflict!
 Boolean Satisfiability: Implication Graph
f  (x1  x4 )(x1  x3  x8 )(x1  x8  x12 )(x2  x11 )(x7  x3  x9 )(x7  x8  x9 )(x7  x8  x10 )(x7  x10  x12 )
🗸 🗸 🗸
 Idea:
 Assign a variable such that it simplifies the largest number of clauses
(removes literal from a claus )
 Draw an implication graph
 Step 1: x1=0 x4=1 4

 Step 2: x3=1 x8=0

4
12

3 8
 Boolean Satisfiability: Implication Graph
f  (x1  x4 )(x1  x3  x8 )(x1  x8  x12 )(x2  x11 )(x7  x3  x9 )(x7  x8  x9 )(x7  x8  x10 )(x7  x10  x12 )
🗸 🗸 🗸 🗸 🗸
 Step 3: x7 =1 🗸 (x1  x 4 )
4
12 🗸 (x1  x3  x8 )
1 🗸 (x1  x8  x12 )
(x2  x11 )
3 8
🗸 (x7  x3  x9 )
🗸 (x7  x8  x9 )
9

Conflict : x 7 x 3 x 8 (x7  x8  x10 )

(x7  x10  x12 )
7 9

This will be 1 when

Conflict Clause: x7 x 3 x 8   (x 7  x3  x 8 ) x 7  1 or x 3  1 or x 8  0
So does not change the function
 Boolean Satisfiability: Implication Graph
 When a conflict clause is found: 🗸 (x1  x4 )
 Add the conflict clause to f 🗸 (x1  x3  x8 )
 Does not the conflict to happen again 🗸 (x1  x 8  x12 )
 Backtrack to the point where we first assigned one of the (x2  x11 )
variables in the conflict clause (x7  x3  x9 )
 So we should go back to step 2 where x3=1: (x7  x8  x9 )
🗸 (x7  x8  x10 )
🗸 (x7  x10  x12 )
‐‐‐‐‐‐‐‐‐‐‐‐
🗸 (x7  x8  x3 )
(x7  x8  x12 )

Conflict : x7x12x8
Conflict Clause:x7  x12  x8
Boolean Satisfiability: Implication Graph
Note: no variable that was previously set is present in the conflict 🗸 (x 1  x4 )
clause. Therefore, the current branch is unsatisfiable, so explore 🗸 (x1  x3  x8 )
the other branch, i.e., x3=0. 🗸 (x1  x8  x12
 Also set x7=0, which does not force anything (x2  x11 )
 So set x8=0 then conflict! 🗸 (x7  x3  x9 )
🗸 (x7  x8  x9 )
🗸 (x7  x8  x10
(x7  x10  x1
‐‐‐‐‐‐‐‐‐‐‐
Conflict : x7 x1x8 🗸 (x7  x8  x3 )
🗸 (x7  x8  x12
Conflict Clause: x7  x1  x8
Boolean Satisfiability: Implication Graph
 Go back to x1=0, x3=0, x7=0. 🗸 (x1  x4 )
 Set x2=0 🗸 (x1  x3  x8 )
 Set x10=0 🗸 (x1  x8  x12
🗸 (x2  x11 )
🗸 (x7  x3  x9 )
🗸 (x7  x8  x9 )
🗸(x7  x8  x10
🗸 (x7  x10  x12
‐‐‐‐‐‐‐‐‐‐‐

Satisfiable! 🗸(x7  x8  x3 )
(SAT) 🗸(x7  x8  x12
🗸(x7  x8  x1 )
We explored 12 cas s of 212=4096 possible cases!
 Boolean Satisfiability: SAT Solvers
 Go back to our question.
 Given a logic structure can we implement a given logic expression within it?
 Characteristic Equation (CE):
 A logical expression that takes as inputs all literals of a function as well as its
output, and it produces a “1” iff for a given set of inputs the output is correct
 Example: Dose G = f ?
Characteristic Equation

F  (x2  G)(x1  G)(x1  x2  G)

If we substitute (x1+x2) for G then F=1

Thus, F is SAT so G implements an OR function
 Boolean Satisfiability: SAT Solvers
 Characteristic Equation (CE) for a Logic Network:
 Divide‐and‐Conquer
 Create a CE for each gate
 Combine CEs for gates to form a CE for the network
x2 x3 z FAND
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0 FOR  (z G)(x 1  G)(x 1  z  G)
1 0 0 1
1
1
0
1
1
0
0
0
FAND  (x 3  z)(x 2  z)(x 3  x2  z)
1 1 1 1

F  FOR FAND  (x3  z)(x2  z)(x3  x2  z)(z  G)(x1  G)(x1  z  G)

 Boolean Satisfiability: SAT Solvers
 SAT Theorem:
 In order for a given logic network, represented by a characteristic
equation F, to be equivalent to a logic function H, then for all xis,
F(G=H) must be SAT.

 Example: Assume H = x1+x2, find out if G = H ?

 This question is equivalent to see if F(G= x1+x2) is SAT for all x1,x2 ,x3 values?


F G
x1 x 2
 (x 3
 z)(x  z)(x  x  z)(z  x  x )(x  (x  x ))(x  z  (x  x ))
2 3 2 1 2 1 1 2 1 1 2

x3 0 F x1 x1x2 (Not SAT for all x1, x2 values)

So we can NOT imple ment an OR function in F

 SAT Theorem

 SAT Theorem:

Characteristic Equation F represents H if and only if:

i, j, xi z j F(G  H) : SAT

 xi : Literals
 zj : Internal wires
Quantified SAT (QSAT) Problem:

SAT Problem QSAT Problem

Question: Question:

Can F(G) implement H Can F(G) implement

for all x1,x2 ,x3 values? H=x1+x2 for all x1,x2
values by adjusting B0?
 Quantified SAT (QSAT) Problem:
 Step 1: Generate CE for F(G):
F  (B0  z)(x2  z)(B0  x2  z)(z  G)(x1  G)(x1  z  G)
 Step 2: For each valuation of x1, x2, determine what B0 should be in order
for G to implement H

 i) Fx x (G)  (B0  z)(z)(1)(z  G)(1)(z  G)

1 2

H(x1  0, x2  0)  0 G 0 z0 B0 : don’t care

 ii) Fx x  (B0  z)(1)( B0  z)(z  G)(1)(z  G)

1 2

H(x1  0, x2  1)  1 G1 z 1 B0  1
 Quantified SAT (QSAT) Problem:
 Step 2, Cont’d:

 iii) Fx x  (B0  z)(z)(1)(z  G)(G)(1)

1 2

H(x1  1, x2  0)  1 G1 z0 B0 : don’t care

 iv) Fx x (G)  (B0  z)(B 0  z)(1)(z  G)(G)(1)

1 2

H(x1  1, x2  1)  1 G1 z 1 B0  1 SAT

z0 B0  0
Contradicts the results from Fx x
1 2

All Fs are SAT and B0 =1 is the consistent solution

Quantified SAT (QSAT) Problem:

QSAT Problem

Question: Answer:

Can F(G) implement

H=x1+x2 for all x1,x2 YES for B0=1
values by adjusting B0?
 Boolean Satisfiability: SAT Solvers
 Can we solve this problem with a single equation?
 Yes, solve SAT for
F Fx1 x2 Fx1x 2 Fx1x 2 Fx1x 2
 G is replaced with H(x1, x2)
Note that signal z should be rep icated as
 z1 for Fx x
1 2
 z2 for Fx x
1 2
 z3 for Fx x
1 2
 z4 for Fx x
1 2

 This is b/c z is an intermediate vari able and based on the above calculations z
results in a conflict
 The choice of B0=1 will be resolve d due to conflict clauses
 QSAT Theorem

 QSAT Theorem:

Characteristic Equation F represents H if and only if:

i, j, k, Bkxi z j F(G  H) : SAT

 xi : Literals
 zj : Internal wires
QSAT Theorem
 Can we implement function H = x1+x2 into:
x1 x2

B0 0 G

B1 1

 We are looking for a value for B0 and a value for B1

 Step 1: Represent G as a logic expression. This expression is the
characteristic equation x1

B0 0
z
B1 1
QSAT Theorem
 Step 1: Represent MUX as a logic expression. This expression is the
characteristic equation of the MUX B B x z F
x1 0 1 1 MUX

I) B0  x1  z B0 0
0 0 0 0 1
0 0 0 1 0 I
z 0 0 1 0 1
II) B1  x1  z B1 1
0
0
0
1
1
0
1
0
0
1
0 1 0 1 0 II
0 1 1 0 0
III) B0  x1  z 0 1 1 1 1 IV
1 0 0 0 0
1 0 0 1 1
III
IV) B1  x1  z 1
1
0
0
1
1
0
1
1
0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

FMUX  (B0  x1  z)(B1  x1  z)(B0  x1  z)(B1  x1  z)

 Boolean Satisfiability: SAT Solvers

FOR  (x2  G)(z  G)(z  x2  G)

 Thus the complete characteristic equa ion for the logic structure is:
F  (B0  x1  z)(B1  x1  z)(B0  x1  z)(B1  x1  z)(x2  z  G)(x 2  G)(z  G)
 Step2: Take F and see if a given logic expression can be implemented in it.
This means that we need to find a value for B0 and B1 such that for all x1, x2
values, B0 and B1 are consistent.
 Quantified SAT (QSAT) Problem:
 Step 2: For each valuation of x1, x2, determine what B0 and B1 should be in
order for G to implement H = x1+x2

i) Fx x (G)  (B0  z1 )(1)(B0  z1 )(1)(z1  G)(1)(z1  G)

1 2

G has to be equal to H, i.e., 0

G0 z1  0 B0  0 H  0 🗸

 ii) Fx x  (1)(B1  z2 )(1)(B1  z2 )(z2  G)(1)(z2  G)

1 2

G has to be equal to H, i.e., 1

G1 z2  1 B1  1 H1 🗸
Quantified SAT (QSAT) Problem:

 iii) Fx x (G)  (B0  z3 )(1)(B0 z3 )(1)(1)(G)(z3  G)

1 2

H1 G1 z3  0 B0  0 🗸

 iv) Fx x  (1)(B1  z4 )(1)(B1  z4 )(1)(G)(z4  G)

1 2

H1 G1
B1  1 z4  1 🗸 No surprise as when
x1=1 then z4 has to be
B1  0 z4 0 × equal to B 1

Find a consistent value: B1 = 1 and B0 = 0

Quantified SAT (QSAT) Problem:

x1 x2

B0 0 G

B1 1

Question: Answer:

Can F(G) implement

H=x1+x2 for all x1,x2 YES for B0=0 and B1=1
values by adjusting B0?
Outline

 Introduction to Synthesis
 Digital Logic Basics
 Logic Optimization
 Two‐level logic synthesis
 Multi‐level logic synthesis
 Technology Mapping
 Boolean Satisfiability
 ASIC/FPGA‐oriented Te hnology Mapping

85
Logic Synthesis

 Logic synthesis normally in two steps:

 Technology independent
 Manipulate equations
 Optimize the logic equatio s
 Independent of target IC media

 Technology dependent (Tech ology Mapping (TM))

 Equations are turned into netlist of the available gates
Technology Mapping
 Problem Definition:
 Given:
1. Boolean network G(v,e), where
v  V : represent logic functions
e E : represent depe ndencies between logic functions
2. Library of available gates

 Find:
 Netlist of gates from libr ary that implements logic function G
so as to minimize some of the following metrics:
o Area
o Delay
o Power
o Defect
Technology Mapping (TM)
 Example: Implement function y=t(a+g) given the following library
Area Delay
Library Element
(sq units) (nsec)

INV 3 1 ns

AND 8 2.5 ns

6 2 ns
NAND

OR 8 2.5 ns

25 4 ns
AND‐OR
Technology Mapping (TM)
 Possible Implementations:
Area Delay
t
a 25 4 Best Delay
g

t
a 16 5 Best Area
g

t
a 17 5.5
g

 This is a small function with small library 3 choices

 Larger designs + libraries many more choices
Technology Mapping (TM)
 Algorithmic approach to TM (DAGON Keutzer 80s)
1. Take input Boolean network and do a simple mapping into a network
of “base functions ” to create a “subject graph”
e.g., 2‐input NANDs + inver ters

a
b
F  de(a  b)
 de  (a b)
d
e

“Subject Network”
G(V,E)
 Technology Mapping (TM)
 Algorithmic approach to TM (DAGON Keutzer 80s)
2. Take gates in library and cre ate a “pattern graph” for each that is
functionally equivalent and expressed in the same base functions
Gate Pattern Graph

P1(V1,E1)

P2(V2,E2)

In case there are alternatives,

Different implementations have add all of the pattern graphs
different area/delay properties
 Technology Mapping (TM)
 Now we have subject graph G(V,E) and set of pattern graphs
P1(V1,E1), P2(V2,E2),…, PL(VL,EL) with their area and delay properties

 We have to cover G(V,E) with the set of pattern graphs that results
in a minimum cost

 Cost: area (sum of area of all gates), delay (max delay along any path),…

 Find the minimum‐cost cover is equivalent to dynamic programming (DP)

 DP Idea:
 Break the overall problem into s b‐problems
 Solve sub‐problems optimally (store results in a table)
 Use solutions to sub‐problems, construct solution to the overall problem
 Technology Mapping (TM)

 DP for TM: (Work Backward)

 Begin at leafs of tree and find optimal mapping of each leaf node

 Move up tree find optimal map ings for sub‐trees using already‐
computed mappings Subject Graph

leaf
F abcd 1 2

 ab  cd 3 4

Create subject graph

 ab  cd using base functions 5
root
 Technology Mapping (TM)
 DP for TM: (Work Backward)
Subject Graph List of gates, costs, and pattern graphs

1 2 Gate

3 4 Area Cost 0.5 1 1.2 1.2

A B C D
5
Pattern Graph
 Technology Mapping (TM)
 Begin at leafs, traverse all nodes
 Find all pattern graphs that match at each node (match the entire
pattern graph all the way back (with trace back))
 Record the best total cost to implement sub‐tree rooted at node

1) B matches, cost = 1 record this match + cost

2) B matches, cost = 1 record this match + cost
3) A matches, cost = 0.5 +1 (cost sha ed for node 1)
C matches, cost = 1.2 record this match + cost
4) Same as node 3
5) B matches, cost = 1 + 1.2 + 1.2 =3.4
D matches, cost = 1.2 + 1 + 1 = 3.2 Best for node 5
Solution: D for node 5, B for nodes 1 and 2 (Optimal Mapping)
Technology Mapping (TM)
 Optimal Solution:

 Key DP point:
 If we later need to implement the output of 3 explicitly (as the input to
another gate), we need only consider using C for node 3 (DP result).
 Technology Mapping (TM)
 Summary:
 Post‐order tree traversal (from leaves to the root)

 For each node, find all the pattern graphs that match with trace back

 Choose the one with the best c umulative cost

 At root of tree, have optimal co st, trace back to construct mapping

 Can also be used for delay (carr forward the longest path delay)
 FPGA Technology Mapping (TM)
 Target gates: LUTs with K‐inputs th at can implement any function
with K inputs

 Subject graph need not be in base functions

 Nodes must have less than K inputs (K‐bounded network)

 Same bottom‐up DP TM algorithm

 Matching is different
 Only need to care about # of in puts not functionality
 FPGA Technology Mapping (TM)
 Example: 3
 Mapping to 3‐LUTs (K=3)
1 2
 What are matches at node 3?
 Each match is a cut
 Cuts of nodes 3:
 {i1, i2, 2} i1 i2 i3 i4
 {i3, i4, 1}
 {1,2}

 Finding all matches at a node = finding set of K‐feasible cuts for that node

A cut is K‐feasible if its size is less than K