ASIC/FPGA Chip Design

Outline

 ASIC/FPGA Design Flow

 Hardware Description Language (HDL)
 Verilog
o Introduction
o Language Fundamentals
o Modeling Combinational & Sequential Logic Circuits
o Modeling Finite State Machines
o Verilog Operations

2
Outline

 ASIC/FPGA Design Flow

 Hardware Description Language (HDL)
 Verilog
o Introduction
o Language Fundamentals
o Modeling Combinational & Sequential Logic Circuits
o Modeling Finite State Machines
o Verilog Operations

3
 ASIC/FPGA Design Flow

Standard
Specifications
Cells

Pre-Layout Post-Layout
Simulation Yes Timing Yes Back Yes
RTL Coding Synthesis APR Timing Logic
Pass? Alanysis Annotation Alanysis verification
Pass? Pass?
NO NO
Test Bench Timing NO
Constraints
Tapeout

1. HDL Coding 2. Simulation 3. Synthesis 4. Placement & routing 5. Timing Analysis & Verification

Front-End Back-End (Physical Design)

 In this course we learn all the above steps in detail for ASIC
 1. HDL Coding

Standard
Specifications
Cells

Pre-Layout Post-Layout
Simulation Yes Timing Yes Back Yes
RTL Coding Synthesis APR Timing Logic
Pass? Alanysis Annotation Alanysis verification
Pass? Pass?

NO NO
Test Bench Timing NO
Constraints
Tapeout

 HDL allows us to describe the functionality of a logic circuit in a language that is:
 Easy to understand
 Easy to share
 Hides complicated implementation details
Designer more concerned about the design functionality than the detailed circuit
design
 2. Simulation by Testbenches

Standard
Specifications
Cells

Pre-Layout Post-Layout
Simulation Yes Timing Yes Back Yes
RTL Coding Synthesis APR Timing Logic
Pass? Alanysis Annotation Alanysis verification
Pass? Pass?

NO NO
Test Bench Timing NO
Constraints
Tapeout

 After HDL coding, the code has to be tested using “testbenches” (Verification).
 Simulation tools:
 Synopsys VCS (Synopsys)
 Modelsim (Mentor Graphics)
 NCVerilog (Cadence)
 3. Synthesis

Standard
Specifications
Cells

Pre-Layout Post-Layout
Simulation Yes Timing Yes Back Yes
RTL Coding Synthesis APR Timing Logic
Pass? Alanysis Annotation Alanysis verification
Pass? Pass?

NO NO
Test Bench Timing NO
Constraints
Tapeout

 Synthesis tool:
 Analyzes a piece of Verilog code and converts it into optimized logic gates
 This conversion is done according to the “language semantics”
We have to learn these language semantics, i.e., Verilog code.
3. Synthesis

 Why using synthesis tools?

It is an important tool to improve designers’ productivity to

meet today’s design complexity.

If a designer can design 150 gates a day, it will take 6666 man’s
day to design a 10-million gate design, or almost 20 years for 10
designers! This is assuming a linear grow of complexity when
design gets bigger.
 3. Synthesis
 Synthesis tool:
 Input:
 HDL Code
 “Technology library” file Standard cells (known by transistor size, 90nm)
o Basic gates (AND, OR, NOR, …)
o Macro cells (Adders, Muxes, Memory, Flip-flops, …)
 Constraint file (Timing, area, power, loading requirement, optimization Alg.)
 Output:
 A gate-level “Netlist” of the design
 Timing files (.sdf)
 3. Synthesis Tools
HDL Tech Lib Constraints

 Synthesis tool:

Gate-level Netlist

Synthesis
Tool

 Example: A 2-to-1 Multiplexer (2x1-MUX)

If (s==0) a a 0
f = a; s
f
f
else b 1
f = b; Synthesis b
s
Tool
Verilog code
(has to comply with certain structures) Synthesized gate-level Schematic
 3. Synthesis
 Synthesis tools:
 Infer logic and state elements
 Perform technology-independent optimizations
 e.g., logic simplification, state assignment
 Map elements to the target technology
 Perform technology-dependent optimizations
 Multi-level logic optimization
 Choose gate strengths to achieve speed goals
 Synthesis Tools
 Commercial Synthesis Tools:

Vendor Name Product Name Platform

Altera Quartus II FPGA
Xilinx ISE, VIVADO FPGA
Mentor Graphics Modelsim, Precision FPGA/ASIC
Synopsys Design Compiler, Galaxy ASIC
Synplicity Synplify ASIC
Cadence Ambit, BG, RC ASIC
 4. Pre-Layout Timing Analysis

Standard
Specifications
Cells

Pre-Layout Post-Layout
Simulation Yes Timing Yes Back Yes
RTL Coding Synthesis APR Timing Logic
Pass? Alanysis Annotation Alanysis verification
Pass? Pass?
NO NO
Test Bench Timing NO
Constraints
Tapeout

 Timing analysis across all design corners:

 Different voltages and temperatures
 Check for setup-time and hold-time violation
 Rough estimation as wire delays and RC models are not considered
 5. APR

Standard
Specifications
Cells

Pre-Layout Post-Layout
Simulation Yes Timing Yes Back Yes
RTL Coding Synthesis APR Timing Logic
Pass? Alanysis Annotation Alanysis verification
Pass? Pass?
NO NO
Test Bench Timing NO
Constraints
Tapeout

 Automatic Placement and Routing (APR)

 Floorplan (Die size, Pad configuration, Die-to-pad space)
 Placement (where each submodule sits in the chip)
 Routing (metal wiring to connect all instances together according to the netlist)
 6. Back Annotation & Timing Analysis

Standard
Specifications
Cells

Pre-Layout Post-Layout
Simulation Yes Timing Yes Back Yes
RTL Coding Synthesis APR Timing Logic
Pass? Alanysis Annotation Alanysis verification
Pass? Pass?
NO NO
Test Bench Timing NO
Constraints
Tapeout

 Back Annotation (Timing Closure)

 To estimate the delay after tapeout
 Extraction of RC parasitics in the layout netlist interconnect delay
 Some paths might now violate (setup-time and hold-time)
 Causes increase in the path delay (specially in deep submicron)
 7. Logic Verification & Tapeout

Standard
Specifications
Cells

Pre-Layout Post-Layout
Simulation Yes Timing Yes Back Yes
RTL Coding Synthesis APR Timing Logic
Pass? Alanysis Annotation Alanysis verification
Pass? Pass?
NO NO
Test Bench Timing NO
Constraints
Tapeout

 Logic Verification
 Simulate and test the very final netlist after APR
 Timing analysis using testbenches
 Send the final design (GDS file) for fabrication
Outline

 ASIC/FPGA Design Flow

 Hardware Description Language (HDL)
 Verilog
o Introduction
o Language Fundamentals
o Modeling Combinational & Sequential Logic Circuits
o Modeling Finite State Machines
o Verilog Operations

17
 Introduction: Digital Logic Design
 Conventional Approach:
 Schematic Entry good for fairly small designs
(Draw K-maps, optimize the Boolean logic, draw the schematic)
A
B
Y
C (10 gates)
D
Clk

 Possible for large designs?

 NO!
(10,000,000 gates)
 Introduction: Why HDL?
 Schematic entry not feasible for large designs:
 Time consuming to draw the schematic for millions of gates
 Prone to mistakes
 Difficult design entry and sharing
 Different design entry tools to learn
 Tools not compatible (hard to convert the design from one to another)
 Not easy to modify

 Solution:
 Describe the design in text Hardware Description Language (HDL)
 Just describe the design “behavior” not the detailed gate-level logic
 Gate-level logic is generated automatically by a “synthesis” tool
 Introduction: Why HDL?
 Complicated designs can be easily described by HDL

 Can be used as the input to the synthesis tool

 Supports behavioral and structural descriptions

 Supports bit-level descriptions

 Detailed design cycle-by-cycle timing is supported

 Concurrent cores can be implemented and simultaneously simulated,

which is vital to describe the hardware systems
 Software programming languages typically have no concept of time. In hardware,
there are delays associated with going from an input to an output.
HDL Coding
 Advantages of HDL Coding

 Designer describes what the hardware should do without actually

designing the hardware itself

 HDL Coding allows designers to separate behavior from implementation

 Designers develop an executable functional specification that documents

the exact behavior of all the components and their interfaces

 Designers can make decisions about cost, performance, power, and area
earlier in the design process
 Advantages of HDL Coding
There are several benefits to using an HDL to describe your design:

 An HDL facilitates a top-down design methodology using synthesis

 You can design at a high implementation-independent level
 You can delay decisions on implementation details
 You can easily explore design alternatives
 You can solve architectural problems before implementation
 You can automate mapping of your high-level description to a
technology-specific implementation

 An HDL provides greater flexibility

 You can re-use earlier design components
 You can move your design between multiple vendors and tools
HDL Coding Goals

1. To simulate digital designs

2. To synthesize digital designs

 Some tools can automatically manipulate the design for verification,

synthesis, optimization, etc.
 Computer Aided Design (CAD) tools
 HDL is NOT a Software Programming Languae

 Software Programming Language

 Language which can be translated into machine instructions
and then executed on a computer

 Hardware Description Language

 Language with syntactic and semantic support for modeling
the temporal behavior and spatial structure of hardware
 HDL Coding
A Hardware Description Language is a high-level programming language
that offers special constructs, used to model microelectronic circuits

 Two standard HDLs:

 VHDL (Very high-speed integrated circuit HDL)
 Verilog

 Verilog:
 Developed by Philip Moorby in 1985 as a proprietary language
 Open to public by Cadence Design Systems in 1990
 IEEE standard in 1995 and revised in 2001

Verilog is used in this course!

 Verilog or VHDL?

VHDL Verilog
Commissioned in 1981 by Department of Defense Created by Gateway Design Automation in 1985

An IEEE standard An IEEE standard

Initially created for ASIC Synthesis Initially an interpreted language for gate-level simulation

Strong support for package management and large No special extensions for large designs
designs
ADA-like software language C-like software language

Design is composed of entities each of which can have Design is composed of modules which have just one
multiple architectures implementation
Gate-level, dataflow, and behavioral modeling. Gate-level, dataflow, and behavioral modeling.
Synthesizable subset. Synthesizable subset.
Harder to learn and use Easy to learn and use
 Verilog in Three Flavors
 There are three types of Verilog Coding:
 Behavioral:
Most
 Describes a system by the flow of data between its functional Blocks
Descriptive
 Defines signal values when they change
 Structural:
 Shows detailed design components, nets, and interconnects
Least
 Uses technology-specific, low-level components Descriptive
 Used to pass netlist information b/w design tools (e.g., from DC to APR)
 RTL (Register Transfer Level):
 Describe how data transfers b/w registers and input/outputs
Focus of  Describes a system by the flow of data and control signals between and Somehow
this course
within its functional blocks Descriptive
 Defines signal values with respect to a clock
Verilog Coding Styles
RTL Behavioral Structural
module RTL ( A, B, C, D, Out); module behavior (A,B, C, D, Out); module structural (A,B, C, D, Out);
input A, B, C, D; input A, B, C, D; input A, B, C, D;
output Out; output Out; output Out;
reg Out; reg Out; wire n30;
always @ (A or B or C or D) always @ (A or B or C or D) EO U9 ( .A(D), .B(C), .Z(n30) );
begin begin AN3 U8 ( .A(A), .B(n30), .C(B), .Z(Out) );
if (A & B & ~D) if (A & B & ~D) endmodule
Out = C; Out = #5 C;
else if (A & D & ~C) else if (A & D & ~C)
Out = B; Out = #3 B;
else else if ((A ==1'bx) | (B ==1'bx) |
Out = 0; (C ==1'bx) |(D ==1'bz))
end Out = #7 1'bx;
endmodule else if ((A ==1'bz) | (B ==1'bZ))
Out = #7 1'bZ;
else
Our Focus Out = #3 0;
end
endmodule

Synthesizable Not synthesizable! Synthesizable

A
DC n30 Out
EO AN3

B
Verilog in Three Flavors : Behavioral
Verilog in Three Flavors : RTL
Verilog in Three Flavors : Structural
Verilog Coding Styles: Levels of Abstraction
Verilog Coding Styles: Levels of Abstraction
 Trade-offs:
 Verilog Coding Styles: Levels of Abstraction
 One language for all levels:
 Verilog Coding Styles: Design Style
 Verilog, like any other hardware description language, permits a design in either
Bottom-up or Top-down methodology.
 Bottom-Up Design
• The traditional method of electronic design is bottom-up. Each design is
performed at the gate-level using the standard gates. With the increasing
complexity of new designs this approach is nearly impossible to maintain.
New systems consist of ASIC or microprocessors with a complexity of
thousands of transistors. These traditional bottom-up designs have to give
way to new structural, hierarchical design methods.
 Top-Down Design
• A real top-down design allows early testing, easy change of different
technologies, a structured system design and offers many other
advantages. But it is very difficult to follow a pure top-down design. Due
to this fact most designs are a mix of both methods, implementing some
key elements of both design styles.
 Verilog for Synthesis (RTL)
 In this course we focus on RTL coding
 RTL coding is the closest one to the actual hardware implementation
 RTL code includes a subset of all Verilog syntax
 Not all Verilog syntax are synthesizable
 We cover most Verilog coding parts that are needed for logic synthesis
 Simulation of the RTL code is also covered
 We learn how to write a “good” Verilog code for synthesis
 Lots of examples on the synthesized RTL!

In Combinational Out
Comb. Logic
Logic
Critical path

Clk
Verilog Applications

The Verilog HDL is used by:

 System Architects: doing high level system simulations

 Verification Engineers: writing advanced tests for all levels of
simulation
 ASIC and FPGA Designers: writing RTL code for synthesis
 Library Developers: describing ASIC or FPGA cells, or higher level
components
Outline

 ASIC/FPGA Design Flow

 Hardware Description Language (HDL)
 Verilog
o Introduction
o Language Fundamentals
o Modeling Combinational & Sequential Logic Circuits
o Modeling Finite State Machines
o Verilog Styles for Synthesis
o Testbench and Simulation

39
 Verilog Fundamentals : Comment
 Comments are used for documentation

 Comments are in two types:

 Short comments (single line)
// This is a comment
 Long comments (Multiple lines)
/* This a multiple
line comment
in Verilog */

 Space, tab and blank lines are ignored by the compiler

 Verilog Fundamentals : Module
 Any circuit or subcircuit is declared as a “module” in Verilog.
DUT
input Output

 Each module may have: Signals

 Ports (Three possibilities), Body

inout

 input
 output module

 inout module DUT (A, B, C);

input A;
 Signals (main or intermediate) output B;
inout C;
 Body-code
Signals
(statements for module description)
Body-code
endmodule
 Verilog Fundamentals : Signals

Signal

Type Range Name Value

Net Variable Scalar Vector

wire tri reg integer [3:0]

 Example: wire [2:0] tmp ; tmp[0]=1 Each element of a vector

tmp = 3’b001; tmp[1]=0
can be accessed
tmp[2]=0
 Signal

Verilog Fundamentals : Signal Type Type Range Name Value

 Net
 wire:
 For interconnecting logic elements (LEs)
 To connect an output of a logic element to the input of another LE
 tri
 Circuit nodes that are connected in a tri-state fashion
 Variable
 reg (unsigned in general)
 Corresponds to a circuit node (not necessarily a register!)
 Allow a circuit to be described in terms of its behavior
 Retains its value until it is overwritten by a subsequent assignment
 integer (signed in general)
 Used for loop counters
 Signal

Verilog Fundamentals : Signal Type Type Range Name Value

 The “wire” declarations are not necessary as Verilog assumes that signals
are nets by default .
 The “reg” declaration is required!

 Example:
module DUT (A, B, C) ; Don’t forget semicolon
input [1:0] A;
output B;
inout [2:0] C;

Not necessary wire [1:0] A;

Required reg B, w; Two signal declarations in one line

Body-code

endmodule
 Signal

Verilog Fundamentals : Signal Type Type Range Name Value

 Example: Out

DUT DUT_
module DUT (s, Out);
input [3:0] s;
Ports
output [2:0] Out;
Wire
wire [2:0] Out; (for interconnection)
Signals reg [2:0] Count;
integer k; Loop counter

Count = 0;
for (k=0; k<4; k=k+1)
Code if (s[k])
Body Count = Count + 1; “;” at the end of each line
assign Out = Count;

endmodule
 Signal

Reg Type Type Range Name Value

 The keyword “reg” does NOT necessarily denote a storage element or register.
 “reg” only models the behavior of a circuit.
 May or may not be synthesized as a register.

Not Register Register

reg C; reg C;
always @ (a,b) always @ (posedge Clk)
C = a+b; C <= a+b;

a a
C C
b b
Clk
Verilog Fundamentals : Signal Range
 Signals in Verilog can be:
Signal
 Scalar: representing a node
reg C;
Type Range Name Value
wire B;

 Vector: representing a bus

Scalar Vector
reg [10:0] Data;
reg [0:6] S;
wire [7:4] B;

 Each element of a bus can be accessed.

assign a = Data[8];
Verilog Fundamentals : Signal Name
 Signal name may consists of:
Signal
 Any letter
 Any digit Type Range Name Value
 Underscore (_) and $ sign
 DON’Ts:
 Should not start with a digit
 Should not be a Verilog keyword
Legal Illegal
A_m 1xb
B1_signal wire
My$ R&z

Note: Verilog is case sensitive!

Verilog Fundamentals : Signal Value
 Scalar: each scalar signal can have four possible values:
 0: Logic value “0” Signal
 1: Logic value “1”
 Z(z): Tri-state (high impedance) Type Range Name Value

0
Scalar Vector
1 Z

 X(x): Unknown value

0 0
X
1 1

X: Unknown
Verilog Fundamentals : Signal Strength

Strength Level Type Degree

supply Driving Strogest
strong Driving Signal

pull Driving
large Storage Type Range Name Value

weak Driving
medium Storage Scalar Vector
small Storage
highz High Impedance weakest
Verilog Fundamentals : Signal Value
 Vector: <# of bits> <base> <number> Signal

Type Range Name

4 ‘b 0101 Value

 <# of bits> : number of bits for representation

Scalar Vector
 <base> : (default decimal)
 “d” : Decimal
 “b” : Binary
 “h” : Hexadecimal Used for clarity

 “o” : Octal  Example:

 <number> : signal value in base K = 8’ha9; // K=1010_1001
C= 4’d3; // C=0011
D= 4’b100; // D=0100
F= ‘b10x; // F=10X
L = -6’b3 // L = 111101
Verilog Fundamentals : Parameters
 A parameter is used as a “constant” to facilitate coding.

 Example:
module DUT (s, Out)

parameter n = 3;
parameter S0 = 4’b1010;

input [n-1:0] s;
output [n:0] Out;

wire [n:0] Out;

assign Out = S0;

endmodule
 Verilog Fundamentals : Memories
 Memory:
 A two-dimensional array of bits
 Declared in Verilog as a two-dimensional variable (reg)
 Example: A 4-byte memory: 0 1 2 3 4 5 6 7
R[0]
reg [7:0] R [3:0]; R[1]
R[2]
R[3]
8-bit 4 rows (cell)
R[2][5]
 A three-dimensional array may also be declared. (indexing method)
 Example:
reg [7:0] M [3:0][1:0];
 If an 8-bit A is declared then the legal assignment is:
reg [7:0] A; A = M[3][0];
 Verilog Fundamentals : Operators
 Example:
 Bitwise: Operation Result
1010 & 1100 1000
& 1010
1010 | 1100 1110 1100

~1010 0101
1000
1101 Λ 0100 1001

 Logical:
Operation Result
X || 1 = 1 1010 && 1100 1 Non-zero operand=logical “1”
X && 0 = 0
2’b11 || 2’b00 1

!0010 0

2’b1X && 2’b11 X Any operand X/Z, result is X

 Verilog Fundamentals : Operators
 Example:
 Reduction: Operation Result
& 1100 0

& 111 1

Λ 0100 1

 Relational:
Operation Result
A=2’b10 B=(A == 2’b10) B=1

B=(A == 2’b11) B=0 == Used only with 0 and 1

B=(A === 2’b1x) B=0 === Used with x and z
B=(A <= 2’b11) B=1
 Verilog Fundamentals : Operators
 Example:
 Logical Shift:
Operation Result
A=6’b001100 C = A >> 1 C = 000110

D = A << 2 D = 110000

F = A >> 3 F = 000001

 Concatenation:
Operation Result
A=2’b11 {A, B} 5’b11010
B=3’b010 {3{A}} 6’b111111
{B, B} 6’b010010
{{3{A}}, {2{B}}} 12’b111111010010
Be generous in {}
 Verilog Fundamentals : Operators
 Conditional: (? , : )
C
 D = S ? B:C; 0
D
B 1
B if S=1;
D=
C if S=0;
S

 D = ({S1,S2}==2’b00)? F: F
00
({S1,S2}==2’b01)? E:
E 01
({S1,S2}==2’b10)? C:B;
D 4-input
Default C
 D = ({S1,S2}==2’b00)? F: 10 Multiplexer
({S1,S2}==2’b01)? E: B (MUX)
11
({S1,S2}==2’b10)? C:
({S1,S2}==2’b11)? B:B;
S1 S2
Verilog Fundamentals : Operators (All in One)
 Verilog Fundamentals : Module-Revisited
 Any circuit or subcircuit is declared as a “module” in Verilog.
 There are three types of ports: module DUT (A, B, C)
 input type “wire” input A;
output [3:0] B;
 output type “wire” or “reg” inout C;

 inout type “wire” wire A; Optional

wire C; Optional
 Note: reg [3:0] B; Mandatory

Signals
output [3:0] B; Combined
output reg [3:0] B; Body-code
reg [3:0] B;
endmodule
 Verilog Fundamentals : Module Ports
 Inside view of the module
 input port: wire
 output port : wire or reg
 inout: wire net

net inout
 Outside view of the module
 input port: wire or reg input output
 output port : wire reg or net net reg or net net
 inout: wire
 Verilog Fundamentals : Module-Revisited
 In Verilog-2001 the port list can directly follow the module declaration

module DUT (A, B, C) module DUT ( input A,

input A; output [3:0] B,
output [3:0] B; inout C);
inout C;
wire A;
wire A; wire C;
wire C; reg [3:0] B;
reg [3:0] B;
Signals
Signals
Body-code
Body-code
endmodule
endmodule

 Body-code consists of some “statements”

 Statements describe the circuit/module functionality
 Verilog Fundamentals : Statements
 Programming languages:
 High-Level Language (HLL): C, Pascal, Matlab
 Hardware Description Language (HDL): Verilog, VHDL
 In HLL programming all statements are sequential (procedural)
 Statements evaluated in the order and one-bye-one
always @ (x, y)
Procedural : evaluated sequentially begin
(Order IS important) s = x^y;
c = x&y;
end
 Verilog Statements

Concurrent : evaluated in parallel assign s=x^y;

assign c=x&y;
(Order NOT important) assign out=x|y;
 Verilog Fundamentals : Concurrent Statements
 Evaluated in parallel
 Each statement describes part of the circuit, thus concurrent
 Most popular:
 Continuous statements: realized as connection or wire in the design
 Format: Net  Example: wire [1:3] A, B, C;
assign C = A&B;

x C
y assign C = x & y; Equivalent
assign C[1] = A[1]&B[1];
assign C[2] = A[2]&B[2];
Statement Assignment assign C[3] = A[3]&B[3];

 assign used only for nets (to be synthesizable)

 Concurrent Statements
 Example: Full Adder, same circuit, two descriptions:
module Adder (Cin, x, y, S, Cout) module Adder (Cin, x, y, S, Cout)
input x, y, Cin; input x, y, Cin;
output S, Cout; output S, Cout;
wire S, Cout; wire S, Cout;

assign S = x ^ y ^ Cin;
assign {Cout, S} = x + y + Cin;
assign Cout = (x & y)|(x & Cin)|(y & Cin);
endmodule
endmodule

x y Cin Cout S
Cin
0 0 0 0 0
x 0 0 1 0 1
Cout
0 1 0 0 1
0 1 1 1 0
y
1 0 0 0 1
1 0 1 1 0
S 1 1 0 1 0
1 1 1 0 1
 Concurrent Statements
 Example: Signed vs. unsigned addition:
 In Verilog “+” declares unsigned addition
 Signed addition has to be explicitly specified using the sign extension
module Adder_sign (X, Y, S_unsigned, S_signed); module Adder_sign (X, Y, S_unsigned, S_signed);
input [3:0] X, Y; parameter n = 4;
output [4:0] S_unsigned, S_signed; input [n-1:0] X, Y;
output [n:0] S_unsigned, S_signed;
assign S_unsigned = X + Y;
assign S_unsigned = X + Y;
Sign
assign S_signed = {{X[3]},X} + {{Y[3]},Y}; assign S_signed = {{X[n-1]},X} + {{Y[n-1]},Y};
extension
endmodule endmodule

X = 0011 (unsigned 3) or (signed +3)

Y = 1101 (unsigned 13) or (signed -3)

S_unsigned = 10000 (unsigned 16)

S_signed = 00000 (0 signed)
Concurrent Statements: Sign Extension
Concurrent Statements: Sign Extension

 Ignore carry bits: Do not spend any hardware calculating any

bits to the left of the answer’s MSB
 Verilog Fundamentals : Delay
 Delay can be used with continuous assignments by using the “#” sign

wire #2 S;
assign #5 S = x&y;

 2 time unit of delay on wire S

 5 time units of delay for AND gate
 Any change in x or y reflects on S after 7 time unit delay

 Used only for simulation purposes

 No meaning for synthesis
 Not synthesizable
 Procedural Statements
 Evaluated in the order in which they appear in the code (sequential)
 Should be inside an “always” block
 An “always” block contains one or more procedural statements
List of all signals that trigger the
evaluation inside the always block
always @ (sensitivity list)
begin
 Procedural assignments
 if-else statements Procedural
 case statements Statements
 while, repeat, for loops
end
 Procedural Statements: Half-Adder
 Example: module Adder (x, y, S, C) If either x or y changes, the statements inside
input x,y; the always block are evaluated.
output S,C;
Type: “reg” reg S, C; module Adder (x, y, S, C)
always @ (x, y) input x,y;
x y C S begin output S,C;
S = x Λ y; wire S, C; Type: “wire”
0 0 0 0
0 1 0 1 C = x & y; assign S = x Λ y;
1 0 0 1 end assign C = x & y;
1 1 1 0 endmodule endmodule

 Anything on the RHS should be on the sensitivity list

 always @(*) Automatically considers all signals on the RHS in the sensitivity list
 Any signal assigned inside an always block has to be a variable of type
 reg
 integer
 always block: Quick Notes
 The always construct requires begin-end only if there are multiple statements
in the block.
 Example:
always @ (x, y, z)
begin always @ (x, y, z)
z = x; z = x;
if (x == 1) if (x == 1) Not part of the always block
z = y; z = y;
end

Correct Incorrect

 A given variable should never be assigned a value in more than one always block.
 Because always blocks are concurrent with respect to one another.

always @ (x,y) always @ (x,y)

begin always @ (x,y)
Incorrect a <= x;
a <= x; a <= y;
always @ (x,y)
a <= y;
a <= y; end Correct
Procedural Statements
Procedural Statements

If-else Case Loop statements

Procedural Assignments
Statements Statements

Blocking Non-blocking while repeat for

always @ (sensitivity list)

begin
 Procedural assignments
Procedural  if-else statements
Statements  case statements
 while, repeat, for loops
end
Procedural Statements
Procedural Statements

If-else Case Loop statements

Procedural Assignments
Statements Statements

Blocking Non-blocking while repeat for

 Used inside an always block and are of two types:

 Blocking: denoted by “=“ token
 Evaluation within the always block is “blocked” until this assignment is completed

 Non-blocking: denoted by “<=“ token

 Nothing is hold or blocked (parallel evaluation)
 Blocking vs. Non-Blocking Assignments
 Example: assume S=2 then
Blocking Non-Blocking
always @ (*) always @ (*)
begin begin
S = 4; S <= 4;
a = S; a <= S;
end end

S=4 & a=4 S=4 & a=2

(sequential) (Parallel)

 Evaluated and assigned in a single step  Evaluated and assigned in two steps
 Sequential nature 1. All RHSs are evaluated in parallel
 Assignment ordering IS important 2. Assignments to LHSs are performed together
 S=4 “blocks” a=S to be evaluated  They all are evaluated all at once
 a=S has to wait for S=4 to be evaluated first  Assignment ordering is NOT important
 S<=4 and a<=S evaluated in parallel
 Blocking vs. Non-Blocking Assignments
 Example: Swap bytes in words
B[15:8] B[7:0]

 Which one is correct?

Blocking Non-Blocking
always @ (*) always @ (*)
begin begin
Incorrect B[15:8] = B[7:0]; B[15:8] <= B[7:0]; Correct
B[7:0] = B[15:8] ; B[7:0] <= B[15:8] ;
end end

B[15:8] B[7:0] B[15:8] B[7:0]

 Blocking vs. Non-Blocking after Synthesis:
always @ (posedge Clk) always @ (posedge Clk) always @ (*)
begin begin begin
y1 = in; y1 <= in; y1 = in;
y2 = y1 ; y2 <= y1 ; y2 = y1 ;
end end end

y1 y1
in y1 y2 in y2 in y2

Clk Clk
 Overall Code Parallelism
 Statements inside an always block are evaluated sequentially
 However, all always blocks are evaluated concurrently
 All continuous assignments are evaluated concurrently too

always @ (posedge Clk)

begin
b = in;
C
a
end

assign a=b&c; in b

always @ (c,b) d
begin Clk
d = c^b;
end e

assign e=b|c;
Verilog Assignments in a Glance
Verilog Assignments

Procedural Continuous
Inside an always block Using assign statement

assign a=b;
Blocking Non-blocking
always @ (*) always @ (*)
begin begin
= <=
= <=
end end

 assign can not be used inside an always block b/c assign is used for nets.
 Nets can not be assigned inside an always blocks (only reg or integer).
Outline

 ASIC/FPGA Design Flow

 Hardware Description Language (HDL)
 Verilog
o Introduction
o Language Fundamentals
o Modeling Combinational & Sequential Logic Circuits
o Modeling Finite State Machines
o Verilog Operations

79
 Logic Circuits Category
 Logic Circuits:
 Combinational logic: (realized by assign and always)
 Output depends on inputs
 Inputs propagates to the output through some gates with delay
 e.g., adders, Mux, multiplier, all logic gates
 Sequential Logic: (realized only by always)
 Output depends on inputs and circuit history
 Circuit history is kept using flip-flops, registers or latches
 e.g., Finite State Machines (FSM), shift registers, Flip Flops (FF)
 Sequential logic has two flavors:
 Synchronous: all registers controlled by a global clock
 Asynchronous: based on the handshaking process
 Logic Circuits Category
 A general system consists of both combinational and sequential circuits

assign assign
always always always always always

In Combinational Out
Comb. Logic
Logic
Critical path

Clk

 Critical path of the Comb. Logic determines the max operating frequency
 Combinational logic can be realized using assign and always constructs
 Sequential logic can only be realized using always blocks.
 Combinational Logic
 Combinational logic can be realized using assign and always constructs
 Example: Full Adder:

module Adder (x, y, S, C)

input x,y;
output S,C;
reg S, C; module Adder (x, y, S, C)
always @ (x, y) input x,y;
begin output S,C;
S = x Λ y; wire S, C;
C = x & y; assign S = x Λ y;
end assign C = x & y;
endmodule endmodule

 When using always block for Com. Logic, “blocking” assignments are used
 When using an always block, time instant changes when one of the
sensitivity list variables changes
 Blocking Assignment for Combinational Logic
 Use only blocking assignments for combinational logic. Why?
 Example: Accumulator: (Assume Count == 0)

always @ (*) always @ (*)

begin begin
for (k=0; k<4; k=k+1) for (k=0; k<4; k=k+1)
Count = Count + k; Count <= Count + k;
end end

Count = Count + 0; Count <= Count + 0;

Count = 0 + 1; Count <= Count + 1;
Count = 0 + 1 + 2; Count <= Count + 2;
Count = 0 + 1 + 2 + 3; Count <= Count + 3; In multiple concurrent
Result: Count = 6 Result: Count =3 non-blocking
assignments to a
Correct Incorrect variable, the last one
executes
Combinational Logic
 always block vs. assign for Combinational Logic
 When do we use the always block to describe a combinational logic?
1. Normally for high-complexity Comb. Logic
2. When output depends on several conditions, which requires if-else
or case constructs to be fully described

 Why?
1. Because powerful statements like if-else and loop constructs can only
be used inside an always block
 Comes with more clarity and more concise description than assign
2. Multiple outputs can be assigned within a single always block
 Sequential Logic
 Sequential circuits have memory (i.e., remembers the past)
 The current state is held in memory and the next state is computed through
the combinational logic
 In a synchronous system, a global clock signal orchestrates the flow of the
data and the sequence of events

Input
Output
Comb. Next State Registers/
Current State Comb.
Logic (NS) Flip Flops
(CS) Logic
(FFs)

Clk
Sequential Logic
 Sequential logic can only be realized using an always block
 Consists of :
 Flip flops that are normally controlled by:
 Positive edge of the clock (posedge) always @ (posedge Clk)
 Negative edge of the clock (negedge) always @ (negedge Clk)
 Have posedge or negedge in the sensitivity list
 Any variable assigned a value is the output of a flip-flop
 Latches
 Transfers input to output when clock is “1” and stores the value O.W.
 Finite State Machine (FSM)
 When using the always block for the sequential Logic, “Non-blocking”
assignments are used
 Sequential Logic: Flip-Flop
 Example: Flip-flop with asynchronous Reset:

always @ (posedge Clk, negedge Reset) D Q

if (Reset == 0)
Q<=0; Clk
else
Q<=D;
Reset

 Example: Flip-flop with synchronous Reset:

always @ (posedge Clk)
if (Reset == 0) D
Q
Q<=0; Reset
else
Q<=D; Clk
 Sequential Logic: Flip-Flop
 Example: Flip-flop with complete features:

module flip_flop_n ( output reg Q , output Q_n ,input pre_n, clr_n,

D, input clk_n, CE ); pre

always@ (negedge clk_n or negedge pre_n or negedge clr_n)

begin Q
D
if (!pre_n) Q <= 1'b1; CE
!Q
elseif (!clr_n) Q <= 1'b0; Clk
elseif (CE) Q <= D;
end
assign Q_n = ~Q; clr
endmodule
Sequential Logic: Flip-Flop

 Use reset-able FFs only where needed

 FFs are a little larger and higher power
 Requires the global routing of the high-fanout reset signal

high-fanout
reset signal

Reset
 Sequential Logic
 Example: D-Latch:
module Latch(D, Clk, Q);
input D, Clk;
D Q
output reg Q;
always @ (D, Clk)
if (Clk) Clk
Q<=D;
endmodule

 Example:
Clk

Reset

D-Latech

FF (sync Rst)

FF (Async Rst)
 Sequential Logic
 Example: D-Latch:
module Latch(D, Clk, Q);
input D, Clk;
D Q
output reg Q;
always @ (D, Clk)
if (Clk) Clk
Q<=D;
endmodule
Both results in a latch

module Latch(D, Clk, Q);

input D, Clk;
output reg Q;
always @ (Clk)
if (Clk) This results in a warning saying D is
Q<=D;
endmodule not in the sensitivity list
Sequential Logic: Registers

 Store a multi-bit encoded value

 One D-FF per bit
 Stores a new value on each clock cycle

wire [n:0] d;
reg [n:0] q;
...
always @ (posedge Clk)
q<=d;
 Signal

Reg Type (Revisited) Type Range Name Value

 The keyword “reg” does NOT necessarily denote a storage element or register.
 “reg” simply means a variable that can hold a value
 May or may not be synthesized as a register.

Not Register Register

reg C; reg C;
always @ (a,b) always @ (posedge Clk)
C = a+b; C <= a+b;

a a
C C
b b
Clk
 Sequential Logic
 When using always block for sequential Logic, “Non-blocking”
assignments are used. Why?
always @ (posedge Clk) always @ (posedge Clk)
y1=in; y1<=in;

always @ (posedge Clk) always @ (posedge Clk)

y2=y1; y2<=y1;

Race Condition

Clk Clk

in in

y1 y1

y2 ? ? ? ? ? ? y2
 Sequential Logic
 When using always blocks for sequential Logic, “Non-blocking”
assignments are used. Why?
 Example: Shift register

always @ (A) always @ (A)

begin begin
for (k=0; k<4;k=k+1) for (k=0; k<4;k=k+1)
A[k]=A[k+1]; A[k]<=A[k+1];
A[3] = A[0]; A[3] <= A[0];
end end

Incorrect!

A[0] A[1] A[2] A[3]

 Do NOT use blocking assignments for sequential logic

Important Timing Parameters
System Timing Parameters
 System Timing Parameters : Minimum Period
 Setup-time Condition:
 If violates circuit works at lower frequency (why?)

Combinational Out
In
Logic

Clk

Clk
Tsu Thold Tsu Thold

in
Tcq Tlogic Tsu

TClk>Tcq+Tlogic+Tsu
Tlogic<TClk-Tsu-Tcq
 System Timing Parameters : Minimum Delay
 Hold-time Condition:
 If violates circuit does not work (even at lower frequencies) (why?)

Combinational Out
In
Logic

Clk

Clk
Tsu Thold Tsu Thold

in
Tcq,d Tlogic,cd Tcq,d Tlogic,cd

Tcq,cd+Tlogic,cd>Thold
Procedural Statements
Procedural Statements

If-else Case Loop statements

Procedural Assignments
Statements Statements

Blocking Non-blocking while repeat for

always @ (sensitivity list)

begin
 Procedural assignments
Procedural  if-else statements
Statements  case statements
 while, repeat, for loops
end
 If-else statements
 Used only inside an always block
 Format: If (expression1)
statement1; Single statement no need for begin-end
else if (expression2) Multiple statements, begin-end is needed
statement2;
else
statement3;

module Mux21 (in1, in2, s, out) module Mux21 (in1, in2, s, out)
input in1, in2, s; input in1, in2, s;
 Example: output reg out; output reg out;
always @ (in1, in2, s)
in1 0 always @ (in1, in2, s) begin
out if (s==0) out = in1;
in2 out = in1; if (s==1)
1
else out = in2;
s out = in2; end
endmodule endmodule
 If-else statements
 If-else construct inside an always block have a sequential nature when used
by blocking assignments. Sequential means direct effect on synthesis not
necessarily sequential in actual hardware implementation
 This means ordering is important
 Example: always @ (*) always @ (*)
begin begin
out = in1; if (s==1)
if (s==1) out = in2;
out = in2; out = in1;
end end

in1 0
out in1 out
in2 1

s
Procedural Statements
Procedural Statements

If-else Case Loop statements

Procedural Assignments
Statements Statements

Blocking Non-blocking while repeat for

always @ (sensitivity list)

begin
 Procedural assignments
Procedural  if-else statements
Statements  case statements
 while, repeat, for loops
end
 Case statements
 Used only inside an always block
 Format: case (expression)
alternative1: statement1; Single statement no need for begin-end
alternative2: begin
statement2; Multiple statements, begin-end is needed
end
default: statementn;
endcase

module Mux21 (in1, in2, s, out) module Mux21 (in1, in2, s, out)
 Example: input in1, in2, s; input in1, in2, s;
output reg out; output reg out;

always @ (in1, in2, s) always @ (in1, in2, s)

case (s) case (s)
1’b0: out = in1; 1’b0: out = in1;
1’b1: out = in2; default: out = in2;
endcase endcase
endmodule endmodule
 Case statements
 Example: Combinational logic using both assign and always block
module FullAdder (Cin, x, y, S, Cout) module FullAdder (Cin, x, y, S, Cout)
input x, y, Cin; input x, y, Cin;
output S, Cout; output reg S, Cout;
wire S, Cout; always @ (Cin, x, y)
begin
assign S = x ^ y ^ Cin; case ({Cin, x, y}) concatenation
3’b000: {Cout, S} = ‘b00;
assign Cout = (x & y)|(x & Cin)|(y & Cin); 3’b001: {Cout, S} = ‘b01;
3’b010: {Cout, S} = ‘b01;
endmodule 3’b011: {Cout, S} = ‘b10;
3’b100: {Cout, S} = ‘b01;
x y Cin Cout S 3’b101: {Cout, S} = ‘b10;
3’b110: {Cout, S} = ‘b10;
0 0 0 0 0 3’b111: {Cout, S} = ‘b11;
0 0 1 0 1
0 1 0 0 1 endcase
0 1 1 1 0 end
1 0 0 0 1 endmodule
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1
 Case statements
 In case statements, each alternative is compared for an exact match
Synthesis tools are only concerned about matching of “0” and “1” while
“Z” and “X” are not important
 If “X” or “Z” are needed to be added, casex is used (casex is synthesizable).
 In fact casex treats them as don’t care. module Priority (W, Y, f)
input [3:0] W;
 Example: 4-to-2 priority encoder output reg [1:0] Y;
output f;
w3 w2 w1 w0 y1 y0 f assign f = (W!=0)
always @ (W)
0 0 0 0 d d 0 begin
casex (W)
0 0 0 1 0 0 1 ’b1xxx: Y = 3;
0 0 1 X 0 1 1 ‘b01xx: Y = 2;
0 1 X X 1 0 1 ‘b001x: Y = 1;
1 X X X 1 1 1 default: Y = 0;
endcase
end
endmodule
Case statements
 casez allows use of wildcard “?” character for don’t

module Priority (W, Y, f)

input [3:0] W;
output reg [1:0] Y;
output f;
w3 w2 w1 w0 y1 y0 f assign f = (W!=0)
always @ (W)
0 0 0 0 d d 0 begin
casez (W)
0 0 0 1 0 0 1 ’b1???: Y = 3;
0 0 1 X 0 1 1 ‘b01??: Y = 2;
0 1 X X 1 0 1 ‘b001?: Y = 1;
1 X X X 1 1 1 default: Y = 0;
endcase
end
endmodule
 Latch Inference in Combinational Logic

 When realizing combinational logic with always block using if-else or case
constructs care has to be taken to avoid latch inference after synthesis

 The latch is inferred when “incomplete” if-else or case statements are declared

 This latch is “unwanted” as the logic is combinational not sequential

 If there is some logic path through the always block that does not assign a value
to the output, a latch is inferred
 Latch Inference in If-else or Case Statements
 Example: module DUT (A, B, S, out);
module DUT (A, B, S, out); input A, B;
input A, B, S; Input [1:0] S;
output reg out; output reg out;
always @(*) always @(A, B, S)
begin begin
if (S==1) case (S)
out = A; 2’b00: out = A;
end 2’b01: out = B;
endmodule endcase
end
endmodule

A out
D Q A
0
S out
Clk D Q
B 1
Clk
Latch Inference
S[0] S[1]

Latch Inference
 Latch Inference in Combinational Logic
 To avoid latch inference make sure to specify all possible cases “explicitly”

 Two practical approaches to avoid latch inference:

 For if-else construct:

1. Initialize the variable before the if-else construct
2. Use else to explicitly list all possible cases
 For case constructs:
1. Use default to make sure no case is missed!

 Do NOT let it up to the synthesis tool to act in unspecified cases and do specify
all cases explicitly.
 Avoid Latch Inference in If-else Statements
module DUT (A, B, S, out); module DUT (A, B, S, out);
 Example: input A, B, S; input A, B, S;
output reg out; output reg out;
always @(*) 1 always @(*)
B

begin Begin S out

if (S==1) out = B;
out = A; if (S==1)
A
end out = A;
endmodule end
2 endmodule
No Latch

module DUT (A, B, S, out);

input A, B, S;
A out output reg out;
D Q
always @(*) B
S
Clk begin
if (S==1) S out
out = A;
Latch Inference else A
out =B;
end
endmodule No Latch
 Avoid Latch Inference in Case Statements
module DUT (A, B, S, out); module DUT (A, B, S, out);
 Example: input A, B; input A, B;
Input [1:0] S; Input [1:0] S;
output reg out; output reg out;
always @(A, B, S)
always @(A, B, S) begin
begin case (S)
case (S) 2’b00: out = A;
2’b00: out = A; 2’b01: out = B;
2’b01: out = B; default: out = 1’b0;
endcase endcase
end end
endmodule endmodule

A S[1]
0
out B
D Q
B 1
S[0] out
Clk

S[0] S[1] A

Latch Inference No Latch

Procedural Statements
Procedural Statements

If-else Case Loop statements

Procedural Assignments
Statements Statements

Blocking Non-blocking while repeat for

always @ (sensitivity list)

begin
 Procedural assignments
Procedural  if-else statements
Statements  case statements
 while, repeat, for loops
end
 Loop Statements
 To be used for efficient coding style
 All being used inside an always block
 Make sure to use blocking statements for combinational logic

for (k=0; k<n-1; k=k+1) while (condition) repeat (constant_value)

begin begin begin
statement; statement; statement;
end end end

Single statements no need for begin-end construct

Multiple statements, begin-end construct is needed
 Loop Statements
 Example: Remember: 1-bit full Adder

module Full_Adder (Cin, x, y, S, Cout)

input x, y, Cin; y x
output S, Cout;
wire S, Cout;
Cout Cin
assign S = x ^ y ^ Cin;

assign Cout = (x & y)|(x & Cin)|(y & Cin);

S
endmodule
 Loop Statements
 Example: n-Bit ripple carry adder
module RippleCarryAdderI (Cin, X, Y, S, Cout)
parameter n = 4; Y[3] X[3] Y[2] X[2] Y[1] X[1] Y[0] X[0]
input Cin;
input [n-1:0] X, Y;
output reg [n-1:0] S; Cout Cin
output reg Cout; C[3] C[2] C[1]
reg [n:0] C;
integer k;
always @(X, Y, Cin) S[3] S[2] S[1] S[0]
begin
Sequential C[0] = Cin; Breaking one statement in two lines is allowed!
Structure for (k=0;k<=n-1;k=k+1) Supported
begin
S[k] = X[k] ^ Y[k] ^ C[k]; module Adder (Cin, X, Y, S, Cout)
C[k+1] = (X[k] & Y[k]) input Cin;
|(X[k] & C[k])|(Y[k] & C[k]); input [3:0] X, Y;
end output [3:0] S;
Cout = C[n]; output Cout;
end assign {Cout, S} = {1’b0, X} + {1’b0, Y} + {4’b0, Cin}
endmodule endmodule
 Using Sub-Circuits (Sub-modules)
 A design can use multiple submodules or a module multiple times
 Using a module in another is called “instantiation”
 Top-level module: the module that has not been instantiated
 To use a module inside another, it should be explicitly instantiated

Top Module

M1 M2

Inputs

M3 M1 M1

Outputs
M2 M1
 Using Sub-modules
 There are some built-in primitive logic gates in Verilog that can be instantiated
 Built-in primitives means there is no need to define a module for these gates
 and, or, nor, ….
 Example:
module Myand(In1, In2, out)
input In1, In2;
output out;

1. Gate instantiation and myand (out, In1, In2);

2. assign assign out = In1 & In2;

reg out;
3. always block always @(In1, In2)
out = (In1 & In2);

endmodule
Using Sub-modules : Gate-level Primitives
 Gate-Level primitives:

and buf nmos tran

nand not pmos tranif0
nor bufif0 cmos tranif1
or bufif1 rnmos rtran
xor notif0 rpmos rtranif0
xnor notif1 rcmos rtranif1
 Using Sub-modules
 Example: (4-input MUX using primitives)
 Sub-modules Instantiation
 To instantiate a module, two things have to be clearly specified
 module’s ports
 module’s parameters (considered as default if not specified)
 Format:
Module_name #(parameter_value) instance_name (.port_name(port-connection), .port_name(port-connection),….)

Module_name instance_name (.port_name(port-connection), .port_name(port-connection),….)

defparam instance_name.parameter_name = parameter_value

 If port connections are in the same order as the original module

“.port_name” is not needed in the port list.
 Sub-modules Instantiation
 Example: module Full_Adder (Cin, x, y, S, Cout);
Y[3] X[3] Y[2] X[2] Y[1] X[1]
input x, y, Cin; Y[0] X[0]

output S, Cout;
wire S, C; Cout Cin
C[3] C[2] C[1]
assign S = x ^ y ^ Cin;
assign Cout = (x & y)|(x & Cin)|(y & Cin);
S[3] S[2] S[1] S[0]
endmodule

module RippleCarryAdderII (Cin, X, Y, S, Cout); Can NOT be of type “reg”

parameter n = 4; (output of a submodule)
input Cin;
input [n-1:0] X, Y;
output [n-1:0] S;
4-bit Ripple Carry output Cout;
Adder wire [n-1:0] C; Cin x y S Cout
Implicit list
Full_Adder stage0 (Cin, X[0], Y[0], S[0], C[1]);
Full_Adder stage1 (C[1], X[1], Y[1], S[1], C[2]);
(Order IS important)
Full_Adder stage2 (C[2], X[2], Y[2], S[2], C[3]); Explicit list
Full_Adder stage3 (.Cout(Cout), .Cin(C[3]), .x(X[3]), .y(Y[3]), .S(S[3]));
(Order NOT important)
endmodule
 Sub-modules Instantiation
 Example: 5-bit Ripple Carry Adder:

module 5-BitRippleCarryAdder (Cin, X, Y, S, Cout)

parameter n = 5;
input Cin;
input [n-1:0] X, Y;
defparam stage0.n = 3;
output [n-1:0] S;
output Cout; If two parameters : # (3,8)
wire C;

RippleCarryAdderI #(3) stage0 (.Cin(Cin), .X(X[2:0]), .Y(Y[2:0]), .S(S[2:0]), .Cout(C));

defparam stage1.n = 2;
RippleCarryAdderI stage1 (.Cin(C), .X(X[4:3]), .Y(Y[4:3]), .S(S[4:3]), .Cout(Cout));

endmodule
Sub-modules Instantiation
IN_2
 Example: DUT
IN_0
in1 out1 w1 OUT_2
M1 M1
M1 (6) (3)
Parameter length =10;
IN_1
in2 out2 w3
w2 M1
(10)
OUT_0

module DUT (IN, OUT) OUT_1

input [2:0] IN;
output [2:0] OUT;
wire w1, w2, w3;

defparam stage0.length = 6;
M1 stage0 (IN[0], IN[1], w1, w2);

defparam stage1.length = 3;
M1 stage1 (.in1(w1), .in2(IN[2]), .out2(w3), .out1(OUT[2]));

M1 stage2 (.in1(w2), .in2(w3), .out1(OUT[0]), .out2(OUT[1]));

endmodule
 Function Construct
 function may be used to have a modular code without defining separate modules

 A function is defined inside a module

 Not crucial for Verilog but might facilitate modular coding

 A function can be called both in continuous and procedural assignments

 A function can have multiple inputs but does not have any output

 Function name serves as the output

 Function Construct
 Example: 16-to-1 multiplexer:
module my16-to-1MUX (W, S, Out);
input [0:15] W;
input [3:0] S;
output reg Out;
reg [0:3] M;

function my4-to-1MUX;
input [0:3] W;
input [1:0] s;
if (s==0) my4-to-1MUX = W[0];
else if (s==1) my4-to-1MUX = W[1];
else if (s==2) my4-to-1MUX = W[2];
else if (s==3) my4-to-1MUX = W[3];
endfunction
if (S[3:2]==0) Out= M[0];
always@ (W, S) else if (S[3:2]==1) Out= M[1];
begin else if (S[3:2]==2) Out= M[2];
M[0] = my4-to-1MUX(W[0:3],S[1:0]); else if (S[3:2]==3) Out= M[3];
M[1] = my4-to-1MUX(W[4:7],S[1:0]);
M[2] = my4-to-1MUX(W[8:11],S[1:0]);
M[3] = my4-to-1MUX(W[12:15],S[1:0]);

Out = my4-to-1MUX(M[0:3], S[3:2]);

end
endmodule
 Function Construct with multiple-bit output
 Example:
module test_fcn (a, b, c, Out); module test_fcn (a, b, c, Out);
input a, b, c; input a, b, c;
output reg [2:0] Out; output [2:0] Out;

function [2:0] myfcn; function [2:0] myfcn;

input a, b, c; input a, b, c;
begin begin
myfcn[0] = a^b; myfcn[0] = a^b;
myfcn[1] = b^c; myfcn[1] = b^c;
myfcn[2] = c^a; myfcn[2] = c^a;
end end
endfunction endfunction

always @(*) assign Out = myfcn(a,b,c);

Out = myfcn(a,b,c);
endmodule
endmodule

With always With assign

 Task Construct
 task may be used to have a modular code without defining separate modules

 A task is defined inside a module

 A task can only be called from inside and always (or initial) block

 A task can have multiple inputs and outputs

 Task Construct
 Example: 16-to-1 multiplexer:
module 16-to-1MUX (W, S, Out)
input [0:15] W;
input [3:0] S;
output reg Out;
reg [0:3] M;

task 4-to-1MUX;
input [0:3] W;
input [1:0] s;
output Result;
begin
if (s==0) Result= W[0];
elseif (s==1) Result = W[1];
elseif (s==2) Result = W[2];
elseif (s==3) Result = W[3];
end
endtask
always@ (W, S)
begin
4-to-1MUX(W[0:3],S[1:0], M[0]);
4-to-1MUX(W[4:7],S[1:0] , M[1]);
4-to-1MUX(W[8:11],S[1:0] , M[2]);
4-to-1MUX(W[12:15],S[1:0] , M[3]);
4-to-1MUX(M[0:3],S[3:2] , Out);
end
endmodule
 HDL for Synthesis (Priority logic)
 The order in which assignments are written in an always block may affect the logic
that is synthesized. (both conditions in if and else if can be true!)
 Example: 0
always @ (s0,s1, d0, d1) 0
begin 0
Q = 0; d1 1 Q
if (s0) Q = d0; d0 1
else if (s1) Q = d1;
end s1
s0
Different

0
0
always @ (s0,s1, d0, d1) 0
begin d0 1 Q
Q = 0; d1 1
if (s1) Q = d1;
else if (s0) Q = d0; s0
end
s1
Non of the above infer latch, why?
 Example: Up & Down Counters
4-Bit unsigned down-counter 4-Bit up-counter with
with synchronous set asynchronous reset and
modulo maximum
module D_counter (C, S, Q); module U_counter (C, CLR, Q);
input C, S; parameter
output [3:0] Q; MAX_SQRT = 4,
reg [3:0] tmp; MAX = (MAX_SQRT*MAX_SQRT);
always @(posedge C) input C, CLR;
begin output [MAX_SQRT-1:0] Q;
if (S) reg [MAX_SQRT-1:0] cnt;
tmp <= 4’b1111; always @ (posedge C or posedge CLR)
else begin
tmp <= tmp - 1’b1; if (CLR)
end cnt <= 0;
assign Q = tmp; else
cnt <= (cnt + 1) %MAX;
endmodule end
assign Q = cnt;

endmodule
 Accumulator
 Accumulates multiple successive k-bit values and stores them into a k-bit register
 The number of successive numbers (Num) as an input
module Accumulator (In, Num, Clk, Rst, Out);
parameter k = 8;
parameter m = 4;
input [k-1:0] In;
input [m-1:0] Num;
Reset input Clk, Rst;
output reg [k-1:0] Out;
Sum Out wire [k-1:0] Sum;
reg [m-1:0] C;
In wire En, Cout;
Clk
defparam stage0.n = k;
RippleCarryAdderI stage0 (.Cin(0), .X(In), .Y(Out), .S(Sum), .Cout(Cout));
always@ (posedge Clk, negedge Rst)
if (Rst == 0)
begin
Num En C <= Num;
Out <= {k{1‘b0}};
Down
end
Counter
else if (En)
begin
C <= C-1;
Out <= Sum;
end
assign En = |C;
endmodule
Outline

 ASIC/FPGA Design Flow

 Hardware Description Language (HDL)
 Verilog
o Introduction
o Language Fundamentals
o Modeling Combinational & Sequential Logic Circuits
o Modeling Finite State Machines
o Verilog Operations

136
Finite State Machine (FSM)
 Used to implement control sequencing
 An FSM is defined by
 set of inputs
 set of outputs
 set of states
 initial state
 transition function
 output function

 States are steps in a sequence of transitions

 There are “Finite” number of states.
 Finite State Machine (FSM)
 The behavior of the circuit can be represented using a finite number of states
 Two types:
 Mealy:
 Output depends on the “current state” and the “input”

Input
Output
Comb. Next State Flip Flops Comb.
(NS) Current State
Logic (FFs) Logic
(CS)

always block always block always block

Finite State Machine (FSM)
 Moore:
 Output depends only on the “current state”

Input
Output
Comb. Next State Flip Flops Comb.
(NS) Current State
Logic (FFs) Logic
(CS)

always block always block assign statement

 Therefore, to describe an FSM in Verilog we have to show how to derive:

 Next State (NC)
 Current State (CS)
 Output
 FSM Code Structure
Mealy Moore
always @(*) always @(*)
NS & Output …………… NS Calculation ……………
Calculation …………… ……………
…………… ……………

always @(*) always @(*)

CS Calculation …………… CS Calculation ……………
…………… ……………
…………… ……………

Output
assign ……………
Calculation

 Output depends on input  Output does not depend on input

 Output declared as reg  Output declared as wire
 FSM
 Example: Mealy Machine module mealy (Clock, w, Resetn, z);
input Clock, w, Resetn ;
Output: reg output reg z ;
reg CS, NS;
Reset parameter A = 1'b0, B = 1'b1;
W=0/z=0 always @(w, CS)
case (CS)
A: if (w == 0)
A B
begin
W=0/z=0 W=1/z=0 W=1/z=1 NS = A; z = 0;
end
else Combinational
NS & Output begin
Calculation NS = B; z = 0; (Blocking)
end
B: if (w == 0)
begin
NS = A; z = 0;
end
else
begin
NS = B; z = 1;
end
endcase
always @(posedge Clock, negedge Resetn)
CS if (Resetn == 0)

Calculation
CS <= A; Sequential
else
CS <= NS; (Non-Blocking)
endmodule
 FSM
 Example: Moore Machine module moore (Clk, w, Resetn, z);
input Clk, w, Resetn;
Output: wire output z;
reg [1:0] CS, NS;
parameter A = 2'b00, B = 2'b01, C = 2'b10;

Reset always @(w, CS)

begin
case (CS)
W=0
A: if (w == 0) NS = A;
W=0 A/z=0 B/z=0 NS else NS = B; Combinational
B: if (w == 0) NS = A;
W=1 Calculation else NS = C;
(Blocking)
C: if (w == 0) NS = A;
W=0 W=1 else NS = C;
default: NS = 2'bxx;
endcase
C/z=1 end
always @(posedge Clk, negedge Resetn)
begin
if (Resetn == 0)
W=1
CS CS <= A; Sequential
Calculation else (Non-Blocking)
CS <= NS;
end
Output
assign z = (CS == C);
Calculation endmodule
Outline

 ASIC/FPGA Design Flow

 Hardware Description Language (HDL)
 Verilog
o Introduction
o Language Fundamentals
o Modeling Combinational & Sequential Logic Circuits
o Modeling Finite State Machines
o Verilog Operations

143
 Tri-State Logic in Verilog
 Tri-state buffer:
module tri-buffer (A, y, EN)
input A, EN;
A EN = 1 A Y output Y;
Y=
Z EN = 0 assign Y = (EN) ? A : 1’bZ;
EN
endmodule

 Tri-state driver inference: always @ (ENa, a)

begin
if (ENa)
a out = a;
else
out out = 1’bz; assign out = (ENa) ? a : 1’bz;
ENa end assign out = (ENb) ? b : 1’bz;
always @ (ENb, b)
b begin
if (ENb)
out = b;
ENb else
out = 1’bz;
end
 Tri-State Applications
1. Buffering:
A Y
EN

2. Half-duplex communication:
A A

Ena = 0 Enb = 1 Ena = 1 Enb = 0

Enb = 1 Ena = 0 Enb = 0 Ena = 1

3. Bus multiplexing: a 8 8

s 8 Out[7:0]

b 8 8
 Tri-State Applications
 Example: Adder with four options
module tri-adder (a, b, c, d, S_ab, S_cd, Out);
a 8 8
input S_ab, S_cd;
S_ab 8 input [7:0] a, b, c, d;
p output [8:0] Out;
wire [7:0] p, q;
b 8 8

Out[7:0] assign p = ~S_ab ? a : 8’bzzzzzzzz;

c 8 8 assign p = S_ab ? b : 8’bzzzzzzzz;
assign q = ~S_cd ? c : 8’bzzzzzzzz;
S_cd assign q = S_cd ? d : 8’bzzzzzzzz;
8
q
assign Out = p + q;
d 8 8

endmodule

Z is an allowed logic value and implies

a tri-state driver for synthesis
 Verilog Operations: Right/Left Shift
 Verilog supports << for left and >> for right shift. (Only one position)
 Both of these operators use a zero for the shift input bit.
 We can also control the shift input
module LRShift (Si, L, R, In, Out);

input Si, L, R;
input [7:0] In;
output [7:0] Out;

always @ (L, R, In, Si)

begin
case({R,L})
2’b01 : Out = {In[6:0], Si}; // Left shift
2’b10 : Out = {Si, In[7:1]}; // Right shift
default: Out = In;
endcase
end
endmodule
 Verilog Operations: Barrel Shifter
 Barrel shifter shifts a signal by multiple positions module BarrelShifter (s, a, y);
input [4:0] s;
 Example: input [31:0] a;
 32-bit left shift barrel shifter output [31:0] y;
assign y = a<<s;
 Left shifts by 0 to 31 positions based on the 5-bit s input endmodule
 Each of its stages corresponds to a fixed shift by a power of 2 (16, 8, 4, 2, 1)
 Simple HDL implementation, which illustrates the power of HDL to hide
implementation details from a designer
Counters

 Stores an unsigned integer value

 Increments or decrements the value
 Used to count occurrences of
 Events
 Repetitions of a processing step
 Used as timers
 Count elapsed time intervals by incrementing periodically
Free-running Counter:

 Increments every rising edge of clock

 Up to –1, then wraps back to 0
 Counts modulo 𝑛
 This counter is synchronous
 All outputs governed by clock edge
Example: Periodic Control Signal

 Count modulo 16 clock cycles

 Control output = 1 every 8thand 12th cycle
 Decode count values 0111 and 1011

module decoded_counter ( output ctrl,

input clk );
reg [3:0] count_value;
always@(posedge clk)
count_value <= count_value + 1;
assign ctrl = count_value == 4'b0111
|| count_value == 4'b1011;
endmodule
 Fixed-point vs. Floating-point
 Fixed-point means allocating a fixed number of bits with a fixed pointer
position to represent numbers.
 Simpler for implementation
 Less accuracy

 Floating-point representation is provide a much more extensive means for

providing real number representations and tend to be used extensively in
scientific computation applications.
 More flexible/accuracy
 More complexity on implementation side (some times 10 times larger
hardware than fixed-point counterpart!)
 Verilog Operations: Fixed-Point Simulation
 For realization of DSP algorithms all variables should be converted
to the fixed-point representation

 Normally 2’s complement representation is used to represent signed numbers

 A fixed-point 2’s complement representation of a number has two parts:

 Integer part (WI bits)
 Fractional part (WF bits)

 The length of WI and WF are calculated based on the dynamic range of variables
 Total length: WI + WF
 Verilog Operations: Fixed-Point Simulation
 Typical word lengths:

 Fixed word-length dynamic range:

Verilog Operations: Fixed-Point Simulation
 2’s complement Representation: (WI , WF) format

Sing Bit

WI WF

0: positive
Sign Bit =
1: negative
 W  W 1  1 WF 
 Good to represent quantized numbers in the range: 2 I ,  2 I    
   2  
WF  
 Resolution : 
1

2
 Example:
 in (3,3) 011101 represents 3.625 (smallest number: 0.125)
 in (3,5) 10111000 represents -2.25 (smallest number: 0.03125)
Fixed-Point Simulation: Rounding
 Eliminates LSB bits
 Need to reduce the number of bits due to word growth
 For example, if we multiply two 5-bit words, the product will have 10 bits,
i.e., xxxxx × yyyyy = zzzzzzzzzz and we likely don’t want or need all that
precision

 Matlab rounding:
 round(∙): towards nearest integer
 Pos. and neg. numbers are rounded symmetrically about zero
 Generally the best possible rounding algorithm
 fix(∙): truncates towards zero
 Pos. and neg. numbers are rounded symmetrically about zero
 floor(∙): rounds towards negative infinity
 ceil(∙): rounds towards positive infinity
Fixed-Point Modeling: Casting
 Care must be taken when dealing with fixed-point numbers
 Casting: To convert a number with a larger bit length to a smaller one

A:

WI WF
W W
I I

W  W
F F
B:

WI WF

 B  {A[WI  WF - 1],A[WI  WF - 2 : WF  WF]}

 Saturation happens if:
“A” is positive and A[WI  WF - 2 : WI WF  1]  0
 “A” is negative and A[WI  WF - 2 : WI WF  1]  111...111(all one)
Fixed-Point Modeling: Casting
 Example: Saturation
WI WF
WI WF

(10,4) 0 0 0 0 1 1 0 1 1 1 0 1 0 0 (10,4) 0 0 0 1 1 1 0 1 1 1 0 1 0 0

(7,2) 0 1 1 0 1 1 1 0 1 (7,2) 0 1 1 1 1 1 1 1 1

WI WF WI WF

(10,4) 1 1 1 1 1 1 0 1 1 1 0 1 0 0 (10,4) 1 1 0 1 1 1 0 1 1 1 0 1 0 0

(6,3) 1 1 0 1 1 1 0 1 0 (6,3) 1 0 0 0 0 0 0 0 0
 Fixed-Point Modeling: Sign Extension
 To convert a number with a smaller bit length to a larger one sign extension
is required.
WI WF

A:
WI  WI (6,3) 1 1 0 1 1 1 0 1 0

WI WF WF  WF

B: 0 0
(10,4) 1 1 1 1 1 1 0 1 1 1 0 1 0 0

WI WF

assign B  {{n{A[WI  WF - 1]}},A,2'b0}

 Examples: Adding two numbers with different lengths:
wire [2:0] A;
wire [5:0] B;
wire [6:0] C;
assign C = {B[5],B} + {{4{A[2]}},A};
Verilog Operations: Addition with Same Length
 Adding two signed n-bit numbers and save it in a signed n-bit number:
 Might not be safe if two number are large A[n-1:0]
+
 Overflow condition should be checked B[n-1:0]

C[n-1:0]
 Overflow may happen if:
0110 1010
 A[n-1]==1 and B[n-1]==1 and C[n-1]==0 + +
0111 1001
 A[n-1]==0 and B[n-1]==0 and C[n-1]==1
1101 10011

assign SUM = B + A;
assign OV = (A[n-1]==1 && B[n-1]==1 && C[n-1]==0)||
(A[n-1]==0 && B[n-1]==0 && C[n-1]==1);

assign C = (OV && A[n-1] == 1) ? MIN_NEG_n : SUM;

assign C = (OV && A[n-1] == 0) ? MAX_POS_n : SUM;
 Floating-point
 In floating-point, the aim is to represent the real number using a sign (S),
exponent (Exp) and mantissa (or fraction).

𝐸𝑥𝑝−127

 The most widely used form of floating-point is IEEE Standard for Binary
Floating-Point Arithmetic (IEEE 754) with two major formats:
 Single-precision (32-bit)
 Double-precision (64-bit)
 Floating-point Implementation
 The floating-point implementation concurs a complicated hardware compared to
the fixed-point counterpart.
 Take into account as an example a floating-point adder!
 This additional logic is needed to perform the various normalization steps for the adder
implementation.
 Fixed-point vs. Floating-point
 The area comparison for floating-point is additionally complicated as the
relationship between multiplier and adder area is now changed.
 In fixed-point, multipliers are generally viewed to be N times bigger than
adders where N is the word length.
 However, in floating-point, the area of floating-point adders is comparable
to that of floating-point multipliers which corrupts the assumption at the
algorithmic stages to reduce number of multiplications in favor of additions.
 Table below gives some figures on area and speed figures for floating-point
addition and multiplication implemented in a Xilinx Virtex 4 FPGA
technology.
Verilog Operations: $signed and $unsigned
 A = $signed(B)
 Sign extends B and assigns it to A
 bit width(B) < bit width (A)
 Example
wire [5:0] A; A = 111110
assign A = $signed (3b’110);

 A = $unsigned (B)
 Zero fill B and assign it to A
 bit width(B) < bit width (A)
 Example
wire [5:0] A;
A = 000110
assign A = $unsigned (3b’110);
Verilog Operations: Signed Addition
 There are two ways to perform signed addition:
1. Sing Extension:
wire [2:0] A, B;
wire [3:0] SUM; Same result
assign SUM = {B[2],B} + {A[2],A};
1110 (-2)
0010 (+2)
2. Using signed signals
10000 (0)
wire signed [2:0] A, B; Discard Overflow
wire signed [3:0] SUM;
assign SUM = B + A;

 Wrong otherwise:
wire [2:0] A, B; 110 (-2)
wire [3:0] SUM; 010 (+2) (Wrong)
assign SUM = B + A; 1000 (-8)
Verilog Operations: Signed Addition with Carry-in
 There are two correct ways to perform signed addition with carry-in:
1. Sing Extension:

wire [2:0] A, B;
wire Cin; Same result
wire [3:0] SUM; (-2)
1110
assign SUM = {B[2],B} + {A[2],A} + Cin; 0010 (+2)
0001 Cin

2. Using signed signals 10001 (1)

Discard Overflow
wire signed [2:0] A, B;
wire Cin;
wire signed [3:0] SUM;
assign SUM = B + A + $signed({1’b0},Cin);
Verilog Operations: Signed Addition with Carry-in
 Incorrect Codes:
wire signed [2:0] A, B; 110 (-2)
wire Cin;
If any operand of an operation is
010 (+2)
wire signed [3:0] SUM; unsigned, the entire operation is
1 Cin
assign SUM = B + A + Cin; (9)
performed unsigned
1001

wire signed [2:0] A, B; (-2)

1110
wire signed Cin; 0010 (+2) When Cin=1, it sign extends it, to
wire signed [3:0] SUM; match the size of A and B,
1111 Cin
assign SUM = B + A + Cin; which is incorrect!
1111 (-1)

1110 (-2)
wire signed [2:0] A, B; When Cin=1, it sign extends it, to
wire Cin; 0010 (+2)
match the size of A and B,
wire signed [3:0] SUM; 1111 Cin
1111 (-1) which is incorrect!
assign SUM = B + A + $signed(Cin);
Verilog Operations: Signed Multiplication
 Use signed construct as we used for signed addition:
1. Use Verilog constructs:

wire signed [16:0] A, B;

wire signed [31:0] MULT;
assign MULT = A*B;

2. Write it manually as a module

Complicated!
 Verilog Operations: Signed Multiplication
 Multiplication of a signed number and an unsigned number:
 Correct:
wire signed [2:0] A; 110 (-2)
wire [2:0] B; 111 (7)
wire signed [5:0] PROD;
110010 (-14)
assign PROD = A*$signed({1’b0,B});

 Incorrect:
wire signed [2:0] A; wire signed [2:0] A;
wire [2:0] B; wire [2:0] B;
wire signed [5:0] PROD; wire signed [5:0] PROD;
assign PROD = A*$signed(B); assign PROD = A*B;

When B[2]==1, treats it as a negative number! Entire operation is performed unsigned

110 (-2) 110 (-2)
111 (7) treat it as (-1) 111 (7)
000010 (+2) 101010 (42)
Verilog Operations: Fixed Multiplication
 Sometimes one input is fixed so remove partial products that are always zero
 We have to try to find the minimum number of power-of-2 numbers to add
together to equal the fixed multiplier input
Verilog Operations: Fixed Multiplication
 Example: Multiply by 3:
input [7:0] in;
wire [9:0] product;
assign product = {in[7], in, 1’b0}
+ {in[7], in[7], in};

 Example: Multiply by 56:

56=32+16+8 56=64-8
input [7:0] in; input [7:0] in;
wire [13:0] product; wire [13:0] product;
assign product = assign product =
{in[7], in, 5’b00000} {in, 6’b00000}
+ {in[7], in[7], in, 4’b0000} - {in[7], in[7], in[7], in, 3’b000};
+ {in[7], in[7], in[7], in, 3’b000};
 Verilog Operations: Constant Multiplication
 Multiplication with a set of constant numbers may be implemented more
efficiently: P  ab b{-7,-5,-3,-1,1,3,5,7}
a
b
4
3
2
1

<<1 <<2 <<3

MSB

LSB

SUM SUM SUM

0111 b[4]

0101
1 0 1 0 1 0
0011
0001 0 1 0
b[2]  b[3]

1111
1101 1 0
b[3]b[4]  b[3]b[4]

1011
1001 P=axb
 Verilog Operations: Constant Multiplication
 Simpler way for implementation: P  ab b{-7,-5,-3,-1,1,3,5,7}
Area (um2) Critical Path Multiplier
1800 3.5 Constant MUL
12000 5.1 Normal MUL

a b
b
C.M. 0 <<1 <<2 <<3
4
3
2
1
MSB

LSB

1 0 1 0
b[2]  b[3]
0111
0101 b[1]b[2]b[3] 1 0 1 0
b[4]  b[3]
0011 +

0001 b[3]b[2]b[1]

1111
1101 1 0
b[4]
1011
1001 Constant Multiplier

P  ab
 Verilog Operations: Complex Multiplication
 A complex multiplication is equivalent to four real multiplications

(a  jb)(c  jd)  (ac  bd)  j(ad  bc)

 However, it can be efficiently realized using only three real multiplications:
(a  jb)(c  jd)  (ac  bd)  j(a b)(c  d) - (ac  bd)
(a+b)(c+d) Imag
a a+b

-
c+d
d

bd ac+bd
b

- Real
c ac ac-bd
 Pipelined Complex Multiplication
 Pipelined Implementation:
(a  jb)(c  jd)  (ac  bd)  j(a b)(c  d) - (ac  bd)

a+b (a+b)(c+d) Imag

a
-
c+d
d

bd ac+bd
b

- Real
c ac ac-bd
Squaring
 x2 can be done with about half the hardware of a full multiply (for a
dedicated squaring block, of course)

x3 x2 x1 x0 x3 x2 x1 x0
x0 x0
x1 x1
x2 x2
x3 x3

 Diagonals (x0 x0, x1 x1, …) can be replaced by the single input bit with
no computation for that bit b/c we have x0 AND x0= x0
Resource-Shared Complex Multiplication

 Operands: 4 integer, 12 fraction bits

 Result: 8 pre-, 24 post-binary-point bits
 Subject to tight area constraints

 4 multiplies, 1 add, 1 subtract

 Perform sequentially using 1 multiplier, 1 adder/subtracter
 Digital Systems

inputs n
General Architecture: Data Path
m outputs

 Data Path:
 Transfer input data signals into outputs
 Normally combinational logic or counters Controller
Clk

 Controller:
 Provides any control signal to determine the direction of data flow
 Examples: Reset, set, MUX select signals, …
 Sequential logic
Resource-Shared Complex Multiplication

 Data Path VLSI Architecture:

 Resource-Shared Complex Multiplication

 HDL Code:

 Control Path:
1. a_r * b_r →pp1_reg
2. a_i * b_i →pp2_reg
3. pp1 –pp2 →p_r_reg
a_r * b_i →pp1_reg
4. a_i * b_r →pp2_reg
5.pp1 + pp2 →p_i_reg

 Takes 5 clock cycles

 Resource-Shared Complex Multiplication

 Control Logic (Timing Schedule):

 Resource-Shared Complex Multiplication

 Control Logic Design:

 One state per step
 Separate idle state?
 Wait for input_rdy = 1
 Then proceed to steps 1, 2, ...
 But this wastes a cycle!
 Use step 1 as idle state
 Repeat step 1 if input_rdy ≠ 1
 Proceed to step 2 otherwise
 Resource-Shared Complex Multiplication
 Control Logic Design:
 Resource-Shared Complex Multiplication
 Control Logic Design:
Memories
 A memory is an array of storage locations
 Each with a unique address
 Like a register bank, but with optimized
implementation
 Address is unsigned-binary encoded
 n address bits 2n locations
 All locations the same size
 2n×m bit memory
Memory Sizes

 Use power-of-2 multipliers

 Kilo (K): 210= 1,024 ≈ 103
 Mega (M): 220= 1,048,576 ≈ 106
 Giga (G): 230= 1,073,741,824 ≈ 109
 Example:
 32K ×32-bit memory
 Capacity = 1,024K = 1Mbit
 Requires 15 address bits
 Size is determined by application requirements
Basic Memory Operations

 a inputs: unsigned address

 d_in and d_out
 Type depends on application
 Write operation
 en = 1, wr = 1
 d_in value stored in location given by address
inputs
 Read operation
 en = 1, wr = 0
 d_out driven with value of location given by
address inputs
 Idle: en = 0
 Wider Memories

 Memory components have a

fixed width

 E.g., ×1, ×4, ×8, ×16, ...

 Use memory components in

parallel to make a wider memory

 E.g, three 16K×16 components

for a 16K×48 memory
 Larger Memories

 To provide 2n locations with 2k-

location components

 Use 2n/2k components

 Larger Memories

 Example: 64K×8 memory

composed of 16K×8
components
Memory Types

 Random-Access Memory (RAM)

 Can read and write
 Static RAM (SRAM)
 Stores data so long as power is supplied
 Asynchronous SRAM: not clocked
 Synchronous SRAM (SSRAM): clocked
 Dynamic RAM (DRAM)
 Needs to be periodically refreshed
 Read-Only Memory (ROM)
 Combinational
 Programmable and Flash rewritable
 Volatile and non-volatile
 Verilog Memories: Single-Port vs. Dual-Port RAM
 Single-port RAM (SPRAM):
 Can only be accessed at one address at one time
 Read or Write (not both) one memory cell at a time in each clock cycle

 Dual-port RAM (DPRAM):

 Can be accessed at two addresses at one time
 Read & Write different memory cells at different addresses simultaneously

In Out In0 Out0

Write SPRAM Read In1 DPRAM Out1

Write Read

Add Add0 Add1

 Verilog Memories: Single-Port RAM
 256-Byte SPRAM:
 With chip select and read/write enable

module SPRAM ( clk , address , data, cs, we , oe);

// cs:chip select, we:Write/Read Enable, oe: Output Enable // CONTINUED
parameter DATA_WIDTH = 8 ; // Memory Write : when we = 1, cs = 1
parameter ADDR_WIDTH = 8 ; always @ (posedge clk)
parameter RAM_DEPTH = 1 << ADDR_WIDTH; begin : MEM_WRITE_READ
input [ADDR_WIDTH-1:0] address ; if ( cs && we )
input clk, cs, we, oe ; mem[address] <= data;
inout [DATA_WIDTH-1:0] data ; // Memory Read: when we = 0, oe = 1, cs = 1
reg [DATA_WIDTH-1:0] data_out ; else if (cs && !we && oe)
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; data_out <= mem[address];
//Tri-state buffer, Output: When we = 0 (read), oe = 1, cs = 1 end
assign data = (cs && oe && !we) ? data_out : 8'bz; endmodule
 Verilog Memories: Single-Port RAM
 256-Byte SPRAM:
 With chip select and read/write enable
cs

we
cs&!we&oe
oe
data
Clk CLK data_out
DATAOUT[7:0]

Clk
RADDR[7:0] EN
address
WADDR[7:0]

DATAIN[7:0] cs&!we&oe
cs&we
mem
(SYNC RAM)
 Verilog Memories: Dual-Port RAM
 256-Byte DPRAM:
 Two separate read/write operations

module SPRAM ( clk , address_0 , data_0, cs_0, we_0 , oe_0, // CONTINUED

address_1 , data_1, cs_1, we_1 , oe_1); // Memory Write : when we = 1, cs = 1
// cs:chip select, we:Write/Read Enable, oe: Output Enable always @ (posedge clk)
parameter DATA_WIDTH = 8 ; begin : MEM_WRITE_READ
parameter ADDR_WIDTH = 8 ; if ( cs_0 && we_0 )
parameter RAM_DEPTH = 1 << ADDR_WIDTH; mem[address_0] <= data_0;
input [ADDR_WIDTH-1:0] address_0, address_1 ; else if (cs_0 && !we_0 && oe_0)
input clk, cs_0, we_0 , oe_0, cs_1, we_1 , oe_1 ; data_out_0 <= mem[address_0];
inout [DATA_WIDTH-1:0] data_1, data_2 ; end
reg [DATA_WIDTH-1:0] data_out _0, data_out _1; if ( cs_1 && we_1 )
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; mem[address_1] <= data_1;
//Tri-state buffer, Output: When we = 0, oe = 1, cs = 1 else if (cs_1 && !we_1 && oe_1)
assign data _0= (cs_0 && oe_0 && !we_0) ? data_out _0: 8'bz; data_out_1 <= mem[address_1];
assign data _1= (cs_1 && oe_1&& !we_1) ? data_out _1: 8'bz; end
endmodule
 Verilog Memories: Dual-Port RAM
 256-Byte DPRAM: cs0

we0

oe0 cs0 & !we0 & oe0

data0
Clk CLK data_out0
DATAOUT[7:0]

Clk
address0 RADDR[7:0] EN
WADDR[7:0]

DATAIN[7:0] cs0 & !we0 & oe0

cs0 & we0
mem
(SYNC RAM)

cs1

we1

oe1 cs1 & !we1 & oe1

data1
Clk CLK data_out1
DATAOUT[7:0]

Clk
address1 RADDR[7:0] EN
WADDR[7:0]

DATAIN[7:0] cs1 & !we1 & oe1

cs1 & we1
mem_dual
(SYNC RAM)
 Verilog Memories: Dual-Port RAM
 256-Byte DPRAM: // CONTINUED
// Memory Write : when we = 1, cs = 1
 One write two reads simultaneously always @ (posedge clk)
begin : MEM_WRITE_READ
if ( cs_0 && we_0 )
module SPRAM ( clk , address_0 , data_0, cs_0, we_0 , oe_0,
mem[address_0] <= data_0;
address_1 , data_1, cs_1, we_1 , oe_1);
else if ( cs_1 && we_1 )
// cs:chip select, we:Write/Read Enable, oe: Output Enable
mem[address_1] <= data_1;
parameter DATA_WIDTH = 8 ;
end
parameter ADDR_WIDTH = 8 ;
end
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
always @ (posedge clk)
input [ADDR_WIDTH-1:0] address_0, address_1 ;
if (cs_0 && !we_0 && oe_0)
input clk, cs_0, we_0 , oe_0, cs_1, we_1 , oe_1 ;
data_out_0 <= mem[address_0];
inout [DATA_WIDTH-1:0] data_1, data_2 ;
else
reg [DATA_WIDTH-1:0] data_out _0, data_out _1;
data_out_0 <= 0;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
always @ (posedge clk)
//Tri-state buffer, Output: When we = 0, oe = 1, cs = 1
if (cs_1 && !we_1 && oe_1)
assign data _0= (cs_0 && oe_0 && !we_0) ? data_out _0: 8'bz;
data_out_1 <= mem[address_1];
assign data _1= (cs_1 && oe_1&& !we_1) ? data_out _1: 8'bz;
else
data_out_1 <= 0;
endmodule
 Verilog Memories: Dual-Port RAM
 256-Byte DPRAM: cs1

we1

oe1 cs1 & !we1 & oe1

1 data1
Clk CLK data_out1
DATAOUT[7:0]
00
Clk
RADDR[7:0] EN
WADDR[7:0] cs1 & !we1 & oe1
address1
DATAIN[7:0]
cs1 & we1
mem_dual
(SYNC RAM)

cs0 & we0 & !cs1 & !we1

1 data0
DATAIN[7:0] data_out0
DATAOUT[7:0]
00
address0 Clk
RADDR[7:0] EN
cs0 & !we0 & oe0
WADDR[7:0] cs0 & !we0 & oe0

Clk

cs0 mem
(SYNC RAM)
we0

oe0
FIFO
 First-In/First-Out buffer
 Connecting producer and consumer
 Decouples rates of production/consumption

 Implementation using dual-port RAM

 Circular buffer
 Full: write-addr = read-addr
 Empty: write-addr = read-addr
FIFO Example
 Design a FIFO to store up to 256 data items of 16-bits each, using
256x 16-bit dual-port SSRAM for the data storage. Assume the
FIFO will not be read when it is empty, not to be written when it
is full, and that the write and read ports share a common clock.
Verilog Memories: ROM
 For constant data, or CPU programs

 Masked ROM
 Data manufactured into the ROM

 Programmable ROM (PROM)

 Use a PROM programmer

 Erasable PROM (EPROM)

 UV erasable
 Electrically erasable (EEPROM)
 Flash RAM
 Verilog Memories: ROM
 ROM can be realized using two methods:
 Initialized using a file module ROMCase( address , data , read_en , ce );
 Initialized explicitly using case statement input [2:0] address;
output reg [7:0] data;
input read_en, ce;
module ROMFile( address , data , read_en , ce );
input [7:0] address; always @ (ce or read_en or address) begin
output [7:0] data; case (address)
input read_en, ce; 0 : data = 10;
reg [7:0] mem [0:255] ; 1 : data = 55;
assign data = (ce && read_en) ? mem[address] : 8'b0; 2 : data = 244;
initial 3 : data = 0;
begin 4 : data = 1;
$readmemb("memory.list", mem); 5: data = 8'hff; 6
// memory.list is the memory file : data = 8'h11; 7
end : data = 8'h1;
endmodule endcase
end
endmodule
 Function Implementation using look-up tables
 Complex or arbitrary functions are not uncommon
 Example:

 One way is to implement it using Look-

up Tables always @ (input) begin
case (input)
 Often best to write a Matlab program to 4’b0000: begin real=3’b100; imag=3’b001; end;
write the Verilog table as plain text 4’b0001: begin real=3’b000; imag=3’b101; end;
 Easy to adapt to other specifications 4’b0010: begin real=3’b110; imag=3’b011; end;
……
 Not efficient for very large tables default: begin real=3’bxxx; imag=3’bxxx; end;
 Tables with data that is less random will endcase
have smaller synthesized area end
Reviews and Notes
 Every Verilog statement must end with a semicolon “;”
 For comparison “==” has to be used not “=”

 When there are multiple assignments to the same variable in an always block,
the last statement is evaluated
 Example:
module DUT(Count );
output reg [2:0] Count;
integer k; module DUT(Count );
output reg [2:0] Count;
always @ (*) integer k;
begin
Count <= 0; always @ (*)
for (k=0; k<4; k=k+1) Counter
Count <= Count + 3; 3
Count <= Count + k; endmodule
end
endmodule
 Reviews and Notes
 Two codes with different simulation results might have the same synthesized circuit

always @ (a, b, c) always @ (a, b)

if (a & b & c) if (a & b & c) a b c I II
Out =0; Out =0;
else else 0 0 0 1 1
Out = 1; Out = 1; 0 0 1 1 1
0 1 0 1 1
I II 0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
a 1 1 0 1 1
b Out 1 1 1 0 1
c
Different Simulation

Same Synthesized Circuit

 Therefore, to avoid mismatch b/w simulation and synthesized version, the sensivity
list of always block should include all the signals on the RHS
 Coding Styles
 Do not mix blocking and non-blocking assignments in an always block
 Use parentheses to optimize logic structure
 Use meaningful names for signals, variables, and modules
 Define if-else and case statements explicitly to avoid latch inference
 Multiple procedural assignments (inside an always block) to a single variable is allowed.
 The last assignment is evaluated.
 Multiple continuous assignments (assign) to a single net in NOT allowed.
 Do not mix edge and level sensitive elements together
 Use assign statements for simple comb. logic and always block for complex comb. logic
 Avoid mixing positive-edge and negative-edge triggered flip-flops in one design
 Confuses the timing closure
Coding Styles : Parentheses
Coding Styles : Parentheses
 Difference b/w HDL and HLL (1)
 In HLL (high-level language) assignment order is important
 In HDL for “assign” and “non-blocking” assignments, order is NOT important
 Example:

a = 1; b=0; s=0; na=0; nb=0; a = 1; b=0; s=0; na=0; nb=0;

y = na|nb; nb = b&s;
HLL: nb = b&s; na = a&~s;
na = a&~s; k = a&b;
k = a&b; y = na|nb;

Result: y=0; Result: y=1;

b nb
wire na, nb; wire na, nb; s
y

HDL: assign y = na|nb; assign na = a&~s; na

assign nb = b&s; assign k = a&b; a
assign na = a&~s; assign nb = b&s;
assign k = a&b; assign y = na|nb; a k
b
The same!
 Difference b/w HDL and HLL (2)
 In HLL, multiple assignments to a single signal is allowed
 In HDL , multiple continuous assignments to a signal is NOT allowed.
 Example:

a = 1; b=0; s=0; na=0; nb=0;

y = na|nb;
HLL: na = b&s;
na = a&~s;

Result: na = a&~s;

wire na; b
s Illegal
HDL: assign y = na|nb; na
(only used for tri-state implementation)
assign na = b&s;
assign na = a&~s;
a