Memory Interfacing

A0 BHE Chip Data Data Lines

Selected Transfer
0 0 Even Word D0-D15

0 1 Even Byte D0-D7

1 0 Odd Byte D8-D15

 Basic concepts in memory interface
• μp 8086 can access 1 MB memory (since address lines are 20)

• Same as 8085 when EPROM is used for program memory and RAM is used
for data the space is shared between those two.

• Both RAM and EPROM capacities depends on application

• Multiple RAM and EPROM can be used.

• EPROM/RAM can be placed any where, but EPROM should be located at

last memory page1

• It is not always to locate EPROM and RAM in consecutive locations. (it is

advised to)

• Even bank is selected when A0=0 and odd if BHE=0

summarizes capacity with address
Memory Capacity Address lines required

1k 10
2k 11
4k 12
8k 13Slide 13: Absolute
addressing
16k 14Slide 15: Linear Decoding
32k 15
64k 16
128k 17
256k 18
512k 19
1 MB 20
 Memory interface requirements
• Select the chip
• Identify the register
• Enable the appropriate buffer.
• μp system includes memory and I/O devices
• μp can communicate with only one device1
• So decoding needed to communicate with memory and I/O
• So each device can be accessed independently.
• Three type of decoding:
• Absolute
• Linear
• block
2732 (4k x 8 ) EPROM

Pin Function

A0-A11 Address Lines

CE* Chip Enable

OE* Output Enable

O0-O7 Output Lines

Block diagram of 2732 EPROM
2764 UV EPROM (8k x 8)
Pin Function

A0-A12 Address Lines

CE*/E* Chip Enable

G*/OE* Output Enable

Q0-Q7/O0-O7 Output Lines

PGM*/P* Program

NC Not connected
Block diagram of 2764 UV EPROM
6116 CMOS RAM (2k x 8)
Pin Function

A0-A10 Address Lines

CS* Chip Enable

OE* Output Enable

WE* Write Enable

D0-D7 Output Lines

Block diagram of 6116 RAM
 Absolute decoding

• The memory chip is selected only for the specified logic level on
address lines; no other logic level can select the chip as shown below.

• Two 8K EPROMs (2764) are used to provide even and odd memory
banks (16 bits).

• Control signals BHE and A0 are used to enable O/P of odd and even
memory banks.

• 13 address lines are required to address 8K locations.(A1-A13)

• All remaining address lines (A14-A19) to generate chip select

• This technique is used in large memory system.

Absolute addressing
 Linear Decoding (Partial Decoding)

• In small system, H/W can be eliminated by using the required addressing lines 1.

• The figure below shows the addressing of 16K RAM (6264) with linear decoding

• BHE & A0 are used to enable odd & even banks.

• A19 is used to select the RAM2.

• A14 to A18 are not affect the chip selection

• This method reduces cost

• But it gives multiple (shadow) addresses

Linear Decoding
 Block Decoding

• In a μp system the memory array is often consists of

several blocks of memory chips

• Each block of memory requires decoding circuit.

• To avoid separate decoding for each memory block

special decoder IC is used to generate chip select signal
for each block.

• The figure below shows the block decoding using IC

74138 => 3:8 decoder
Block Decoding
Decoder 74LS138
 Decoding type comparison
Full Address Decoding Partial Address Decoding

All higher lines are decoded Few higher address lines are decoded

More H/W is required H/W design is less or eliminated

Higher cost Less cost

No multiple addresses It has multiple address (shadow address)

Used in large system Used in small system

Design memory system for 8086 μp such that it should
contain 8 KB of EPROM and 8 KB of RAM. Minimum
mode.
Sol:
•The figure below shows the desired memory system
using IC 2764 (8K) EPROM and 6264 (8k) RAM.
•Memory requires 13 address lines (A0-A12)
•The remaining address lines (A13-A15) are decoded to
generate chip select (CS) signals.
•IC 74SL138 is used as decoder, when (A13-A15) address
lines are 0 the Y0 output of decoder goes low and select
the EPROM. other line to select the particular memory
location.
•When these lines are 001, the Y1 output of decoder goes
low and selects the RAM.
 MEMORY MAP FOR 8K EPROM AND 8 K RAM

CHIPS A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS

1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 FE000H
EPROM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH
0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1E000H
RAM
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFFFH

Microprocessor Data Bus Address bus

8086 16 20

8088 8 20
 Example

• Design an 8086 based system with the following specifications:

• 8086 in minimum mode

• 64 KB EPROM

• 64 KB RAM

• Draw the complete schematic of the design indicating address map.

Sol: 8086 is 16 bit μp so it is necessary to have odd and even memory banks.

• Two 32 KB EPROMs and two 32 KB RAMs1

• For 32 KB RAM & EPROM need 15 address lines (A1-A15)

• A0 & BHE are used to select even and odd banks

 MEMORY MAP FOR 64K EPROM AND 64K
RAM USING TWO 32 K EROM AND 32K RAM

ADDRES
CHIPS BHE A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
S
EVEN 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0000H
EPROM 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFFEH
ODD 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 F0001H
EPROM 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH
0

EVEN 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30000H
RAM 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 3FFFEH
ODD 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 30001H
RAM 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 3FFFFH
Design an 8086 based system with the following specifications:

8086 in MAXIMUM mode

64 KB EPROM

64 KB RAM

Draw the complete schematic of the design indicating address map.

Sol: 8086 is 16 bit μp so it is necessary to have odd and even memory banks.

Two 32 KB EPROMs and two 32 KB RAMs1

For 32 KB RAM & EPROM need 15 address lines (A1-A15)

A0 & BHE are used to select even and odd banks