EXP 2 :Creating a symbol using Quartus II

Half and Full adder

Objectives:
The aim of this lab is creating a symbol from a schematic (BDF file), then use it in a
new project to perform a specific task.

Introduction:
 HALF ADDER

The half adder adds two single binary digits A and B. It has two outputs, sum (S) and
carry (C). The carry signal represents an overflow into the next digit of a multi-digit
addition.

The truth table for the half adder is:

Inputs Outputs

A B C S

0 0 0 0

1 0 0 1

0 1 0 1

1 1 1 0

The Boolean logic for the sum (in this case S) will be A'B+AB' (A XOR B), whereas for
carry (C) will be AB.

Figure 1

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  FULL ADDER

A full adder adds binary numbers for values carried in as well as out. A one-bit full-adder
adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and
Cin is a bit carried in from the previous less-significant stage.
The truth table for the full adder is:

Inputs Outputs

A B Cin Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

A full adder can be constructed from two half adders by connecting A and B to the input
of one half adder, then taking its sum-output(S) as one of the inputs to the second half
adder and Cin as its other input, and finally the carry-outputs from the two half-adders are
connected to an OR gate. The sum-output from the second half-adder is the final Sum-
output (S) of the Full-Adder and the output from the OR gate is the final Carry-output
(Cout ).
Two half adders can be combined to make a full adder.

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 Figure 2

Figure 3

Procedure:

Part one: Design the Half Adder

To start working on a new design (HALF ADDER ) we first have to define a new
design project. Create a new project as follows:

1. Select File > New Project Wizard to reach the window below, which asks for the
name and directory of the project.

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 Figure 4

2. Set the working directory to be ARCH_LAB; of course, you can use some other
directory name of your choice if you prefer. The project must have a name,
which is usually the same as the top-level design entity that will be included in
the project. Choose half_adder as the name for both the project and the top-
level entity, Press Next. Since we have not yet created the directory
ARCH_LAB, Quartus II software displays the pop-up box in Figure 5 asking if it
should create the desired directory. Click Yes, which leads to the window in
Figure 5.

Figure 5

3. The wizard makes it easy to specify which existing files (if any) should be
included in the project. Assuming that we do not have any existing files, click
Next, which leads to the window in Figure 6.

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 Figure 6

4. We have to specify the type of device in which the designed circuit will be
implemented. Choose Cyclone II as the target device family. We can let Quartus
II software select a specific device in the family, or we can choose the device
explicitly. We will take the latter approach. From the list of available devices,
choose the device called EP2C5F256C6 which is the FPGA used on Altera’s
DE2 board. Press Next, which opens the window in Figure 7. Click next twice.

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 Figure 7

5. A summary of the chosen settings appears in the screen shown in Figure 8.

Press Finish.

Figure 8

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 6. The Quartus II Graphic Editor can be used to specify a circuit in the form of a
block diagram. Select File > New Block Diagram/Schematic File.

Now build the half adder as in figure 1.

Figure 9

7. Compile the design from processing menu > start compilation.

8. After the compilation is successful create a vector waveform file for the
simulation File > new >choose vector waveform.

9. To include the input and the output nodes of the circuit to be simulated. Click
Edit > Insert >Insert Node or Bus to open the window in Figure 10.

Figure 10

It is possible to type the name of a signal (pin) into the Name box, but it is
easier to click on the button labeled Node Finder to open the window in
Figure 11. The Node Finder utility has a filter used to indicate what type of
nodes are to be found. Since we are interested in input and output pins, set
the filter to Pins: all. Click the List button to find the input and output nodes as
indicated on the left side of the figure.

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 Figure 11

Figure 12

10. We will now specify the logic values to be used for the input A and B during
simulation. The logic values at the outputs S and C will be generated
automatically by the simulator.

Figure
13

11. To perform the functional simulation, select Assignments > Settings to open the
Settings window. On the left side of this window click on Simulator Settings to
display the window in Figure 37, choose Functional as the simulation mode, and

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 click OK. The Quartus II simulator takes the inputs and generates the outputs
defined in the half_adder.vwf file.

12. Before running the functional simulation it is necessary to create the required
netlist, which is done by selecting Processing > Generate Functional Simulation
Netlist. A simulation run is started by Processing > Start Simulation, or by using
the icon . At the end of the simulation, Quartus II software indicates its
successful completion and displays a Simulation Report illustrated in Figure 14.
If your report window does not show the entire simulation time range, click on
the report window to select it. Observe that the outputs S and C are as specified
in their truth table(Figure 15).

Figure 14

Figure 15

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 13. Now we can create a symbol for this design , go to file > create/update > create
symbol files for current file, save it.

Figure 16

Part Two: Design the Full Adder using two Half Adders

1. create a new project called full_adder in the same directory of the symbol of
half_adder, if not, we will add the symbol while we are creating the project in
step 2.

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 Figure 17

2. In the following figure add the symbol of the half adder to the project from its
directory ( ARCH_LAB), click add

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 Figure 18

3. Create a new block diagram/schematic file.

4. Insert two half adders to the workspace, click on the symbol tool.
5. You will find the symbol in a library called project.
6. Complete the design of the full adder as in the following figure.

Figure 19

6. Compile and simulate as we did previously with the Half adder.

The next vector waveform represents a sample of the output for the full adder

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Figure 20

And that’s all

The End

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