WHK GSG ZKF Qur TNBN

CustomSim™ Command
Reference
Version H-2013.03, March 2013
Copyright and Proprietary Information Notice
Copyright © 2013 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary
information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and
may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may
be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without
prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America.
Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to
determine the applicable regulations and to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
http://www.synopsys.com/Company/Pages/Trademarks.aspx.
All other product or company names may be trademarks of their respective owners.
Synopsys, Inc.
700 E. Middlefield Road
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www.synopsys.com
Printed in U.S.A.
ii CustomSim™ Command Reference

H-2013.03
Contents
Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1. Using CustomSim Commands and Options . . . . . . . . . . . . . . . . . . . . . . . . 1

Using CustomSim Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Using a Command Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Using Commands Within the Netlist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Using Commands During Interactive Debugging Mode . . . . . . . . . . . . . . 2
Interactive mode with Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . 3
Enabling Tcl Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Common Syntax Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Command Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. CustomSim Batch Command Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

add_rc_element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
check_node_excess_rf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
check_node_hotspot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
check_node_quick_rf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
check_node_zstate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
check_timing_edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
check_timing_hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
check_timing_pulse_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
check_timing_setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
enable_print_statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
force_node_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
keep_top_element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
load_ba_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
iii
Contents
load_operating_point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
load_parameter_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
load_vector_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
load_verilog_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
map_ba_terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
meas_post . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
probe_waveform_current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
probe_waveform_logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
probe_waveform_va. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
probe_waveform_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
pulse_oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
release_node_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
report_dangling_node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
report_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
report_node_alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
report_node_cap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
report_operating_point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
report_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
set_active_net_flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
set_ams_view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
set_array_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
set_ba_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
set_bus_format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
set_capacitor_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
set_ccap_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
set_ccap_option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
set_dc_option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
set_duplicate_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
set_flash_option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
set_floating_node. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
set_hotspot_option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
iv
Contents
set_inductor_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
set_logic_threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
set_measure_format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
set_message_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
set_model_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
set_model_option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
set_monte_carlo_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
set_multi_core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
set_multi_rate_option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
set_oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
set_partition_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
set_powernet_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
set_powernet_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
set_probe_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
set_probe_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
set_resistor_option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
set_restore_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
set_sample_point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
set_save_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
set_sim_case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
set_sim_hierid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
set_sim_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
set_sram_characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
set_synchronization_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
set_synchronization_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
set_tolerance_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
set_tolerance_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
set_vector_option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
set_waveform_format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
set_waveform_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
set_wildcard_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
v
Contents
set_zstate_option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
skip_circuit_block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
3. CustomSim Interactive Command Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . 175

alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
icheck_node_zstate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
iclose_log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
icontinue_sim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
idelete_break_point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
iforce_node_voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
ilist_break_point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
ilist_force_node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
imatch_elem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
imatch_node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
iopen_log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
iprint_connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
iprint_dcpath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
iprint_elem_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
iprint_exi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
iprint_flash_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
iprint_help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
iprint_node_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
iprint_subckt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
iprint_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
iprint_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
iprobe_waveform_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
iquit_sim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
irelease_node_voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
ireport_node_cap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
ireport_operating_point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
vi
Contents
isearch_node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
iset_break_point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
iset_diagnostic_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
iset_interactive_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
iset_save_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
iset_zstate_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
A. Converting WDF and FSDB Waveform Output File Formats . . . . . . . . . . . 217

Using the convert2out Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
convert2out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
vii
Contents
viii
About This Manual
This manual describes the Synopsys CustomSim™ batch and interactive

commands and options.
This chapter describes:
■ Related Publications.
■
Conventions used in this manual.
■
How to access Customer Support.
Related Publications
For additional information about the CustomSim tool, see
■
The documentation installed with the CustomSim software.
■ The CustomSim Release Notes, available on SolvNet (see Accessing
SolvNet on page xi)
■
Documentation on the Web, which provides HTML and PDF documents and
is available on SolvNet (see Accessing SolvNet on page xi)
You might also want to refer to the documentation for the following related
Synopsys (and third-party) products:
■ HSPICE®
■
Eldo™
■
Spectre®
CustomSim™ Command Reference ix

H-2013.03
Conventions
Conventions
The following conventions are used in Synopsys documentation.
Convention Description
Courier Indicates command syntax.
Italic Indicates a user-defined value, such as object_name.
■
Purple Within an example, indicates information of special
interest.
■
Within a command-syntax section, indicates a default
value, such as:
include_enclosing = true | false
■
Bold Within syntax and examples, indicates user input—text
you type verbatim.
■
Indicates a graphical user interface (GUI) element that has
an action associated with it.
[] Denotes optional parameters, such as:

write_file [-f filename]
... Indicates that parameters can be repeated as many times as

necessary:
pin1 pin2 ... pinN
| Indicates a choice among alternatives, such as

low | medium | high
\ Indicates a continuation of a command line.
/ Indicates levels of directory structure.
Edit > Copy Indicates a path to a menu command, such as opening the
Edit menu and choosing Copy.
Ctrl+C Indicates a keyboard combination, such as holding down the

Ctrl key and pressing the C key.
x CustomSim™ Command Reference

H-2013.03
Customer Support
Convention Description
{} Indicates a definition that can be repeated as many times as

necessary. For example: [-node] {node_name
node_name}
Customer Support
Customer support is available through SolvNet online customer support and
through contacting the Synopsys Tecnical Support Center.
Accessing SolvNet
SolvNet includes an electronic knowledge base of technical articles and
answers to frequently asked questions about Synopsys tools. SolvNet also
gives you access to a wide range of Synopsys online services, which include
downloading software, viewing Documentation on the Web, and entering a call
to the Support Center.
To access SolvNet:
1. Go to the SolvNet Web page at http://solvnet.synopsys.com.
2. If prompted, enter your user name and password. (If you do not have a
Synopsys user name and password, follow the instructions to register with
SolvNet.)
If you need help using SolvNet, click Help on the SolvNet menu bar.
Contacting the Synopsys Technical Support Center

If you have problems, questions, or suggestions, you can contact the Synopsys
Technical Support Center in the following ways:
■
Open a call to your local support center from the Web by going to
http://solvnet.synopsys.com/EnterACall (Synopsys user name and
password required).
■
Send an e-mail message to your local support center.
• E-mail [email protected] from within North America.
CustomSim™ Command Reference xi

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Customer Support
• Find other local support center e-mail addresses at

http://www.synopsys.com/support/support_ctr.
■ Telephone your local support center.
• Call (800) 245-8005 from within the continental United States.
• Call (650) 584-4200 from Canada.
• Find other local support center telephone numbers at
http://www.synopsys.com/support/support_ctr.
xii CustomSim™ Command Reference

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1
1 Using CustomSim Commands and Options
Describes how to use CustomSim commands and options.
This chapter describes:

■
Using CustomSim Commands
■
Common Syntax Definitions
■ Command Categories

CustomSim commands are used to control simulator options and features. You
can enter the commands in any of the following ways:
■
Using a Command Script File
■
Using Commands Within the Netlist
■ Using Commands During Interactive Debugging Mode
All commands and their arguments are case-sensitive—even those commands
placed within HSPICE and Eldo netlists. Command arguments that refer to
netlist identifiers are treated as case-insensitive in HSPICE and Eldo format
netlists, and as case-sensitive in Spectre format netlists. See the CustomSim
User Guide for more information about working with HSPICE, Eldo, or Spectre
netlists. Degree symbol test: 28°.
See the CustomSim User Guide for details about the syntax of the CustomSim
command itself, in “Starting the Simulator.”
The CustomSim tool uses Tcl, which is a non-proprietary scripting language, as
its command language. To facilitate simple and easy use, many of the Tcl
features are disabled by default. No previous knowledge of Tcl is required to
CustomSim™ Command Reference 1

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Chapter 1: Using CustomSim Commands and Options
use CustomSim commands. You can also set the CustomSim tool to use a full
Tcl interpreter, as described in Enabling Tcl Mode.
Using a Command Script File

To use a command script file, enter a -c switch on the command line when
starting the CustomSim tool, as shown in the following example:
xa netlist.sp -c command_file
All commands and settings in the command file are processed as if the
command were placed on the final line of the netlist. That is, the commands
used in the command file override any CustomSim commands used in the
netlist file.
Using Commands Within the Netlist

Enter CustomSim commands directly into the netlist using the .option or
options statement appropriate for that netlist.
HSPICE and Eldo syntax netlists use an .option command to insert the
CustomSim tool-specific commands into a netlist. See the following syntax:
.opt[ion] XA_CMD="xa_command arg arg arg"
For example:
.option XA_CMD="set_sim_level -level 5"
Spectre format netlists use an options analysis statement. See the following
syntax:
user_xa_commands options xa_cmd="xa_command arg arg arg"
For example:
myoptions options xa_cmd="set_sim_level -level 5"
Using Commands During Interactive Debugging Mode

The CustomSim tool provides an interactive mode, in which you can enter
commands at the XA > command prompt. The CustomSim tool interactive
mode commands are listed in Chapter 3, CustomSim Interactive Command
Syntax.
2 CustomSim™ Command Reference

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To enter the CustomSim tool interactive mode, use the -intr command-line
flag. This command-line flag is used for all supported netlist formats.
-intr [time[unit]]
time
The time at which the CustomSim tool enters interactive mode. If you do not
specify a time, the CustomSim tool does not enter interactive mode until you
enter Ctrl-C.
unit
The unit of measure for time. Default is second. There can be no space
between the time and the unit, or the CustomSim tool terminates the
simulation with an error message.
Ctrl-C
After entering the -intr flag, you can optionally press Ctrl-C to enter
interactive mode.
Important: If you do not specify -intr on the command line, the
CustomSim tool cannot enter interactive mode. If you
enter Ctrl-C, the CustomSim tool prompts you to abort
or continue the simulation.
Interactive mode with Tcl Commands

The interactive mode defaults to the Tcl OFF mode. You can change to Tcl ON
using the -tcl command-line flag. All Tcl syntax rules are applied in the Tcl
ON mode.
Please refer to the Enabling Tcl Mode section for the special characters in the
Tcl on mode.
Enabling Tcl Mode

When invoking the simulator, a full Tcl interpreter can be enabled by using the
-tcl switch on the command line (Tcl ON behavior). The Tcl mode cannot be

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toggled on-and-off during a session—see Table 1.

Table 1 Tcl on-and-off behavior
Character Tcl ON behavior Tcl OFF behavior
$ Variable substitution Literal $
[ ] Command substitution Literal [ ]
\ Backslash substitution Same as Tcl ON
“ ” Argument grouping Same as Tcl ON
{ } Argument grouping Same as Tcl ON
# Comment if first character on Same as Tcl ON

line
; End of command delimiter Same as Tcl ON

The standard syntax conventions are documented in the Conventions section
of this manual. There are also some common syntax definitions shared
between many CustomSim commands, described in this section.
Several commands use enable_value as an argument. Possible values are:
Table 2 Possible values for the enable_value argument
Positive Negative
1 0
yes no
true false
on off
Several commands use the instance_spec argument. The instance_spec

argument can take one of three different forms as shown:

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Syntax
-inst inst_name [...]
-subckt subckt_name [...]
-inst inst_name [...] -subckt subckt_name [...]
Arguments
Argument Description
inst_name The name of the instance to which the command

applies. A full hierarchical instance name can be
supplied. Wild cards are allowed.
subckt_name The name of the subcircuit to which the

command applies. The command is applied to all
instances of that subcircuit type.
Description
Commands such as set_sim_level and set_ams_view take
instance_spec as an argument. The instance_spec argument specifies
the instances upon which the command is applied. The -inst switch is used
alone to provide a set of instance names. The -subckt switch is used alone to
provide a set of subcircuit names. When both the -inst and -subckt
switches are used, the command is applied to the named instances—only in
the named subcircuit.
Example
Example 1 applies a command to instances x1.x2 and x1.x4:
Example 1
-inst x1.x2 x1.x4
Example 2 applies a command to all instances of the subcircuit pll:

Example 2
-subckt pll
Example 3 applies a command to all MOSFET transistor instances in the

subcircuit chgpump:
Example 3
-inst m* -subckt chgpump

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Command Categories
Example 4 applies a command to all instances X1 and X2 in subcircuits sub1

and sub2:
Example 4
-inst X1 X2 -subckt sub1 sub2
An equivalent instance_spec to that previously shown:

-inst X1 X2 -subckt sub1
-inst X1 X2 -subckt sub2
Command Categories
Table 3 categorizes the CustomSim batch commands. See for a list of the
interactive commands, see Chapter 3, CustomSim Interactive Command
Syntax.
Table 3 CustomSim command categories
Command Category Command
Diagnostics check_node_excess_rf
check_node_hotspot
check_node_quick_rf
check_node_zstate
check_timing_edge
check_timing_hold
check_timing_pulse_width
check_timing_setup
force_node_voltage
probe_waveform_current
probe_waveform_logic
probe_waveform_va
probe_waveform_voltage
release_node_voltage
report_power
set_hotspot_option
set_sample_point
set_zstate_option

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Command Categories
Table 3 CustomSim command categories
Command Category Command
Netlist Control keep_top_element

pulse_oscillator
set_ams_view
set_capacitor_option
set_duplicate_rule
set_flash_option
set_floating_node
set_inductor_option
set_logic_threshold
set_resistor_option
set_wildcard_rule
skip_circuit_block
Output Control enable_print_statement

report_model
report_operating_point
set_measure_format
set_message_option
set_probe_option
set_probe_window
set_waveform_option
Post-layout / load_ba_file
Back-annotation map_ba_terminal
set_ba_option
Speed and Accuracy set_ccap_level

Control set_dc_option
set_model_level
set_model_option
set_oscillator
set_partition_option
set_powernet_option
set_sample_point
set_sim_level
set_tolerance_level
set_tolerance_option
Vector Stimulus load_vector_file

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Command Categories

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2
2 CustomSim Batch Command Syntax
Provides the syntax for all of the CustomSim batch commands.
The CustomSim commands are:

add_rc_element
check_node_excess_rf
check_node_hotspot
check_node_quick_rf
check_node_zstate
check_timing_edge
check_timing_hold
check_timing_setup
enable_print_statement
force_node_voltage
keep_top_element
load_ba_file
load_operating_point
load_parameter_file
load_vector_file
load_verilog_file
map_ba_terminal
meas_post
probe_waveform_va
pulse_oscillator
report_dangling_node
report_model

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Chapter 2: CustomSim Batch Command Syntax
report_node_alias
report_node_cap
report_power
set_active_net_flow
set_ams_view
set_array_option
set_ba_option
set_bus_format
set_ccap_level
set_ccap_option
set_dc_option
set_duplicate_rule
set_flash_option
set_floating_node
set_hotspot_option
set_inductor_option
set_logic_threshold
set_measure_format
set_message_option
set_model_level
set_model_option
set_monte_carlo_option
set_multi_core
set_multi_rate_option
set_oscillator
set_powernet_level
set_powernet_option
set_probe_option
set_probe_window
set_resistor_option
set_restore_option
set_sample_point
set_save_state
set_sim_case
set_sim_hierid
set_sim_level
set_sram_characterization
set_synchronization_level

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add_rc_element
set_synchronization_option
set_tolerance_level
set_vector_option
set_waveform_option
set_wildcard_rule
set_zstate_option
skip_circuit_block
source
add_rc_element
Inserts a resistor or capacitor between two nodes. If you specify a subcircuit,
the extra resistance or capacitance element is inserted between the two nodes
locally inside the subcircuit.
Syntax
add_rc_element -type (r|R|c|C) -n1 node1 -n2 node2 -val RCval
-subckt subcircuit_name
-type (r|R|c|C) Specifies if the element to be added is a resistor or

capacitor.
-n1 node1 Specifies that the first node of the element is connected
to node1, which a port, global, or local node to the
subcircuit name.
-n2 node2 Specifies that the second node of the element is

connected to node2, which a port, global, or local node
to the subcircuit name.
-val RCval Specifies the value of the element connected between

node1 and node2. Units are in Ohm for resistors and
Farads for capacitors.
-subckt Adds the elements to the specified subcircuit.

subcircuit_name

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Examples
add_rc_element -type R -n1 nv1 -n2 vdd -val 1e6 -subckt memcell
Adds a resistor with a value of 1e6 Ohm between nodes nv1 and vdd inside
the memcell subcircuit.
Performs an excessive rise/fall timing check.
Syntax
check_node_excess_rf -node node_name {node_name}
-title title_name [-fanout value] [-rtime rise_time]
[-ftime fall_time] [-utime ustate_time]
[-loth logic_low_voltage] [-hith logic_high_voltage]
[-twindow tstart [{tstop}] {tstart [tstop]}]
[-subckt subckt_name] [-error_file output_file_name]
[-limit level]
-node node_name Defines the signal node name, which can be the node
{node_name} name of a single node or a node name with the asterisk (*)
wildcard character that represents a group of node names.
The behavior of asterisk (*) character is controlled by
set_wildcard_rule on page 169.
You must specify this argument first.
-title title_name Defines the title name of this excess rise/fall time check.
Errors that occur during this check are listed in the .errt
file. The name of the excessive rise/fall time error starts
with this title name. This name is useful when there are
multiple excessive rise/fall time checks used for a single
run.

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-fanout value Defines the fanout of driver nodes. If fanout is set to 1

(one), only the driver nodes with fanouts are checked to
avoid an unnecessary check on internal nodes within logic
gates. If fanout is set to 0 (zero), both the internal node and
the driver node are checked. For example:
fanout=0: all nodes (the default).
fanout=1: nodes that have direct connection to transistor
gate.
bulk.
-rtime rise_time Defines the rise time of the signal as time duration t2–t1.
t1 is the time when the rising signal voltage crosses the
voltage level logic_low_voltage. t2 is the time when
the same continuously rising signal voltage crosses the
voltage level logic_high_voltage. The default value is
1 ns.
-ftime fall_time Defines the fall time of the signal as t4-t3. t3 is the time
when the falling signal voltage crosses the voltage
logic_high_voltage. t4 is the time when the same
continuously falling signal voltage crosses the voltage
logic_low_voltage. The default value is 1 ns.
-utime ustate_time Defines the time period when the signal voltage is
between logic_low_voltage and
logic_high_voltage. The default is 1ns. Note that
-utime checking is only performed when a transition is
incomplete, which means it fails to go from low-to-high or
high-to-low.
-loth Defines the logic low voltage for the signal. The default is
logic_low_voltage the same as the set_logic_threshold value.
-hith Defines the logic high voltage for the signal and ref node.
logic_high_voltage The default is the same as the set_logic_threshold value.

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-twindow tstart Performs the check within the time window defined by
tstop {tstart tstart tstop {tstart tstop}. The tstart and
tstop} tstop must come in pairs, except for the final window
where if tstop is not specified it is be assumed to be the
end of the simulation. The final tstop can also be the end
or END keyword.
-subckt Performs the operation on all instances of the specified

subcircuit_name subcircuit. A wildcard character is not allowed when you
specify the using the subcircuit_name.
-error_file Specifies the output error file name for any excessive rise/
output_file_name fall time violations. If the output file name is not specified,
the default output file use the output prefix name by –o
follow by .errt.
For example, if –o xa_default, then the output error file
is xa_default.errt. If –error_file is specified, the
output file name is the user-specified
output_file_name with the .errt extension.
-limit level Specifies the hierarchical depth to which the nodes are
printed when the asterisk (*) characters are used as the
first character of a node name or subcircuit name. If not
specified, this setting defaults to 3.
Description
When performing an excess rise/fall time check, if violations occur, they are
stored in a new CustomSim output file, output_file_name.err. The output
file name is the prefix name from the XA –o command line argument. If –o is
not specified, it is the prefix of the input file name.
By default, the CustomSim tool uses 30%/70% as the logic threshold value
based on the rail-to-rail voltage it detects on the signal. The logic threshold
value can be modified by the set_logic_thresholdcommand. If –loth and –
hith are specified, they take precedence over the default logic threshold value
specified by the set_logic_threshold command if the same node name is
applied to both commands.
Examples
check_node_excess_rf -node output -title exrf_check1 -rtime \
2ns -ftime 2ns

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check_node_hotspot
Sets up excessive rise/fall time check with output signal with title name
exrf_check1, and rise time of 2ns and fall time of 2ns.
check_node_excess_rf –node output –title exrf_check1 \
-rtime 2ns -ftime 2ns -twindow 50ns 1000ns
Same as the previous example, but adds a start time of 50ns and stop time of
1000ns.
check_node_excess_rf –node output –title exrf_check1 \
-rtime 2ns -ftime 2ns –utime 2ns -twindow 50ns 200ns 400ns \
800ns
Same as the previous example, but adds multiple start and stop time, start at
50ns stop at 200ns then start at 400ns and stop at 800ns. It also adds a
u-state check of 2ns.
check_node_excess_rf –node dout* –title exrf_check1 \
-rtime 2ns -ftime 2ns -error_file xa_excessive_rise_fall
Same as the first example, but adds a wildcard (*) to match multiple signals and
appends the output violation file to xa_excessive_rise_fall.errt.
check_node_hotspot
Checks for hot spots in a design.
Syntax
check_node_hotspot -node node_name {node_name}
-node node_name Specifies the node names to check for hot spots.
{node_name}
Description
This command checks for hot spots in a design and reports the information in
an output file with prefix of .hotspot. Note that hot spot node analysis does
not apply to input nodes.
The information for each specified node includes:
■
Average node capacitance
• Lumped from netlist, wiring, transistor gate, and diffusion capacitances.

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check_node_quick_rf
■
Toggle count
• Total number of logic toggles for the node.
■
Average charging current
• Average current flowing into the capacitances connected to the node.
■
Average discharge current
• Average current flowing out of the capacitances connected to the node.
At the end of the output file, check_node_hotspot also reports:
■
Total number of non-input nodes.
■
Total number of nodes toggling.
■
Total charging current.
■
Total discharging current.
By default, nodes are not reported when the sum of the capacitive charging and
discharging currents is less than the hot spot factor of 0.5 multiplied by the
sum of the node with the largest capacitive currents. You can modify this
suppression of small current nodes with the set_hotspot_option command.
check_node_quick_rf
Performs a quick rise/fall timing check.
Syntax
check_node_quick_rf -node node_name {node_name}
-title title_name [-fanout value] [-rtime rise_time]
[-ftime fall_time] [-loth logic_low_voltage]
[-hith logic_high_voltage]
[-twindow tstart [{tstop}] {tstart [tstop]}]
[-subckt subckt_name] [-error_file file_name]
[-limit level] [-except_node node_name {node_name}]

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check_node_quick_rf
-node node_name Defines the signal node name, which can be the node
{node_name} name of a single node or a node name with the asterisk (*)
The behavior of asterisk (*) character is controlled by
set_wildcard_rule on page 169.
You must specify this argument first.
-title title_name Defines the title name of this quick rise/fall time check.
file. The name of the quick rise/fall time error starts with
this title name. This name is useful when there are multiple
quick rise/fall time checks used for a single run.
-fanout value Defines the fanout of driver nodes. If fanout is set to 1

(one), only the driver nodes with fanouts are checked to
avoid an unnecessary check on internal nodes within logic
gates. If fanout is set to 0 (zero), both the internal node and
the driver node are checked. For example:
fanout=0: all nodes (the default).
gate.
bulk.
-rtime rise_time Defines the rise time of the signal as time duration t2–t1.
t1 is the time when the rising signal voltage crosses the
voltage level logic_low_voltage. t2 is the time when
the same continuously rising signal voltage crosses the
voltage level logic_high_voltage The default value is
1 ns.
-ftime fall_time Defines the fall time of the signal as t4-t3. t3 is the time
when the falling signal voltage crosses the voltage
logic_high_voltage. t4 is the time when the same
continuously falling signal voltage crosses the voltage
logic_low_voltage. The default value is 1 ns.

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check_node_quick_rf
-hith Defines the logic high voltage for the signal and ref node.
logic_high_voltage The default is the same as the set_logic_threshold value.
or END keyword.

specify the subckt_name.
-error_file Specifies the output error file name for any excessive rise/
output_file_name fall time violations. If the output file name is not specified,
the default output file use the output prefix name by –o
follow by .errt.
-limit level Specifies the hierarchical depth to which the nodes are
printed when the asterisk (*) characters are used as the
first character of a node name or subcircuit name. If not
specified, this setting defaults to 3.
-except_node Specifies the nodes to be excluded from quick rise/fall time

node_name checking. You can use a wildcard character in the node
{node_name} name.
Description
When performing an quick rise/fall time check, if violations occur, they are
stored in a new CustomSim output file, output_file_name.errt. The output
not specified, the default input file name prefix is xa.
value can be modified by the set_logic_thresholdcommand. If –loth and –

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check_node_zstate

Examples
check_node_quick_rf -node output -title quick_rf_check1 -rtime \
2ns -ftime 2ns
Sets up quick rise/fall time check with output signal with title name
quick_rf_check1, and rise time of 2ns and fall time of 2ns.
check_node_quick_rf –node output –title quick_rf_check1 \
-rtime 2ns -ftime 2ns -twindow 50ns 1000ns
Same as the previous example, but adds a start time of 50ns and stop time of
1000ns.
check_node_quick_rf –node dout* –title quick_rf_check1 \
-rtime 2ns -ftime 2ns -error_file xa_quick_rise_fall
Same as the first example, but adds a wildcard (*) to match multiple signals and
appends the output violation file to xa_quick_rise_fall.errt.
check_node_zstate
Checks for nodes in a high-impedance state.
Syntax
check_node_zstate -node node_name {node_name}
-title title_name [-ztime z_time]
[-twindow tstart [tstop] {tstart [tstop]}]
[-tstep tstep_value] [-fanout <0|1|2>]
[-except_node node_name {node_name}]
[-subckt subckt_name {subckt_name}]
[-except_subckt subckt_name {subckt_name}]
[-report port|all] [-error_file output_file_name]
[-numv value]

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check_node_zstate
-node node_name Specifies the node names at which the high-impedance

{node_name} state is checked. The node name can be a single node or
a node name with a wildcard character that represents a
group of node names. The rule of asterisk (*) character is
controlled by set_wildcard_rule.
-title title_name Specifies the title of the high-impedance check statement.

All high-impedance states reported by this statement are
printed under this title in the error report. This argument is
useful when there are multiple check statements specified
in a single run.
-ztime z_time Defines the period for which a node must remain in a high
impedance state to be reported as a high impedance
node. If not specified, the default is 5ns.
or END keyword.
-tstep tstep_value Performs the high-impedance state check at discrete time

points that are integer multiples of the specified
tstep_value. The first time point is the -tstart value
of the -twindow option.
-fanout <0|1|2> Selects the type of nodes for high-impedance checking:

■
A value of 0 enables all nodes.
■
A value of 1 enables nodes that have direct connection
to a transistor gate.
■ A value of 2 enables all nodes that have direct
connection to a transistor bulk.
If not specified, the default is 0.
-except_node Specifies the nodes to be excluded from high-impedance

node_name checking. This argument should be used only when –node
{node_name} node_name contains wildcard characters.
-subckt subckt_name Specifies the subcircuits to be checked. Wildcard

{subckt_name} characters are not allowed in subcircuit names.

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check_node_zstate
-except_subckt Specifies the subcircuits to be excluded from high-

subckt_name impedance checking. This argument should be used only
{subckt_name} when –node node_name contains wildcard characters.
-report port|all Specifies the type of reporting based on the subcircuit

ports. The default is all to report global nodes and
internal nodes. If you set it to port, all internal nodes are
excluded and all global nodes are reported based on the
subcircuit ports. If you specify this argument with |
-subckt, it limits the reporting to only the specified
subcircuits.
-error_file Specifies the file name to report high-impedance state.

output_file_name The file name is followed by .errz as the suffix. If not
specified, the default prefix follows the output file name
specified by –o command-line option.
-numv value Limits the number of violations to be reported for each

check_node_zstate command. It is applied locally.
The default is to report all the violations.
Description
This command enables the CustomSim tool to diagnose specified nodes
staying in a high-impedance (floating) state for a specific period of time. The
detected nodes are reported to an error file with suffix of .errz.
A node stays in a high-impedance state if there is no conducting path from any
voltage source to the node. A conducting path consists of conducting elements.
An element is conducting if that specific element meets the following criteria:
Device Rule
NMOS Vgs > Vth (rule=1) || Ids > idsth (rule=2) || Vg > VDD-0.1
(rule=3)
The default for idsth is 1e-8A. The default rule is 1 & 2.
PMOS Vgs < Vth (rule=1) || Ids > idsth (rule=2) || Vg < 0.1 (rule=3)
NPN Vbe > Vbeth

The default for vbeth is 0.64

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check_timing_edge
Device Rule
PNP Vbe < -Vbeth

The default for Vbeth is 0.64
Diode I(diode) > diode_ith || V(a,c) > diode_vth

The default for diode_ith is 1e-8A.
Resistor Always conducting by default.
Inductor Always conducting.
Capacitor Never conducting.
Verilog-A Never conducting.
Controlled sources Always conducting.
check_timing_edge
Performs an edge timing check.
Syntax
check_timing_edge -node node_name {node_name}
-title title_name -ref ref_name -min_time min_time
-max_time max_time [-window window_limit]
[-trigger trigger_type] [-loth logic_low_voltage]
[-data_edge_type edge_type] [-ref_edge_type edge_type]
[-rule 1|2]
-node node_name Defines a signal node name which can be the node name
{node_name} of a single node or a node name with the asterisk (*)
The wildcard is limited to one hierarchy only.

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check_timing_edge
-title title_name Defines the title name of this edge timing check. Errors
that occur during this check are listed in the .errt file.
The name of the edge timing error starts with this title
name. This name is useful when there are multiple edge
timing checks used for a single run.
-ref ref_name Defines the reference node name. ref_name must be a

single node name. A wildcard is not allowed.
-min_time min_time Defines the lower boundary of the timing edge difference
between the signal and reference nodes. A timing edge
error is reported when the timing edge difference is less
than min_time. The timing edge difference is calculated
only for the pair of permissible state transitions at the
signal node and the reference node.
-max_time max_time Defines the upper boundary of the timing edge difference
between the signal and reference nodes. A timing edge
error is reported when the timing edge difference is greater
than max_time. The timing edge difference is calculated
only for the pair of permissible state transitions at the
signal node and the reference node.
-window Eliminates a timing edge error report if the timing edge

window_limit difference exceeds window_limit.
-trigger Sets the trigger_type to one of the following keywords:

trigger_type ref specifies that the edge checking is executed only
when the reference edge occurs. Use this setting if the
signal changes before the reference edge.
input specifies that the edge checking is executed only
when the input signal edge (i.e., data edge) occurs. Use
this setting if the signal changes after the reference edge.
both specifies that the edge checking is executed when
either the reference edge or the input signal edge occurs.
This is the default setting. Note this setting tends to be
pessimistic and might report false edge timing errors. This
is because the simulator reports errors right away when it
detects and does not filter the errors with later events. Use
-window to remove the false errors.

H-2013.03
check_timing_edge
-hith Defines the logic high voltage for the signal. The default is
logic_high_voltage the same as the set_logic_threshold value.
or END keyword.

subcircuit_name subcircuit. When using the -subckt subcircuit_name
argument, node_name and ref_name are the node
names searched inside the subcircuit in which the node
name must not contain a wildcard character.
-error_file Specifies the output error file name for any edge timing
output_file_name violations. If the output file name is not specified, the
default output file use the output prefix name by –o follow
by .errt.
output_file_name with the .err extension.
-data_edge_type Specify one of the following keywords for edge_type:

edge_type ■
rise (default) to specify the rising edge of the target
node.
■
fall to specify the falling edge of the target node.
■
rf to specify both the rising and falling edge of the
target node.
■
x only has an effect when you specify -rule 2. When
you specify the x keyword with -rule 2, the
CustomSim tool only checks most the recent transition.
It does not matter if it is falling or rising edge. If you
specify rf with -rule 2, the CustomSim tool checks
the most recent of both the rising and falling edge.

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check_timing_edge
-ref_edge_type Specify one of the following keywords for edge_type:

edge_type ■
rise (default) to specify the rising edge of the
reference node.
■
fall to specify the falling edge of the reference node.
■ rf to specify both the rising and falling edge of the
reference node.
■
x only has an effect when you specify -rule 2. When
you specify the x keyword with -rule 2, the
CustomSim tool only checks most the recent transition.
It does not matter if it is falling or rising edge. If you
specify rf with -rule 2, the CustomSim tool checks
the most recent of both the rising and falling edge.
-rule 1|2 Selects the rule of edge timing checking. The default is 1,
which checks at every transition. When set to 2, it follows
the HSIM® behavior, which is to compare the edge time
difference between the most recent target signal transition
and reference signal transition only.
The qualified target-reference signal pair can vary
depending on their transition order. For example, if there is
a target signal transition, this check looks for the reference
signal transition, which happens prior to and also most
recently to this target signal transition. Similarly, if there is
a reference signal transition, this check looks for the target
signal transition, which happens prior to and also most
recently to this reference signal transition.
Description
When performing an edge timing check, if violations occur, they are stored in a
new CustomSim output file, output_file_name.err. The output file name is
the prefix name from the CustomSim –o command line argument. If –o is not
specified, it is the prefix of the input file name.
value can be modified by the set_logic_threshold command. If –loth and –

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check_timing_hold
Examples
check_timing_edge –node data -ref ctrl –ref_edge_type rise \
–title edge_check -min_time 2ns –max_time 5ns \
-error_file xa_edge
When node data has a state transition, such as at time t2, the time edge
difference t2-t1 must be within the range of 2ns for the -min_time and 5ns for
the -max_time. Otherwise, a timing edge error is reported to the output error
file xa_edge.errt with the title name edge_check. Time t1 is the most
recent rise state transition time at node ‘ctrl’ before time t2. When node ctrl
has a rise state transition at time t4, the time edge difference t4-t3 must be
within the range of 2ns and 5ns. Otherwise a timing edge error is also
reported. The time t3 is the most recent state transition time at node data
before time t4.
check_timing_edge –node data -ref ctrl –ref_edge_type rise \
–title edge_check -min_time 2ns –max_time 5ns -trigger input \
-window 10ns -error_file xa_edge
Same as the previous example, except the edge error is reported only when t1-
t2 is less than 2ns or is less than 10ns but greater than 5ns. The time t2 is the
most recent state transition time at node data before time t1.
check_timing_edge –node input* \
-ref ctrl –ref_edge_type rise –title edge_check -min_time \
0ns –max_time 8ns
This example checks if the input* edge changes occurs between 0ns and
8ns of the ctrl rising edge, when the reference signal ctrl rises or input*
changes. The error report to the default output_name.errt file with the title
edge_check.
check_timing_hold
Performs a hold timing check.
Syntax
check_timing_hold -node node_name {node_name}
-ref ref_name -hold_time hold_time -title title_name
[-window window_limit] [-hith logic_high_voltage]
[-loth logic_low_voltage]

H-2013.03
check_timing_hold

-ref ref_name Defines the reference node name and must be a single
node name. A wildcard is not allowed.
-hold_time Specifies the hold time. The signal should not change to
hold_time the specified edge to check for rising or falling conditions
(rising edge only, falling edge only, or both) between Tref
(the time the reference signal edge changes) -
hold_time until Tref if hold_time is positive. Note that
the -window window_limit argument is ignored for a
positive hold_time.
-window Specifies a hold time window for negative hold_time so

window_limit that any hold timing violation with a time difference (| Tref
- <signal change time> |) bigger than window_limitis
ignored.
or END keyword.

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check_timing_hold

-error_file Specifies the output error file name for any hold violations.
output_file_name If the output file name is not specified, the default output
file use the output prefix name by –o followed by .errt.

edge_type ■ rise (default) to specify the rising edge of the target
node.
■
■
target node.

edge_type ■
reference node.
■
reference node.
Description
When performing a hold check, if violations occur, they are stored in a new
CustomSim output file, output_file_name.errt. The output file name is the
prefix name from the XA –o command line argument. If –o is not specified, it is
the prefix of the input file name.

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Examples
check_timing_hold –node data -title hold_check -ref clk \
-hold_time 1.2ns -error_file RAM_timing.error
Specifies a hold timing check with clk as the reference node and “data” as the
data node. The title name is named hold_check and it uses the hold violation
time of 1.2ns. The command also specified the output error file to
RAM_timing.error, the actual output error file is
RAM_timing.error.errt.
check_timing_hold –node data -title \
hold_check - ref clk -hold_time 1.2ns -error_file \
RAM_timing.error
Specifies a hold timing check with clk as the reference node and data as the
data node. The title name is named hold_check and it uses the hold violation
time of 1.2ns. The command also specified the output error file to
RAM_timing.error, the actual output error file is
RAM_timing.error.errt.
Performs a pulse width timing check.
Syntax
check_timing_pulse_width -node node_name {node_name}
-title title_name -low_min_time low_min_time
-low_max_time low_max_time -high_min_time
high_min_time -high_max_time high_max_time
[-loth logic_low_voltage] [-hith logic_high_voltage]

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-title title_name Defines the title name of this pulse width timing check.
file. The name of the pulse width timing error starts with
this title name. This name is useful when there are multiple
pulse width timing checks used for a single run.
-low_min_time Defines the minimum value of the low-state pulse. Each

low_min_time low state pulse (the time period the node stays at the logic
0 state) is required to be greater than low_min_time and
less than low_max_time
. The minimum length of the low pulse is ignored (not
checked) if low_min_time is negative.
-low_max_time Defines the maximum value of the low-state pulse. Each

low_max_time low state pulse (the time period the node stays at the logic
0 state) is required to be greater than low_min_time and
less than low_max_time. The maximum length of the low
pulse is ignored (not checked) if is negative.
-high_min_time Defines the minimum value of the high-state pulse. Each

high_min_time high state pulse (the time period the node stays at the logic
0 state) is required to be greater than and less than
high_max_time. The minimum length of the low pulse is
ignored (not checked) if high_min_time is negative.
-high_max_time Defines the maximum value of the high-state pulse. Each

high_max_time high state pulse (the time period the node stays at the logic
0 state) is required to be greater than high_min_time
and less than high_max_time. The maximum length of
the low pulse is ignored (not checked) if high_min_time
is negative.

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or END keyword.

specify the subcircuit_name.
default output file use the output prefix name by –o follow
by .errt.
output_file_name with the .err extension.
Description
When performing an pulse width timing check, if violations occur, they are
stored in a new CustomSim output file, output_file_name.err. The output
not specified, it is the prefix of the input file name.
Examples
check_timing_pulse_width –node out –title pulse_width_check \
-low_min_time 4ns –low_max_time 8ns -high_min_time 5ns \
–high_max_time 9ns
A pulse width violation error, following the title name of pulse_width_check

is reported when the low pulse width at node out is less than 4ns or greater
than 8ns; or when the high pulse width is less than 5ns or greater than 9ns.
The default logic threshold value is used because –loth/-hith is not defined.

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check_timing_setup

–high_max_time 9ns -subckt digital_ram
Same example as the first example, but the signal ‘out’ applied to only node
inside the subcircuit digital_ram.
–high_max_time 9ns\ -error_file xa_pulse_width
Same the first example, but output error file is append to

xa_pulse_width.errt.
check_timing_setup
Performs a setup timing check.
Syntax
check_timing_setup -node node_name {node_name}
-ref ref_name -setup_time setup_time -title title_name
[-window window_limit] [-loth logic_low_voltage]
-ref ref_name Defines the reference node name and must be a single
node name. A wildcard is not allowed.

H-2013.03
check_timing_setup
-setup_time Specifies the setup time. The signal should not change to
setup_time the specified edge to check for rising or falling conditions
(rising edge only, falling edge only, or both) between Tref
(the time the reference signal edge changes) -
setup_time until Tref if setup_time is positive. Note
that the -window window_limit argument is ignored
for a positive setup_time.
-window Specifies a setup time window for negative setup_time

window_limit so that any setup timing violation with a time difference (|
Tref - <signal change time> |) bigger than window_limit
is ignored.
or END keyword.

default output file use the output prefix name by –o
followed by .errt.

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check_timing_setup

edge_type ■
rise (default) to specify the rising edge of the target
node.
■
target node.

edge_type ■
reference node.
■
■
reference node.
Description
When performing a setup check, if violations occur, they are stored in a new
CustomSim output file, output_file_name.err. The output file name is the
prefix name from the XA –o command line argument. If –o is not specified, it is
the prefix of the input file name.
Examples
check_timing_setup -node data –ref clk -title setup_check \
-setup_time 1.2ns
Specifies a setup timing check with clk as the reference node and data as the
data node. The title name is named setup_check and it uses the setup
violation time of 1.2ns.
check_timing_setup -node data -data_edge_type fall -title \
setup_check1 -ref clk -ref_edge_type fall -setup_time 1.2ns
Specifies a setup timing check with clk as the reference node and data as the
data node. Both the clk and data use the fall edge. The title name is
setup_check1 and it uses the setup violation time of 1.2ns.

H-2013.03
Enables .print statements in HSPICE® and Eldo™ netlists.
Syntax
enable_print_statement -switch enable_value
Arguments
See the Common Syntax Definitions section for details about the
enable_value argument.
Description
By default, the CustomSim tool treats all .print statements as if they were
.probe statements. Use the enable_print_statement command to
enable the ASCII output. The simulator generates a .print file containing the
output from the .print statements.
Examples
enable_print_statement yes
See Also
set_waveform_option
force_node_voltage
Forces the specified nodes to stay at the specified constant voltage.
Syntax
force_node_voltage -node node_name {node_name}
-voltage voltage_value [-time time_value]
[-subckt subckt_name] [-slope t_value]
-node node_name Specifies the node names to force.

{node_name}
-voltage Specifies the voltage value to set.

voltage_value

H-2013.03
keep_top_element
-time Specifies the time to force the nodes. The default is 0.

time_value
-subckt Forces only the nodes inside the specified subcircuit.

subckt_name
-slope t_value Forces the voltage with a ramp of t_value (in seconds
per volt). The default is 10p s/V. Note that this option is
only applicable to set_multi_rate_option -mode
2.
Description
force_node_voltage forces the specified nodes to stay at the specified
constant voltage. The node voltage stays at the same value from the specified
time until either the end of simulation or when the constant node voltage status
is released by release_node_voltage.
Examples
force_node_voltage vpump -voltage 2.5 -time 10ns
The vpump node is forced at 2.5V at 10 ns. This node remains at this value
until the end of the simulation unless you use release_node_voltage for the
same node.
keep_top_element
Specifies the top-level instance to be simulated with respect to the other
elements in the netlist.
Syntax
keep_top_element -inst instance_name

H-2013.03
load_ba_file
-inst Suppose the CustomSim tool uses a netlist, instances,

instance_name and subcircuits with keep_top_element in the
following sequence:
netlist A_nlist
(instance A)
(instance B)
subckt (SA)
subckt (SB)
With the command line:
xa A_nlist -top SB -c cfg.xa
And cfg.xa contains:
keep_top_element -inst A
When you run the CustomSim tool, the top-level netlist
has the A instance and all instances of the SB subcircuit.
Description
This command works with the -top XA command line option to specify the
instances and subcircuits in the top-level netlist. Except for the stimulus and
voltage source elements, all of the elements in the original top-level netlist are
ignored.
load_ba_file
Specifies a post-layout back-annotation file.
Syntax
load_ba_file -file filename [-skipnet net_name
{net_name}] [-min_res min_res_value]
[-min_cap min_cap_value] [-rcnet net_name {net_name}]
[-cnet net_name {net_name}] [-ccnet net_name {net_name}]
[-dpf switch_value]
[-ccap_to_gcap cap_value]
[-add_netpin DSPF_netname DSPF_node {DSPF_node}]
[-add_netpin_file netpin_file_name]
[-delete_netpin DSPF_netname DSPF_node {DSPF_node}]
[-delete_netpin_file netpin_file_name]

H-2013.03
load_ba_file
[-report_no_ba value]
[-add_instpin_file file_name] [-min_res value]
[-max_res value][-min_cap value] [-min_ind value]
-file filename Specifies the name of the parasitic netlist file (SPEF or
SPF format). It can be a gzipped file to save the disk
space. Star-RC™ can directly generate gzipped files.
See the NETLIST_COMPRESS_COMMAND command in
the Star-RC Command Reference.
-skipnet net_name Specifies the name of nets that should not be back-
{net_name} annotated. You can specify multiple net names. You
can use wildcard characters in the net names.
-min_res res_value Specifies the minimum resistor value to keep.

Resistors with values less than res_value are
shorted. The default value is 0.01 ohm.
-min_cap min_cap_value Specifies the minimum capacitor value to keep.

Capacitors with values less than min_cap_res are
ignored. The default value is 1e-02*CSHUNT value.
-rcnet net_name Specifies the nets to use for full RC back-annotation.

{net_name} All other nets not specified by this argument only use
lumped capacitance back-annotation. The lumped
capacitance value uses the net capacitance value in
the *|NET line.
This argument works in both SPF and SPEF formats
and accepts wildcard characters.
-cnet net_name Specifies for the nets to use lumped capacitance

{net_name} back-annotation. The lumped capacitance value uses
the net capacitance value in the *|NET line. All the nets
not specified by this argument use full RC back-
annotation (assuming the net itself contains RCs).
Also, you cannot use this argument with the -
lump_c_only argument of the set_ba_option
command.

H-2013.03
load_ba_file
-ccnet net_name Specifies for the nets to use Cg+Cc back-annotation

{net_name} (remove all resistors from a given net). All the nets not
specified by this argument use full RC back-
annotation (assuming the net itself contains RCs).
Also, you cannot use this argument with the
-lump_c_only argument of the set_ba_option
command.
-dpf switch_value Specifies to back-annotate the DPF section. The

default switch_value is 1.
-ccap_to_gcap Converts all the coupling capacitors to ground

cap_value capacitors if the value of the coupling cap is below the
cap_value. If the back-annotation file contains no
coupling capacitors, there is no impact.
This option works for both SPF and SPEF format. The
default is 1e-19.
-add_netpin Adds a new net pin. The first value is a DSPF net
DSPF_netname name, followed by one or more DSPF node names.
DSPF_node {DSPF_node} The DSPF node name can be a sub-node, instance
pin, or probe text node. You can specify multiple
-add_netpin options.
-add_netpin_file Specifies a user-defined file to add with two columns.

netpin_file_name The first column is a DSPF net name. The second
column is a DSPF node name, with one DSPF net
name - DSPF node name pair per line.
The DSPF node name can be a sub-node, instance
pin, or probe text node. You can specify only one
-add_netpin_file option. Empty lines are
supported. Lines start with '*' are ignored.
-delete_netpin Deletes a net pin. The first value is a DSPF net name,
DSPF_netname followed by one or more DSPF node names. The
DSPF_node {DSPF_node} DSPF node name can be a sub-node, instance pin, or
probe text node. You can specify multiple
-delete_netpin options.

H-2013.03
load_ba_file
-delete_netpin_file Specifies a user-defined file to delete with two

netpin_file_name columns. The first column is a DSPF net name. The
second column is a DSPF node name, with one DSPF
net name - DSPF node name pair per line.
The DSPF node name can be a sub-node, instance
pin, or probe text node. You can specify only one
-add_netpin_file option. Empty lines are
supported. Lines start with '*' are ignored.
-report_no_ba value Specify one of the following values:

■
0 does not report missing SPF nets or instances
(default).
■ 1 reports instance names that contain missing SPF
nets.
■ 2 reports any missing SPF nets.
-add_instpin_file Specifies a user-defined file with four columns per line.

file_name Each line defines the connection between the DSPF
net to the pre-layout device pin name in the following
column format:
DSPF_netname DSPF_nodename
Prelayout_instance_name Prelayout_port_name
1. DSPF_netname is the net name from the DSPF
file. For example: *|NET vdd … where vdd is a
DSPF net name.
2. DSPF_nodename can be a net pin, instance pin,
or sub-node.
3. Prelayout_instance_name is a pre-layout instance/
device name.
4. Prelayout_port_name is a pre-layout port name for
the instance/device
You can specify only one file name. Only the top-level
DSPF is supported.
-min_res value Specifies the lower threshold of resistors from the

specified back-annotation file to be kept. It overrides
the value specified by set_ba_option for the back-
annotation file. All resistors with an absolute value
below the specified value are shorted by
set_resistor_option -rule=1. The default is
0.01.

H-2013.03
load_ba_file
-max_res value Specifies the upper threshold of resistors from the

annotation file. All resistors with an absolute value
above the specified value are treated as open-circuit
by set_resistor_option rule=1. The default is
1e12.
-min_cap value Specifies the lower threshold of capacitors from the

annotation file. All capacitors with an absolute value
below the specified value are treated as open-circuit
by set_capacitor_option rule=1. The default
is 1e-2*CSHUNT. The default of CSHUNT is 1e-20.
-min_ind value Specifies the upper threshold of inductors from the

annotation file. All inductors above the specified value
are shorted by set_inductor_option rule=1.
The default is 0.
Description
Specifies a parasitic back-annotation file. multiple files can be specified using
this command multiple times. You can use a mixture of spf and spef formats.
Examples
In the command script file:
load_ba_file -file Parastic_net.spf
In an HSPICE or Eldo netlist:

.opt Xa_cmd="Load_ba_file -file Parastic_net.spf -skipnet X1.in*"
In a Spectre netlist:
Baoptions Options Xa_cmd="Load_ba_file -file Parastic_net.spf -
skipnet X1.in*"
See Also
map_ba_terminal, check_node_excess_rf

H-2013.03
Determines how the CustomSim tool handles a file containing initial conditions.
Syntax
load_operating_point [-file filename {filename}]
[-node_type node_type] [-type ic_type]
[-subckt subckt {subckt}] [-inst inst {inst}]
-file filename Specifies the name of the file to load.

{filename}
-node_type node_type Limits the application of initial conditions to nodes

detected as node_type. A list of arguments is
supported. Currently only the latch node_type is
supported to limit the application of initial conditions to
detected latches.
-type ic_type Specifies the type of initial condition to be applied. The

ic_type can be ic or nodeset. This option
overrides what is specified in the file.
-subckt subckt Limits the application of initial conditions to nodes of

{subckt} the instances of subckt. A list of arguments is
supported. Wildcards are not supported.
-inst inst {inst} Limits the application of initial conditions to the

specified instances. Wildcards are supported.
Examples
load_operating_point -file op-file -node_type latch -type nodeset
Reads initial conditions from the op-file file and applies them as nodeset to
latch nodes only.
load_operating_point -file op-file -inst xtop.analog
Reads initial conditions from the op-file file and applies them nodes in the
xtop.analog instance only, as defined in the file (.ic or .nodeset).
load_operating_point -file op-file -subckt latch_clr -node_type
latch

H-2013.03
load_parameter_file
Reads initial conditions from the op-file file and applies them only to latch
nodes and to nodes in instances of the latch_clr subcircuit, as defined in
the file (.ic or .nodeset).
load_parameter_file
Lets you override instance parameter values in the netlist.
Syntax
load_parameter_file -file filename
-file filename Specifies the name of the file that contains the instance
parameter information.
Description
This command lets you specify a file that contains instance parameter values
that override the corresponding definitions in the netlist. All other instance
parameters keep their original values.
You can specify multiple lines in the file and use # to denote a comment. The
file format for each line is:
instance_name.parameter_name value
You can use load_parameter_file in a .alter statement.

Examples
load_parameter_file -file param.txt
The param.txt file contains:

x1.m1.dtemp -25
x1.m2.dtemp 0
x2.m1.dtemp 125
x2.m2.dtemp 25
In the previous example the dtemp parameter value overwrites the values for
the x1.m1, x1.m2, x2.m1, and x2.m2 instances. The new dtemp value is -25
for the x1.m1 instance, 0 for the x1.m2 instance, 125 for the x2.m1 instance
and 25 for the x2.m2 instance. All other occurrences of dtemp keep their
original values defined in the netlist.

H-2013.03
load_vector_file
load_vector_file
Loads an HSPICE vector stimulus file or a VCD stimulus file. When VCD is the
stimulus file format, the -ctl flag must be used to name the VCD control file.
Syntax
load_vector_file -file filename
[-format format_specification]
Argument-- format_specification Description
VEC | vec Specifies HSPICE vector file format.
VCD -ctl filename | vcd -ctl Specifies a value change dump file format.
filename The -ctl flag and filename are required.
EVCD [-ctl filename] | evcd You can also specify an extended value
[-ctl filename] change dump file format, as well as signal
control file. If you do not specify the signal
control file, the CustomSim tool follows the
EVCD port direction rule and the unknown
direction is ignored.
Examples
Example 5
#load HSPICE vector stimulus
load_vector_file -file input.vec -format VEC
Example 6
#load VCD stimulus
load_vector_file -file stimulus.vcd -format VCD -ctl mapfile
load_verilog_file
Loads a structural Verilog netlist. The CustomSim tool uses the connectivity
from Verilog netlist but does not support Verilog functions.
Syntax
load_verilog_file -file filename

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map_ba_terminal
-file filename Specifies the name of the structural Verilog

netlist file.
Examples
#load a structural Verilog netlist
load_verilog_file -file top.v
#load multiple structural Verilog netlists

load_verilog_file -file inv.v
load_verilog_file -file ring_oscilator.v
map_ba_terminal
Specifies the terminal name mapping between the back-annotation file and the
terminal names recognized by the simulator.
Syntax
map_ba_terminal -name ba_file_term_name
[-alias] valid_terminal_name [-subckt subcircuit_name]
Arguments
The ba_file_term_name, valid_terminal_name, and
subcircuit_name arguments are user-defined.
Description
The CustomSim tool uses the first character, and optional subsequent
characters, to determine which terminal is represented. Table 4 shows the
terminal identification characters.

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map_ba_terminal
If the instance terminals in the back-annotation file contains names that are not
recognized based upon the characters shown in Table 4, the
map_ba_terminal command must be used.
Table 4 map_ba_terminal identification characters
Terminal M (MOS) Q (BJT) R, C, D (Resistor, Capacitor,

Index Diode)
1 D[R][A][I][N] C[O][L][L][E][C][ A[N][O][D][E],

T][O][R] P[L][U][S],
P[O][S][I][T][I][V]
[E]
2 G[A][T][E] B[A][S][E] B,
C[A][T][H][O][D][E],
M[I][N][U][S],
N[E][G][A][T][I][V]
[E]
3 S[O][U][R][C][ E[M][I][T][T][E][ S[U][B][S][T][R][A]

E] R] [T][E]
4 B[U][L][K] S[U][B][S][T][R][ N/A

A] [T][E]
Examples
In Example 7, UDRN is used for the drain connection in the back-annotation file.
The CustomSim tool does not recognize UDRN, so the following command
must be used to back-annotate correctly:
map_ba_terminal -name UDRN -alias D

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meas_post
Example 7 map_ba_terminal back-annotation file sample

*|NET Xarr1/Xarr<11>/XI1/mc_n5 0.000826547PF
*|I (Xarr1/Xarr<11>/XI1/MM8:UDRN Xarr1/Xarr<11>/XI1/MM8 UDRN B 0 33.06
40.34)
*|I (Xarr1/Xarr<11>/XI1/MM5:SRC Xarr1/Xarr<11>/XI1/MM5 SRC B 0 32.85
40.815)
*|I (Xarr1/Xarr<11>/XI1/MM4:SRC Xarr1/Xarr<11>/XI1/MM4 SRC B 0 32.67
39.51)
*|I (Xarr1/Xarr<11>/XI1/MM3:UDRN Xarr1/Xarr<11>/XI1/MM3 UDRN B 0 32.95
39.035)
Cg39 Xarr1/Xarr<11>/XI1/MM8:UDRN 0 8.26142e-17
Cg40 Xarr1/Xarr<11>/XI1/MM5:SRC 0 1.2562e-17
Cg41 Xarr1/Xarr<11>/XI1/MM4:SRC 0 1.40334e-16
Cg42 Xarr1/Xarr<11>/XI1/MM3:UDRN 0 6.31581e-18
R51 Xarr1/Xarr<11>/XI1/MM8:UDRN Xarr1/Xarr<11>/XI1/MM5:SRC 10.3526
R52 Xarr1/Xarr<11>/XI1/MM8:UDRN Xarr1/Xarr<11>/XI1/MM4:SRC 31.6749
R53 Xarr1/Xarr<11>/XI1/MM4:SRC Xarr1/Xarr<11>/XI1/MM3:UDRN 3.52783
See Also
load_ba_file, check_node_excess_rf
meas_post
Performs measurements using existing simulation results.
Syntax
meas_post -waveform file_name
-waveform You must specify an existing waveform file in fsdb or wdf

file_name format. Split waveforms are not supported.
Description
When you use meas_post in a command script file or with .option xa_cmd,
the CustomSim tool:
■
Only reads in the .measure commands with the related parameters in the
netlist (when the .measure commands uses parameters).
■
Performs the measurement specified in the netlist using the data in the
specified waveform file.

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You can use only one meas_post in a simulation. If you specify more than one
command, the CustomSim tool uses the last one and ignores the previous one.
the CustomSim tool issues a warning in the log file to point out which
meas_post command was used and which ones were ignored.
When you run the CustomSim tool with meas_post, use the -o command line
option to redirect the new output data. This option avoids overwriting the
simulation log file.
You can use meas_post with a SPICE netlist that only includes .measure
commands. This convention does not support wildcard characters.
Examples
Suppose a previous CustomSim simulation generated the following files:
top.fsdb and top.log. To perform a measurement for the simulation
results, do the following steps:
1. Use a measurement command from a previous simulation or add a new one.
For example:
.meas tran delay trig v(clk) val=1.5 rise=1 targ v(d[1])
val=1.5 rise=1
2. Add the following command in the existing command script file, for example:
meas_post -waveform top.fsdb
3. Run the CustomSim tool:
xa original_netlist -c config -o measNewResults
Two new files are created: measNewResults.log and
measNewResults.meas.
Creates current waveform output.
Syntax
probe_waveform_current -i | i1 instance_name {instance_name}
[-in instance_name {instance_name}]
[-iall instance_name {instance_name}]
[-isub | -x subckt_name.port {subckt_name.port}]
[-subckt subckt_name] [-limit level]
[-except_inst instance_name {instance_name}]
[-filetag file_tag]

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-i1 or -i instance_name Specifies the name of the instance at which the

{instance_name} current through instance terminal 1 is probed.
-in instance_name Specifies the name of the instance at which the

current of terminal n is probed, where n is a positive
integer. Note this argument applies only to instances
not specified by -subckt.
-iall instance_name Specifies the name of the instance at which the

current of all terminals are probed. Note this
argument applies only to instances not specified by
-subckt.
-isub | -x -isub or -x probe returns the total current flowing

subckt_name.port into the subcircuit port. The subckt_instance is a
{subckt_name.port} subcircuit instance name, and port is a name of the
subcircuit port. Positive values indicate the current is
flowing into the subcircuit port. Negative values
indicate the current is flowing out of the subcircuit
port.
Note that -x is not supported in Eldo netlist syntax.
-subckt subckt_name Specifies the subcircuit of the instances at which the

current is probed.
-limit level Specifies the hierarchical level down to which the

current is probed. When -subckt is specified, the
-limit level is relative to where the particular
instance is located in the hierarchy. A value of 0 is the
top level of the subcircuit. The default for level is 3.
-except_inst Specifies the instances to exclude from probing.

instance_name
{instance_name}
-filetag file_tag Specifies a file tag to direct the signals probed with
this command to a separate waveform file. The
waveform file has the standard name with .filetag
inserted before the normal file suffix, for example,
xa.filetag.wdf.

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Description
Probes the current through an instance pin. The current waveform is written to
the output file in the format specified by the post option in the netlist.
The CustomSim tool-supported wildcard characters ( * ) can be used in the
instance_name identifiers. The wildcard character can be used to match one
level—or all levels—of the hierarchy. See the set_wildcard_rule command.
Note: The probe_waveform_current command cannot be used to

probe subcircuit terminal currents.
Probes specified by this command are in addition to the .probe statement in

the HSPICE or ELDO netlist files or save statements in the Spectre netlist files.
Long simulations, or simulations in which some nodes have a high level of
activity, can produce very large waveform files. To minimize waveform file
loading time in these files, you can direct signals to separate waveform files
and keep file sizes smaller.
To direct signals to a separate waveform file, use the -filetag argument. All
of the signals probed by that instance of the command are directed to a
separate waveform file. The file name has the same format as the standard
waveform file name, except for the suffix; for example, xa.mytag.wdf. All of
the settings made by set_waveform_option also apply to the tagged output
files. A signal can be directed to multiple files if it is probed with another
command that specifies a different file_tag. Additionally, multiple
probe_waveform_current commands can use the same file tag. The
other probing commands (voltages and logic) can also use the same file tag.
Examples
probe_waveform_current -i vdd vss vda
probe_waveform_current -iall X1.X2.M37

probe_waveform_current * -except_inst *clk
The last example probes all instances down to the default level of hierarchy (3),
except those finishing with the clk pattern.
probe_waveform_current mrxdrv -subckt rxblock -filetag rx_block
The previous example probes the i1 current in mrxdrv in all instances of

rxblock and diverts them to the rx_block waveform file. If the CustomSim
tool is run as xa net.sp -o xa -wavefmt wdf, the waveform file is
named xa.rx_block.wdf.

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See Also
probe_waveform_logic, probe_waveform_va, probe_waveform_voltage,
set_wildcard_rule
Generates logic values of specified nodes in the output waveform file.
Syntax
probe_waveform_logic -node node {node}
[-nN inst_name {inst_name}] [-nall inst_name {inst_name}]
[-loth low_threshold] [-hith high_threshold]
[-subckt subckt_name {subckt_name}] [-limit level]
[-except_node node_name {node_name}]
[-port enable_value] [-filetag file_tag]
-node node Specifies the nodes to be printed as a logical signal.

{node}
-nN inst_name Specifies the name of the instance. The Nth terminal is
{inst_name} probed as a logic signal, where N is a positive integer. Note
that this option cannot probe subcircuit instance terminals.
-nall Specifies the name of the instance in which all terminals are
inst_name probed as a logic signal. Note that this option cannot probe
{inst_name} subcircuit instance terminals.
-loth Specifies the threshold voltage for the LOW logic state, 0.
low_threshold
-hith Specifies the threshold voltage for the HIGH logic state, 1.
high_threshold
-subckt Probes the nodes of the specified subcircuits as logic

subckt_name signals.
{subckt_name}

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-limit level Specifies the hierarchy level down to which the logic values
of the specified node are probed. This option is useful for
limiting output when you use the * wildcard character. The
top level of the netlist is 0. The default level is 3.
-except_node Specifies the nodes to exclude from probing.

node_name
{node_name}
-port If you specify an enable_value value of 1, a wildcard

enable_value character matches the subcircuit port names.
-filetag Specify a file tag to direct the signals probed with this
file_tag command to a separate waveform file. The waveform file
has the standard name with .filetag inserted before the
normal file suffix, for example, xa.filetag.wdf.
Description
The default settings for -loth and -hith are derived from
set_logic_threshold. By default, -loth is set to 30% of the low voltage, and
-hith is set to 70% of the high voltage. The CustomSim tool uses a search
algorithm to determine the high/low voltage for a given node if there are
multiple supply domains:
■ If only -loth is specified, a voltage <= the low_threshold signal is 0,
else 1.
■
If only -hith is specified, a voltage >= the high_threshold signal is 1,
else 0.
■
If -loth and -hith are both specified:
• If -loth >= -hith, error out.
• If voltage < low_threshold, the signal is 0.
• If voltage >= high_threshold, the signal is 1.
• If low_threshold < voltage < high_threshold, the signal is U
(unknown).
Different signals can use different logic thresholds; but for a single signal, there
can be only one logic threshold, even if the signal is being probed to several file
tags as specified by the -filetag option.

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probe_waveform_va
Note: You can only apply the -nN and -nall arguments to primitive
instances.
Examples
probe_waveform_logic -node data -loth 0.6
This example prints the logic state of the data node in the waveform file. If
data has a voltage of <=0.6V, the logic state is 0; otherwise, the logic state is
1.
See Also
probe_waveform_current, probe_waveform_va, probe_waveform_voltage,
set_wildcard_rule
probe_waveform_va
Probes the values of Verilog-A variables or parameters and writes them to the
plot file.
Syntax
probe_waveform_va -var variable_name {variable_name}
variable_name Specifies the hierarchical path to the Verilog-A variable.

{variable_name}
-subckt subckt_name Specifies to probe the variables in all instances of the

specified subcircuit. If you specify -subckt the
var_name is local to the subcircuit.
-limit level Controls the depth of wildcard matching. The default is 3.

If you specify -subckt the level is relative to the top
level of the subcircuit/module.
Description
Note that probe_waveform_va:

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■
Probes the value of Verilog-A variables or parameters and writes them to the
plot file. It does not probe Verilog-A ports or electrical nodes. Use the
probe_waveform_voltage command to probe electrical signals.
■
Scopes only to Verilog-A instances/modules. It does not print SPICE MOS
model parameters.
The output to the waveform file is the hierarchical path and the variable name.
There are no signal access functions such as v() or i() for the voltage and
current signals. The separator between the hierarchical path and the variable
name is the hierarchical separator for the simulation as defined by the
set_sim_hierid command or the .hier command (Eldo format only).
variable_name identifier. The wildcard character can be used to match one
level, or all levels, of the hierarchy. See the set_wildcard_rule command.
Examples
probe_waveform_va -var x1.count
Probes the variable count in the x1 module. The variable appears in the
waveform file as x1.count.
probe_waveform_va -var x1.count
Probes the variable count in the x1 module. The variable appears in the
waveform file as x1:count.
probe_waveform_va -var x1.*
Probes all variables and parameters in the x1 module.

probe_waveform_va * -subckt mymodule
Probes all variables and parameters in all instances of mymodule.

See Also
probe_waveform_current, probe_waveform_logic,
probe_waveform_voltage, set_wildcard_rule
Creates a voltage waveform output.

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Syntax
probe_waveform_voltage -v node_name {node_name}
[-vn instance_name {instance_name}]
[-vall instance_name {instance_name}]
[-vsub subckt_name.port {subckt_name.port}]
[-subckt subckt_name] [-limit limit_val]
[-level level_val] [-except_node node_name {node_name}]
[-port enable_value] [-ba_net net_name {net_name}]
[-filetag file_tag]
-v node_name{ Specifies the node name at which the voltage is

node_name} probed.
-vn instance_name Specifies the name of the instance at which the

voltage of terminal n is probed, where n is a positive
integer.
-vall instance_name Specifies the name of the instance at which the

voltage of all terminals are probed.
-vsub subckt_name.port Probes the ports of the subcircuit using local port
{subckt_name.port} names. You can use wildcard characters. This probe
matches ports identically to an isub probe, except that
it reports voltage instead of current.
-subckt subckt_name Probes the nodes in all instances of the named

subcircuit. If you specify this argument, the nodes or
instances should be in the subcircuit instance
hierarchy level.
-limit limit_val Specifies the hierarchy level down to which the

voltage is probed. When -subckt is specified, the -
limit level is relative to where the particular node
is located in the hierarchy. A value of 0 specifies the
top level of the subcircuit. The default for level is 3.
-level level_val Specifies the relative hierarchical level down to which

voltages are probed when wildcards are used.
Numbering starts with 1 at the hierarchical level
where the first wildcard appears.

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-except_node node_name Specifies the nodes to exclude from probing.

{node_name}
-port enable_value If you specify an enable_value value of 1, a wildcard

character matches the subcircuit port names.
-ba_net net_name Probes the voltage waveforms for the SPF/SPEF pin
{net_name} names. You can specify a wildcard character in a net
name. Note that this argument only works in back-
annotation and is not applicable to the -subckt and
-limit arguments.
-filetag file_tag Specify a file tag to direct the signals probed with this
command to a separate waveform file. The waveform
file has the standard name with .filetag inserted
before the normal file suffix, for example,
xa.filetag.wdf.
Description
Probes the voltage on a node or on the pin of a primitive instance. The voltage
waveform is written to the output file in the format specified by the post option
in the netlist.
node_name and instance_name identifiers. The wildcard character can be
used to match one level—or all levels—of the hierarchy. See the
set_wildcard_rule command.
Long simulations, or simulations in which some nodes have a high level of
To direct signals to a separate waveform file, use the -filetag argument. All
of the signals probed by that instance of the command are directed to a
separate waveform file. The file name has the same format as the standard
waveform file name, except for the suffix; for example, xa.mytag.wdf. All of
the settings made by set_waveform_option also apply to the tagged output
files. A signal can be directed to multiple files if it is probed with another
command that specifies a different file_tag. Additionally, multiple

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probe_waveform_voltage commands can use the same file tag. The

other probing commands (voltage and logic) can also use the same file tag.
Examples
Example 8
probe_waveform_voltage *
Example 8 probes all voltage nodes down to the default level of hierarchy,
which is 3.
Example 9
probe_waveform_voltage *.* -limit 4
Example 9 probes all voltage nodes from hierarchy level 0 to level 4.
Example 10
probe_waveform_voltage *.* -limit 0
Example 10 does not probe the voltage of any node. The asterisk characters
*.* refer to all of the nodes at the first level and below, but the -limit 0
argument limits the nodes (to be probed) to only the top level. The arguments
are, therefore, contradictory.
Example 11
probe_waveform_voltage * -except_node *clk
Example 11 probes all nodes down to the second level of hierarchy, except
those finishing with clk pattern.
Example 12
probe_waveform_voltage -ba_net clk*
Example 12 probes the voltage waveform from the SPF/SPEF instance pins for
any net name that matches clk.
Example 13
probe_waveform_voltage ctrl sig* -subckt mysub -limit 2
Example 13 specifies to probe the ctrl signal and all signals that begin with
sig in all occurrences of the mysub subcircuit. The -limit 2 option is
relative to the top level of the subcircuit and limits the depth of the wildcard
probe. Example 13 is equivalent to the following SPICE definition:

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.subckt mysub
.probe v(ctrl)
.probe v(sig*) level=2
...
ends
Example 14
probe_waveform_voltage rx_data -subckt rxblock -filetag rx_block
Example 14 probes the signal rx_data in all instances of rxblock and

diverts them to the rx_block waveform file. If the CustomSim tool is invoked
as xa net.sp -o xa -wavefmt wdf, the waveform file is named
xa.rx_block.wdf.
The following examples use this sample circuit:
Example 15
.subckt topsub t1 t2
X1 t1 t2 downsub
…
.ends
.subckt downsub d1 d2
…
.ends
X0 a b topsub
X01 c d topsub
probe_waveform_voltage -vsub x0.* -limit 1
Probes all of the ports in xtopsub and any subcircuits contained in topsub
down to the limit of 1. The following probes are in the waveform file: v(x0.t1),
v(x0.t2).
probe_waveform_voltgae -vsub x0.*
Probes all of the ports in x0 and any subcircuits contained in x0 down to the
limit of 1. The following probes are in the waveform file: v(x0.t1), v(x0.t2),
v(x0.x1.d1), and v(x0.x1.d2).
You can combine the vsub probe with the -subckt option. The vsub
instance.port becomes local to the subcircuit definition:
probe_waveform_voltage -vsub * -subckt topsub
This command probes all subcircuit ports in all instances of the named
subcircuit as well as the ports of any subcircuit instance in topsub down the
default limit of 3. This example probes: v(x0.t1), v(x0.t2), v(x0.x1.d1),
v(x0.x1.d2), v(x01.t1), v(x01.t2), v(x01.x1.d1), and v(x01.x1.d2).

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pulse_oscillator
To probe only the ports of the named subcircuit use -limit 0 to prevent
matching any deeper into the hierarchy:
probe_waveform_voltage -vsub * -subckt topsub -limit 0
This command probes all subcircuit ports in all instances of the named
subcircuit, topsub: v(x0.t1), v(x0.t2), and v(x01.t1), v(x01.t2).
probe_waveform_voltage -vsub * -subckt downsub -limit 0
Probes only the port voltages of all instances of the downsub subcircuit. The
following probes are in the waveform file: v(x0.x1.d1), v(x0.x1.d2),
v(x01.x1.d1), and v(x01.x1.d2).
When you use wildcard matching except patterns can be used to exclude some
nodes:
probe_waveform_voltage -vsub * -subckt downsub -limit 0 -
except_node x0.*
This command probe only the ports of all instances of the downsub subcircuit,
but excludes any instance of downsub in x0. The following probes are added
to the waveform file: v(x01.x1.d1), v(x01.x1.d2).
See Also
probe_waveform_current, probe_waveform_logic, probe_waveform_va,
set_wildcard_rule
pulse_oscillator
Applies a current kick to a specified node.
Syntax
pulse_oscillator -node node_name {node_name}
-pw pulse_width -time value [value ...]
[-amp amp_value] [-rt rt_value]
-node node_name Defines the node at which the current source is connected.
{node_name}
-pw pulse_width Specifies the duration of the current pulse.

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-time value Specifies the time at which the current pulse starts. You can
specify multiple pulses by listing multiple times.
-amp amp_value Specifies the amplitude of the current pulse.
-rt rt_value Specifies the rise and fall time of the current pulse.
Description
A current pulse with a pulse width of half the expected oscillation period is
usually sufficient to start oscillations, but sometimes you need to experiment
with the pulse amplitude.
If a circuit has a fully differential structure, then use two pulse_oscillator
commands: one connected to the positive and negative branch of the
differential structure and one applied with opposite polarity.
Examples
pulse_oscillator -node xosc.pl -pw 1n -time 10u -amp 1u
pulse_oscillator -node xosc.nl -pw 1n -time 10u -amp -1u
Releases the node voltages from the values fixed by force_node_voltage.
When you specify this command, the simulation results determine the node
voltages.
Syntax
release_node_voltage -node node_name {node_name}
[-time time_value] [-subckt subckt_name]
-node node_name Specifies the node names to release.

{node_name}
-time Specifies the time to release the nodes. The default is 0.

time_value
-subckt Releases only the nodes inside the specified subcircuit.

subckt_name

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Examples
release_node_voltage vpump -time 150ns
The vpump signal previously forced to a given value is released at 150ns. The
simulation results determine the vpump voltage value until the end of the run
unless you use a new force_node_voltage command.
Reports dangling nodes in a separate file.
Syntax
report_dangling_node enable_value
enable_value By default, when this option is off, the CustomSim tool reports
dangling nodes in the log file. Turn this option on to report
dangling nodes in a separate file with the following format:
sim_output_file_name.dng.
report_model
Reports detailed model information. This command lets you generate reports
that contain detailed model information similar to what the Eldo™ format
provides in the .chi file.
Syntax
report_model -report report_value
[-generate enable_value] [-stop enable_value]
[-count model|subckt|all|none]

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report_node_alias
-report Specifies one of the following values:

report_value ■
1 to generate a condensed report. DEVICE, MODEL,
TYPE, LEVEL, and INSTANCE information is provided,
but the detailed list of model parameters is suppressed.
■
2 to generate a full report, including detailed model
parameters.
-generate Generates a netlist that contains .model cards and a single

enable_value instantiation of each unique model instance. None of the
original circuit netlist connectivity is in the file. This
information is written to a file with a .model extension.
-stop Stops the simulation after front-end processing before

enable_value starting DC or transient analysis. This argument can provide
a quick analysis to help debug models.
-count Specify one of the following options to control how to report

model|subckt|all the list of models.
|none ■
model to report the list of all models and their count in the
.modelinfo file.
■
subckt to report the list of all subcircuits and their count
in the .modelinfo file.
■ all to report the list of all models and subcircuits and their
count in the .modelinfo file.
■ none (default) to not report model and subcircuit
information in the .modelinfo file.
report_node_alias
Reports all the aliased nodes in the report files.
Syntax
report_node_alias -hierarchy enable_value | -short
enable_value

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report_node_cap
-hierarchy If set to 1, reports all hierarchy node aliases to a file. The

enable_value default is 0, which does not report hierarchy node aliases.
-short If set to 1, reports all hierarchy node aliases to a file. The

enable_value default is 0, which does not report shorted node aliases.
Description
This command prints the nodes that have aliased node names. A node might
have an alias because of:
■
Hierarchical alias names from instances of subcircuits.
■ Shorted alias names due to very small resistors or a DC voltage source of
0 volt connected to a node.
The primary node name is the node name that remains in the database. The
alias node name is the name that is removed from database. The alias output
file has two or more columns such as:
<primary_node_name> <alias_node_name_0> …
<alias_node_name_n>
Examples
report_node_alias –hierarchy 1
Reports all hierarchy alias nodes in output_file.nodealias.

report_node_alias –short 1
Reports all shorted nodes in output_file.nodealias.

report_node_alias -hierarchy 1 –short 1
Reports all hierarchy alias nodes and all shorted nodes in

output_file.nodealias.
report_node_cap
Reports capacitance information for the specified nodes.

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report_node_cap
Syntax
report_node_cap -node node_name {node_name}
[-short_resistor value] [-group group_name]
[-limit limit_value] [-report basic|detail]
-node node_name Reports capacitance for the node names you specify. You can
{node_name} use wildcard characters in the node names.
-short_resistor Specifies the value of the resistor to be shorted. The default

value value is 0, which means none of the resistors are shorted.
-group group_name Creates a group name for the nodes you specify with -node.
If you specify this option, all nodes for a report_node_cap
command are grouped together. the CustomSim tool reports
the capacitance information based on this group.
Use this option only for a flat, postlayout design.
-limit Specifies the hierarchy level down to which CustomSim

limit_value reports the capacitance information. The default is 3.
-report Specifies the type of report to print. Use the basic keyword
basic|detail (the default) to print only the basic capacitance information.
Use the detail keyword to print a detailed report.
Description
The reported node capacitance information includes total node capacitance,
wire capacitance, gate capacitance of a MOSFET, and junction capacitance of
a MOSFET. You can specify multiple commands in a simulation. the
CustomSim tool processes each command separately.
report_node_cap outputs the capacitance information in a *.cap# file.
In a prelayout design, capacitance is reported as:
Ctotal = Cgate + Cjunction + Cwire
Cgate = Cgd + Cgs + Cgb
Cjunction = Cdb + Csb
Cwire = Cdesign

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report_node_cap
In postlayout design, the CustomSim tool expands a single node from the
prelayout design into multiple nodes because of the RC parasitics. The
postlayout flow is divided into 2 scenarios:
■
A back-annotated postlayout.
■
A flat postlayout.
In the back-annotated postlayout flow, you can trace the connectivity back to
the prelayout design with the information from the prelayout netlist and the
back-annotation file:
*|NET na 0.00458507PF <-- Net Capacitance (CBAnet)
*|I (x02/mp:GATE x02/mp GATE I 4.8e-16 22.75 3.25) //
$llx=22.55 $lly=3.25 $urx=22.95 $ury=3.25 $lvl=5
*|I (x02/mn:GATE x02/mn GATE I 2.4e-16 22.75 1.05) //
*|I (x01/mp:DRN x01/mp DRN B 0 8.45 3.25) // $llx=8.45
$lly=2.65 $urx=9.2 $ury=3.85 $lvl=7
*|I (x01/mn:DRN x01/mn DRN B 0 8.45 1.05) // $llx=8.45
$lly=0.75 $urx=9.2 $ury=1.35 $lvl=6
*|S (na:1 22.75 2.65) // $llx=22.55 $lly=2.65 $urx=22.95
$ury=2.65 $lvl=3
*|S (na:2 22.75 3.925) // $llx=22.55 $lly=3.85 $urx=22.95
$ury=4 $lvl=5
Cg1 na:1 0 4.33011e-17
Cg2 na:2 0 3.99892e-17
...
R158 na:1 x02/mp:GATE 4.8 $l=0.6 $w=0.4 $lvl=5
R159 na:1 na:3 30 $l=0.8 $w=0.4 $lvl=3
R160 x02/mp:GATE na:2 5.016 $l=0.675 $w=0.4 $lvl=5
R161 na:3 na:4 16.875 $l=0.5 $w=0.4 $lvl=3
R162 na:3 na:5 18.75 $l=0.5 $w=0.4 $lvl=3
R163 na:3 na:8 3.96 $a=0.04 $lvl=10
R164 na:4 na:6 3.96 $a=0.04 $lvl=1
...

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report_node_cap
R186 na:18 x01/mn:DRN 5.38888 $a=0.09 $lvl=12

R187 na:19 na:20 0.992002 $l=0.8 $w=0.5 $lvl=2
R188 na:19 na:21 13.1234 $l=6.45 $w=0.3 $lvl=2
R189 na:20 na:24 0.744002 $l=0.6 $w=0.5 $lvl=2
R190 na:20 x01/mp:DRN 5.38888 $a=0.09 $lvl=12
...
In back-annotated post-layout flow, the capacitance information is reported as:
Cwire = CBAnet + Cdesign
Based on the previous back-annotation file example:
Cgate = Cgate(x02/mp) + Cgate(x02/mn)
Cjunction = Cjunction(x01/mp) + Cjunction(x01/mn)
Cwire = CBAnet (0.00458507PF) + Cdesign
In a flat postlayout flow, the CustomSim tool treats all nodes as unique and
independent. To accurately calculate the capacitance information, you need to
group the nodes and then run report_node_cap. For example, see Figure 1.

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report_node_cap
Figure 1 Flat Postlayout Flow Example
In Figure 1, a prelayout node, BT, has been expanded into different nodes in
the postlayout. Because the postlayout netlist is flat, and there is no trace of
connectivity from the prelayout netlist and back-annotation flow, all nodes are
treated as unique and independent.
To accurately report the capacitance information, you need to tell the
CustomSim tool which nodes can be grouped together for report_node_cap
command to calculate the capacitance information. To group a list of nodes into
one group, use -group argument and list the names of nodes to be grouped:
BT_0, BT_1, BT_2, BT_3, BT_4, BT_5, BT_6, XPERI.BT_7, XCELL1.BTR,
XCELL2.BTR, XCELL3.BTR, and XCELL4.BTR and do the following steps:
1. Specify the following report_node_cap command.
report_node_cap -node BT_? XPERI.BT_7 XCELL?.BTR -group BT
This command groups all the specified node names into one group named
BT.
2. Assuming all parasitic capacitor has a value of 1 fF, the CustomSim tool
calculates the capacitance information is as:

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Cgate = Cgate(XPERI.MA1)
Cjunction = Cjunction(M2) + Cjunction(XCELL1.M1) +
Cjunction(XCELL2.M1)
+ Cjunction(XCELL3.M1) + Cjunction(XCELL4.M1) +
Cjunction(XPERI.MA1)
Cwire = (12 * 1 fF) + Cdesign
Cdesign = 0 pF
Determines how CustomSim exports initial conditions it computes in DC
analysis. It also defines how CustomSim reports the results of latch (and other
circuit types) detection. The initial conditions are dumped in a file named
prefix.time.ic. Note that you cannot specify multiple
report_operating_point commands.
Syntax
report_operating_point -time dc|end|time_value
{dc|end|time_value} [-report all|core]
[-file file_name] [-node_type node_type]
[-type ic_type] [-subckt subckt {subckt}]
[-inst inst {inst}]
[-node_details switch_value]
-time Specifies the time to dump the operating point:

dc|end|time_value ■
dc for a time value of 0.
■ end for the transient end time.
■
time_value for a user-defined time.
-report all|core Specify core (the default) to dump the subset of the core
nodes the CustomSim tool needs to determine the
operating point. Specify all to force all nodes to be written
to a file.

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-file file_name Adds operating point information to the specified file. The
default file name is prefix.time.ic.
-node_type Limits the application of initial conditions to nodes detected

node_type as node_type. A list of arguments is supported. Currently
only the latch node_type is supported to limit the
application of initial conditions to detected latches.
-type ic_type Specifies the type of initial condition to be applied. The

ic_type can be ic or nodeset. This option overrides
what is specified in the file.
-subckt subckt Limits the application of initial conditions to nodes of the

{subckt} instances of subckt. A list of arguments is supported.
Wildcards are not supported.
-inst inst {inst} Limits the application of initial conditions to the specified
instances. Wildcards are supported.
-node_details You can specify one of the following for switch_value:

switch_value ■ 0 (default) does not list node details.
■
1 lists node details in a separate file. The file name is
created by appending .op_table to the name of the
initial conditions file (for example,
xa.0.ic.op_table).
Examples
report_operating_point 0 -node_type latch -type nodeset
Writes out a prefix.0.ic file containing initial conditions from time 0 as

nodeset for latch nodes only.
report_operating_point 10n -file 10n-op -subckt latch_fast -
node_type latch
Writes out a 10n-op file containing initial conditions from time 10n as ic only for
latch nodes and nodes in instances of the latch_fast subcircuit.
report_operating_point -time 0 -node_details 1
Writes out a prefix.0.ic file containing initial conditions from time 0 as ic for
all nodes, including node details. The node details are in the
prefix.0.ic.op_table file.

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report_power
report_power
Generates power consumption reports.
Syntax
Reporting by port name:
report_power -port port_name {port_name}
[-label label_name] [-twindow tstart [{tstop}]
{tstart [tstop]}]
[-limit level] [-subckt subckt]
[-avg enable_value] [-rms enable_value]
[-max enable_value] [-min enable_value]
[-probe enable_value] [-except_port except_pattern]
Reporting by node name:
report_power -by_node node_name {node_name}
[-label label_name] [-twindow tstart [{tstop}]
{tstart [tstop]}]
[-limit level] [-subckt subckt]
[-avg enable_value] [-rms enable_value]
[-max enable_value] [-min enable_value]
[-probe enable_value] [-except_port except_pattern]
[-report basic|detail]
-port port_name Specifies the currents to report based on port names.

{port_name} A preceding ‘‘*’’ or ‘‘.’’ character in the port name is
optional.
-by_node node_name Specifies the currents to report based on connectivity.

{node_name} You can use wildcards in the node names.
-label label_name Specifies the text label for the report file.
-twindow tstart tstop Performs the check within the time window defined by
{tstart tstop} tstart tstop {tstart tstop}. The tstart and
tstop must come in pairs, except for the final window
where if tstop is not specified it is be assumed to be
the end of the simulation. The final tstop can also be
the end or END keyword.

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report_power
-limit level Specifies the maximum hierarchical depth for the

report. The default is 3.
-subckt subckt Specifies a subcircuit name for current reporting. Note

that you cannot use this argument with the
-by_node argument.
-avg enable_value Specifies whether to report the average value. The

default is 1 for printing the average value. See the
Common Syntax Definitions section for details about
the enable_value argument.
-rms enable_value Specifies whether to report the rms value. The default
is 1 for printing the rms value. See the Common
Syntax Definitions section for details about the
enable_value argument.
-max enable_value Specifies whether to report the maximum value. The

default is 1 for printing the maximum value. See the
-min enable_value Specifies whether to report the minimum value. The

default is 1 for printing the minimum value. See the
-probe enable_value Enables or disables the probing of ports: 1, true, or

on to enable; 0, false, or off to disable. The default
is 0.
-except_port Excludes ports that match the except_pattern

except_pattern from the report. You can specify wildcards in the
pattern name.

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report_power
-report basic|detail If detail is set, the following information is printed:

Sub-circuit Level: xx
Percentage of top sub-circuit: Avg(%)=
xx Rms(%)= xx
Percentage of parent sub-circuit:
Avg(%)= xx Rms(%)= xx
The default is basic. This argument is only supported
with -by_node.
Description
report_power produces a text report file that contains subcircuit port
currents. There are two methods for specifying the reporting ports: by the port
name or by connectivity. The report appears in the file.power file. The
-limit argument specifies the absolute hierarchical depth. The top level of
the netlist hierarchy is 0.
To specify reporting by port name, use the –port argument. A subcircuit port
name is defined by a subcircuit definition (.subckt subname portname1
portname2 … ). A leading “*” wildcard and “.” hierarchical delimiter are
optional. You can use the –subckt argument to scope specific subcircuits. You
can also use the –except_port argument to exclude some ports. Any port
names matching the exclude pattern are not reported.
To specify reporting by connectivity, use the –by_node argument. The ports/
terminals of the instances connected to the named nodes have their power
reported. The CustomSim tool automatically creates a port/terminal list based
on the connecting subcircuit and ideal voltage and current sources to the
specified nodes. The list of ports and terminals traverses the hierarchy based
on the –limit option. A power/current report is not generated for any
primitive element other than ideal voltage and current sources. MOS, BJT,
resistors, capacitors, and so on are excluded from the power/current report.
Subcircuit instances that the CustomSim tool detects as a MOS macro model
are also excluded. You can use the –except_port argument to exclude
some ports. Any port names matching the exclude pattern are not reported.
A warning is issued when any of the excluded elements do connect to the
specified node. The warning message is consistent with other CustomSim
warnings. By default, only the first 10 warning are printed and can be controlled
with the set_message_option command.

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report_power
If –by_node is applied, the report is generated for those subcircuits/elements

at that level of hierarchy, even if the hierarchal level is exceeded in the
–limit value. Additional levels of hierarchy are only included if they meet the
–limit value. If a wildcard is used in the -by_node pattern, the –limit
setting limits the hierarchical depth of the wildcard match. Power is reported as
if all matched nodes had been explicitly named. Thus the maximum port depth
in this scenario is the limit value +1.
If the -by_node is also the name of a port, its power is reported, as well as
that of any connected subcircuit ports further down in the circuit hierarchy. It
does not report any ports connected up in the hierarchy.
The –except_port argument excludes some ports from being reported. The
proper way to conceptualize this behavior is to first determine which ports
match the patterns specified by –port or –by_node and exclude any ports
that match the pattern. For more details about excluding ports, see the
following examples.
Examples
The following example shows sample report file content.
###### LABEL=x1_ports_0_1u FROM=0 TO=1e-06 #####
Port Name: x1.vdd (vdd)

Sub-circuit Definition: buf8
Max(A)= 4.3845644e-03 at = 2.0847267e-07 Min(A)= 4.8172598e-
12 at = 5.1890557e-09 Avg(A)= 1.2179682e-04 Rms(A)= 6.3463403e-
04
Max(W)= 1.3153693e-02 at = 2.0847267e-07 Min(W)= 1.4451779e-
11 at = 5.1890557e-09 Avg(W)= 3.6539046e-04 Rms(W)= 1.9039021e-
03
Port Name: x1.x_buf1.vdd (vdd)

Sub-circuit Definition: buf4
Max(A)= 4.3099853e-03 at = 3.0768178e-07 Min(A)= 2.3878731e-
12 at = 5.1890557e-09 Avg(A)= 5.9134919e-05 Rms(A)= 4.2502434e-
04
Max(W)= 1.2929956e-02 at = 3.0768178e-07 Min(W)= 7.1636193e-
12 at = 5.1890557e-09 Avg(W)= 1.7740476e-04 Rms(W)= 1.2750730e-
03
report_power supports on-the-fly reporting. At the conclusion of a report

window, as specified by the -from and arguments, the report is written to the
output file.

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report_power
Example 16 Reporting by Port Name

.global vdd vss
.subckt level1 a
R1 vdd a r=1k
R2 a vss r=1k
X2 a level2
.ends
.subckt level2 a
R1 vdd a r=1k
R2 a vss r=1k
X3 a level3
.ends
.subckt level3 a
R1 vdd a r=1k
R2 a vss r=1k
X4 a level4
.ends
.subckt level4 a
R1 vdd a r=1k
R2 a vss r=1k
.ends
*Top level netlist start here, level=0

vvdd vdd 0 dc=3
vvss vss 0 dc=0
v0 a 0 dc=2
X1 a level1
.tran 1n 5n
.opt xa_cmd="set_sim_level 7"
*-limit is used to specify a hierarchical level:

.opt xa_cmd="report_power -port a -label atlevel0 -limit 0"
*The above does not report anything because 'a' is not a port,
*but is a net at top level (level 0).
.opt xa_cmd="report_power -port a -label atlevel1 -limit 1"

*The above will report power in X1.a, because a is a port for X1
*which is the 1st level of hierarchy (-limit 1)
.opt xa_cmd="report_power -port a -label sublevel2 -subckt level2"

*The above will report power in a port named "a" within subckt
*level2: X1.X2.a

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report_power
.opt xa_cmd="report_power -port a -label porta"

*The above will report power thru all ports "a" in all subcircuits
*down to the hierarchical level 3 because if -limit is unspecified
*it defaults to 3:
*X1.A, X1.X2.A, X1.X2.X3.A; but not X1.X2.X3.X4.a
.opt xa_cmd="report_power -port vdd"

*The above will report power thru all ports VDD in all subcircuits
*down to hierarchical level 3.
.end
Example 17 Reporting by Connectivity

.global vdd
vvdd vdd 0 3
X1 in out vdd 0 ckt1
.subckt ckt1 in out vdd vss

X1 in n1 vdd vss block1
X2 n1 n2 vdd vss block2
X3 n2 out block3
M1 vdd n1 n5 vss nmos
R1 n5 vss
.ends
.subckt block1 clkin clkout vdd vss

X1 clkin int1 vdd vss inv
X2 int1 clkout vdd vss inv
.ends
.subckt block2 input output vcc vss

X1 clkin int1 vcc vss inv
X2 int1 clkout vcc vss inv
.ends
.subckt block3 clkin clkout

X1 clkin int1 vdd vss inv
X2 int1 clkout vdd vss inv
.ends
If you specify the following command:

report_power –by_node vdd –limit 1
For the previous netlist, report_power generates a power/current report of
the following ports:
vvdd

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report_power
x1.vdd
This command generates a power/current report of the following ports:
vdd
x1.vdd
x1.x1.vdd
x1.x2.vcc
x1.x2.vdd
x1.x3.vdd
Note: Because of the global vdd statement exists in all subcircuit

instances, but since the vdd port of the x1.x2 subcircuit is not
connected, the report for this subcircuit is 0. Also, power/current
report is generated for subcircuit and ideal voltage and current
sources only. A report is not generated for other primitive
elements or macro-models connected to the specified node, for
example X1.M1.

vvdd
x1.vdd
x1.x1.vdd
x1.x1.x1.vdd
x1.x1.x2.vdd
x1.x2.vcc
x1.x2.vdd
x1.x2.x1.vcc
x1.x2.x1.vdd
x1.x2.x2.vcc

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report_power
x1.x2.x2.vdd
x1.x3.vdd
x1.x3.x1.vdd
x1.x3.xd.vdd
Note: A power/current report is not generated for non-subcircuit

elements or macro-models, for example, X1.M1.
To further illustrate port reporting, here is another sample netlist:
X1 nodeA out ckt1

.subckt ckt1 in out
X2 nodeB out ckt2
…
.ends
.subckt ckt2 in out
X3 nodeC out VBIAS
…
.ends
.subckt VBIAS node1 VBIASOUT
X4 node1 VBIASOUT VREG
X5 VBIASOUT node2 LOAD
.ends
.subckt VREG IN OUT
…
.ends
.subckt LOAD IN OUT
…
.ends

report_power –by_node X1.out -limit 3
X1.out
X1.X2.out
X1.X2.X3.VBIASOUT
report_power –by_node X1.X2.X3.VBIASOUT -limit 2

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report_power

X1.X2.X3.X4.OUT
X1.X2.X3.X5.IN
X1.X2.X3.VBIASOUT
Note: Although VBIASOUT is at level 3 of the hierarchy and -limit 2

is specified the reports are still generated because the node is
explicitly named.
Here is another example netlist with port reporting examples:

.subckt bottom a b
R1 a 0 r=1k
R2 b 0 r=1k
.ends
.subckt top 1 2
Rtop1 1 z r=100
Rtop2 2 y r=100
Xbottom 1 y bottom
.ends
Xtop a b top
Xtop2 a b top

report_power –by_node xstop1
For the previous netlist, report_power generates a power/current report as
follows:
■ Node xtop.1 is a port so it is reported. This port connects the node up
the hierarchy.
■ For Xtop.xbottom.a, this port is connected to the node xtop.1, but is
down the hierarchy. Note that if you did not use the -by_node argument this
port is not reported.
■
This example does not report xtop2.1.

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report_power
Example 18 Sample Netlist Reporting with the -except_port Argument

.subckt superhuge3 vdd en
…
.ends
.subckt huge1 vdd en
…
.ends
.subckt huge2 vdd en
…
.ends
.subckt regulator vdd regvdd
…
.ends
.subckt tlc din dout vdd
Xreg vdd regvdd regulator
X1huge regvdd en1 huge1
X2huge regvdd en2 huge2
X3huge regvdd en3 superhuge3
.ends
Xchip din dout vdd tlc
Vvdd vdd 0 pwl 0 0 100n 3.3

report_power –port vdd -except_port xchip.x3huge*
For the previous netlist, report_power first finds all the ports that match vdd:
Xchip.vdd
Xchip.xreg.vdd
Xchip.x1huge.vdd
Xchip.x2huge.vdd
Xchip.x3huge.vdd
Then report_power remove s anything from the above that matches
xchip.x3huge.*, leaving:
Xchip.vdd
Xchip.xreg.vdd
Xchip.x1huge.vdd
Xchip.x2huge.vdd

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report_power
report_power –by_node xchip.regvdd -except_port

xchip.x3huge*
For the previous netlist, report_power first finds all the ports connected to
xchip.regvdd:
Xchip.xreg.regvdd
Xchip.x1huge.vdd
Xchip.x2huge.vdd
Xchip.x3huge.vdd
Then report_power removes anything from the above that matches
xchip.x3huge.*, leaving:
Xchip.xreg.regvdd
Xchip.x1huge.vdd
Xchip.x2huge.vdd
Here is another sample netlist example to illustrate the -except_port
argument.
.subckt regulator vdd vdd3v3 vdd5v vaa vcc vee vss vss3v3 vss5v
…
.ends
.subckt huge vdd vdd3v3 vdd5v vaa vcc vee vss vss3v3 vss5v
…
.ends
.subckt tlc
Xreg vdd vdd3v3 vdd5v vaa vcc vee vss vss3v3 vss5v regulator
X1 vdd vdd3v3 vdd5v vaa vcc vee vss vss3v3 vss5v huge
X3 vdd vdd3v3 vdd5v vaa vcc vee vss vss3v3 vss5v huge
.ends
Xchip tlc

report_power –port v* -except_port *vee *vss* xchip.x3*
For the previous netlist, report_power first finds all the ports that match v*:
Xchip.xreg.vdd
Xchip.Xreg.vdd3v3
Xchip.Xreg.vdd5v
Xchip.Xreg.vaa
Xchip.Xreg.vcc

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report_power
Xchip.Xreg.vee
Xchip.Xreg.vss
Xchip.Xreg.vss3v3
Xchip.Xreg.vss5v
Xchip.x1.vdd
chip.X1.vdd3v3
Xchip.X1.vdd5v
Xchip.X1.vaa
Xchip.X1.vcc
Xchip.X1.vee
Xchip.X1.vss
Xchip.X1.vss3v3
Xchip.X1.vss5v
Xchip.x3.vdd
Xchip.X3.vdd3v3
Xchip.X3.vdd5v
Xchip.X3.vaa
Xchip.X3.vcc
chip.X3.vee
chip.X3.vss
Xchip.X3.vss3v3
Xchip.X3.vss5v
Then report_power excludes ports that match *vee *vss* xchipx3*,
leaving:
Xchip.xreg.vdd
Xchip.Xreg.vdd3v3
Xchip.Xreg.vdd5v
Xchip.Xreg.vaa
chip.Xreg.vcc

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report_power
chip.x1.vdd
Xchip.X1.vdd3v3
Xchip.X1.vdd5v
Xchip.X1.vaa
Xchip.X1.vcc

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report_power
Example 19 Sample Netlist Reporting Using Wildcards
.subckt fee r
rr r 0 r=1k
.ends
.subckt bar p q
r1 p 0 r=10
iq q 0 dc=0.1m
fee p fee
.ends
.subckt foo a b c
ra a a1 r=10
a a1 0 dc=1u
b b b1 r=10
ib b1 0 dc=2u
rc c c1 r=10
ic c1 0 dc=0.5u
xbar a b bar
xbar2 a1 b bar
.ends
.subckt top 1 2 3
X1 1 1 1 foo
x2 2 3 3 foo
x3 3 3 3 foo
.ends
xcut 1 2 3 top
v1 1 0 dc=1
v2 2 0 dc=2
v3 3 0 dc=3
.opt xa_cmd="report_power -by_node xcut.x1.* -label wildcardlimit

-limit 1"
* This reports nothing because all matched patterns exceed limit
value
.opt xa_cmd="report_power -by_node xcut.x1.a* -label

wildcard_a*_limit -limit 1"
* This reports nothing because all matched patterns exceed limit
value
.opt xa_cmd="report_power -by_node xcut.x1.a* -label

wildcard_a*_limit2 -limit 2"

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set_active_net_flow
* xcut.x1.a
* xcut.x1.ia (power_element)
* xcut.x1.xbar.p
* xcut.x1.xbar2.p
.opt xa_cmd="report_power -by_node xcut.x1.a -label

defined_a_limit2 -limit 2"
.opt xa_cmd="report_power -by_node xcut.x1.a1 -label
defined_a1_limit2 -limit 2"
* These two command together should produce the same output as
the previous
.opt xa_cmd="report_power -by_node xcut.1 -label defined_1_limit2

-limit 2"
.opt xa_cmd="report_power -by_node xcut.1 -label defined_1_limit1
-limit 1"
* because a named node always report the power of a port conencted
to it, the above
* will produce the same result.
.opt xa_cmd="report_power a -label port_a_limit2 -limit 2"

* note that when specifying by port, limit is a hard limit to the
port hierarchical level
* but with -by_node you can get 1 level deeper.
See Also
set_wildcard_rule
set_active_net_flow
Triggers the automated active net flow.
Syntax
set_active_net_flow [-enable] enable_value [-vtol
numeric_value] [-twindow tstart tstop {tstart tstop}]
[-reuse_active_net enable_value]
[-reuse_ic enable_value] [-setup_cmd cmd_file]
-enable enable_value Runs the active net flow. The default is 1.

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set_active_net_flow
-vtol numeric_value Specifies the tolerance voltage difference. A node is

considered active if the node voltage varies larger than
the specified value. The default value is 100mV.
-twindow tstart tstop Specifies the time windows to be checked for active
{tstart tstop} nodes. If you specify this argument, the check is limited
to the specified time windows.
The default for tstart is 0 and tstop is the end of
transient simulation time. The keywords end and END
are supported for tstop to specify the end of the
simulation. The time window has to be specified in a
pair, except for the last entry. If the last entry has only
one value, tstop defaults to END.
-reuse_active_net Instructs the CustomSim tool to reuse the active net file
enable_value information and avoid rerunning the first pass for a data
sweep. The default is 1, which specifies to reuse the
active net file. Set this option to 0 to rerun the entire flow
and regenerate the active net file. This reuse of the
active net file is also the default behavior for .alter/
bisection optimization flow.
-reuse_ic By default the CustomSim tool reuses the prelayout

enable_value .nodeset. if you enable this option, the CustomSim tool
uses .ic instead of .nodeset.
-setup_cmd cmd_file By default, the CustomSim tool uses the same

command for both the first and second run. If you specify
this option, you can change three commands in the
setup run to further speed-up the setup simulation. The
three commands are: set_sim_level, set_model_level,
and set_synchronization_level.
Description
The active net flow automatically runs a prelayout simulation (ignores the
load_ba_file command) and generates the active net information to use in the
postlayout simulation. Its usage is limited to the back-annotation flow.

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set_ams_view
set_ams_view
Controls whether a SPICE subcircuit or a Verilog-A module definition (or “view”)
is used for the entire netlist, or for an instance or subcircuit when both SPICE
and Verilog-A definitions exist for that instance or subcircuit.
Syntax
set_ams_view -view VA|va|SPICE|spice
[-inst inst_name {inst_name}]
-view VA | va Specifies that Verilog-A module definitions have priority

over SPICE subcircuit definitions.
SPICE | spice Specifies that SPICE subcircuit definitions have priority

over Verilog-A module definitions.
-inst inst_name Specifies a particular instance or set of instances the

{inst_name} set_ams_view command will affect. See Common
Syntax Definitions for more about specifying instance
names.
-subckt subckt_name Specifies a particular subcircuit or set of subcircuits the

{subckt_name} set_ams_view command will affect. See Common
Syntax Definitions for more about specifying subcircuit
names.
Description
If your design has both SPICE subcircuit definitions and Verilog-A definitions,
you can switch between SPICE and Verilog-A depending on the type of
analysis you want to perform. This lets you achieve tradeoffs between the
speed and accuracy of the simulation for particular definitions. Use the
set_ams_view command to perform module- and instance-based partitioning
of the circuit definitions. You can switch to a Verilog-A module description for a
single SPICE subcircuit, or set of subcircuits, within a netlist.
If multiple definitions or “views” of a SPICE subcircuit or Verilog-A module exist,
the CustomSim tool defaults to use the view of the parent netlist. If you set the
entire netlist to use SPICE (set_ams_view -view SPICE), then any
subcircuit instance will use the subcircuit definition by default. If you set the
entire netlist to use Verilog-A (set_ams_view -view VA), then the Verilog-A

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set_ams_view
module definitions will be used by default; if the module definition does not exist
then the subcircuit view is used.
If you specify set_ams_view for a specific subcircuit or instance, then that
subcircuit or instance will use the definition you specify (SPICE or Verilog-A),
as shown in the following examples.
If set_ams_view references a view that does not exist, a warning message
appears and the other view is used. If neither a SPICE nor a Verilog-A
definition exist for the subcircuit, the CustomSim tool returns an error and the
simulation is terminated.
Note: If an Eldo instance is declared with a y element, the Verilog-A

definition is used in all cases. It cannot be overridden with the
set_ams_view command.
Examples
Example 20 shows an HSPICE netlist that will use the SPICE view by default.
Example 20 Netlist using SPICE definitions by default
.hdl mymodule.va
.subckt mymodule a b
...
.ends mymodule
X1 1 2 mymodule
X2 3 4 mymodule
X3 5 6 mymodule
The command in Example 21 sets the SPICE view for all subcircuits and
modules in a netlist.
Example 21
set_ams_view SPICE
The command in Example 22 sets the Verilog-A view for all subcircuits and
modules in a netlist.
Example 22
set_ams_view VA
In Example 23, the Verilog-A module definition will be used for all instances of
subcircuit my_module.
Example 23
set_ams_view VA -subckt mymodule

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set_array_option
If the netlist contains the command in Example 24, the Verilog-A module
definition will be used for subcircuit instance X2 of my_module.
Example 24
set_ams_view VA -inst X2
See Also
“Netlist Syntax for Verilog-A in CustomSim” in the CustomSim User Guide
for details about how to include Verilog-A definitions in HSPICE, Spectre, or
Eldo netlists.
set_array_option
Provides user control over the effects of the CustomSim SPICE optimization for
array (SOFA) technology.
Syntax
set_array_option -array_detection enable_value
[-cell_gndcap_tol tol_value]
[-cell_subckt cell_subckt_name[.controlling_port]]
[-flash_array enable_value]
[-rc_optimize enable_value]
-array_detection Determines whether the CustomSim tool applies array

enable_value optimization. Specify 0 to turn array optimization off. The
default is 1.
-cell_gndcap_tol Sets the relative tolerance for equalizing capacitor

tol_value values for isolated ground capacitors inside memory
cells. Values of ground caps are modified by not more
than tol_value ( abs((c-c_modified)/c)<=tol_value) to
make more in-cell capacitors equal to each other across
the different cells forming an array. This helps array
optimization for some post-layout memory arrays. The
valid range is 0% to 100%. The default is 15%.

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set_ba_option
-cell_subckt Lets you manually provide the memory cell subcircuit

cell_subckt_name name with optional controlling ports. the CustomSim tool
.controlling_port automatically detects the controlling port of the memory
cell, but if the CustomSim tool failed to do that, you can
add one or more controlling port names right after the
cell_subckt_name with the "." concatenation.
Controlling ports generally represent word line ports of
the memory subcircuit.
-flash_array If set to 1, this option enables detection of arrays of flash

enable_value cells of single MOSFET or floating gate. The default is 0.
-rc_optimize Set this option to 1 (default) to apply post-layout array

enable_value optimization (SOLE4SOFA). Set it to 0 to disable post-
layout array optimization.
Description
The SOFA algorithm transforms a memory array cell to an optimized array
model to minimize their solve times while maintaining accuracy from the current
set_sim_level settings. set_array_option can be useful for debugging
simulations, or in other special circumstances when it is desirable to have the
ability to disable the array optimization.
set_ba_option
Adjusts how the CustomSim tool handles back-annotation.
Syntax
set_ba_option -short_pins switch_value
[-lump_c_only switch_value]
[-dpf_scale scale_value]
[-dpf_elem_type type {type}]
[-finger_prefix prefix_string]
[-active_net_file file_name {file_name}]
[-report_large_net value]
[-enable_error_net setting_value]
[-keep_prelayout_cap switch_value]
[-bus_delimiter left_char righ_char]
[-select_ipin_method method_value]

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set_ba_option
[-swap_port port1 port2 sub_name] [-min_res value]

[-max_res value] [-min_cap value]
[-report_trim_rlc enable_value]
-short_pins Sets one of the following values:

switch_value ■
0|off|no|false to disable shorting multiple pins
together from the DSPF/SPEF file.
■
1|on|yes|true to short multiple pins together (the
default).
-dpf_scale Applies a scale_value to the DPF section of the DSPF

scale_value file. This is a global setting and applies to all DSPF files
that are used for a given simulation. The default value for
scale_value is 1, meaning no scale applies to the DPF
section and the CustomSim tool assumes the actual
proper dimension is used in the DPF section.
This argument takes both a unit or numerical value such
as 1u or 1e-6.
-lump_c_only When set to 1, reads in the net capacitance value from

switch_value the NET line and only back-annotate the lumped
capacitance of that net and ignore the distributed RC
back-annotation. The default is 0.
-dpf_elem_type type Lets you specify the types of elements you want to back-
{type} annotate from a DPF file. Table 5 shows the supported
element types.
Note that -dpf_elem_type mos is equivalent to the
-dpf_mos_only 1 option in the previous CustomSim
release.
-finger_prefix Instructs the CustomSim tool to use the

prefix_string prefix_string to identify finger devices. The default
string is the @ character.
-active_net_file Instructs the CustomSim tool to back-annotate the full

file_name{file_name} RC for the active nets from the SPF/SPEF file. For
inactive nets, the lump C value is added.
You must use this argument with the load_ba_file
command.

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set_ba_option
-report_large_net Reports large SPF nets as warnings in the CustomSim

value log file. By default, any net with an RC element count
greater than 1000 is reported in the CustomSim log file.
-enable_error_net Specifies one of the following three options:

setting_value ■
0 | off | no | false ignores back-annotation of the
net (the default).
■
1 | on | yes | true ignores elements connected to
incorrect terminal only. This argument tells the
CustomSim tool to ignore the back-annotation of an
instance (*|I) with an incorrect terminal, and any
element connected to it. All other elements are back-
annotated to the net.
■
lump back-annotates lumped capacitance to the net.
This argument tells the CustomSim tool to add the
total lumped capacitance specified in the back-
annotation file to the net.
If source (SRC) is misconnected to drain (DRN), or vice-
versa, the CustomSim tool automatically swaps the
connection of those two terminals. If any other
misconnection exists, the simulator does not back-
annotate the net unless the -enable_error_net
option is used.
You can use this option only once. Otherwise the last
entry overrides all previous entries.
-keep_prelayout_cap Determines how the CustomSim tool deals with a

switch_value prelayout netlist that contains ground capacitors with the
same node name as the SPF net in the DSPF file.
Specify one of the following values:
■ 0 overwrites the prelayout net capacitance with what
is defined in the DSPF netlist.
■
1 (default) keeps all the ground capacitors in the
prelayout netlist and add the remaining capacitors in
the back-annotation file.
This option applies only to ground capacitors. Coupling
capacitors are not considered. Also, the CustomSim tool
issues a warning message when the prelayout net
capacitance is overwritten by the DSPF netlist.

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set_ba_option
-bus_delimiter Modifies the bus character only inside the SPEF file.
left_char righ_char You can specify the left_char and right_char to
match the prelayout node names. The supported bus
delimiters are [] and <>.
-select_ipin_method Instructs the CustomSim tool to select which ipin to use

method_value for any type of analysis such as .probe/.measure/
.ic/.nodeset, or any statement that uses the NET
name. This option has no impact for NETs with a *|P
statement.
You can specify one of the following values:
■
0 to choose the first instance pin as the
representative node. This is the default value.
■
1 to choose the last instance pin as the
representative node.
■
2 to choose the first instance pin as the
representative node after sorting of (*|I).
■
3 to choose the last instance pin as the
representative node after sorting of (*|I).
-swap_port port1 Allows port swapping for subcircuit (macromodel)

port2 sub_name terminals.
-min_res value Specifies the global lower threshold of the resistors from
the back-annotated DSPF/SPEF to be kept. All resistors
with an absolute value below the specified value are
shorted.
-max_res value Specifies the global upper threshold of the resistors from
the back-annotated DSPF/SPEF to be kept. All resistors
with an absolute value above the specified value are
treated as open-circuit.
-min_cap value Specifies the global lower threshold of the capacitors

from back-annotated DSPF/SPEF to be kept. All
capacitors with an absolute value below the specified
value are treated as open-circuit.
-report_trim_rlc Generates an .rlcignore file with the list of resistor,

enable_value capacitor, and inductor elements that have been
optimized. The default is 0.

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set_ba_option
Description
By default, the CustomSim tool uses load_ba_file for back-annotation. You can
use set_ba_option when you want to make adjustments to how the CustomSim
tool handles files to perform lumped capacitance back-annotation only, or when
you want to short out the SPF pins or apply the DPF scaling to the SPF files.
Note: This command now has the functionality of the

enable_ba_error_net command, which is now obsolete.
Supported Element Types

Table 5 lists the elements you can specify with the -dpf_elem_type option.
Table 5 Supported Element Types
Supported Element Keywords Expected To Match
mos m* or M*
diode d* or D*
resistor r* or R*
bjt (BJT) q* or Q*
capacitor c* or C*
instance (Xxxx macro- x* or X*

model)
Examples
Given the following vss net call:
*|NET vss 0.00924425PF
*|I (x04/mn:BULK x04/mn BULK B 0 20.15 8.55)
*|I (x02/mn:BULK x02/mn BULK B 0 22.75 1.05)
*|P (vss B 0 0.325 0.151)
*|P (vss_1 B 0 20.15 8.55)
*|P (vss_2 B 0 22.75 1.05)
The vss_1 and vss_2 pins are shorted to vss if set_ba_option

–short_pins 1 is applied.
set_ba_option -bus_delimiter < >

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set_bus_format
This command changes the bus delimiters in the SPEF file. For example:
xtop/xsram/xcol1/wl[0] becomes xtop/xsram/xcol1/wl<0>
xtop/xsram/xcol<1>/wl[0] becomes xtop/xsram/xcol<1>/wl<0>
xtop/xsram/xcol[1]/wl[0] becomes xtop/xsram/xcol<1>/wl<0>
set_ba_option -dpf_elem_type mos
Back-annotates only MOSFET DPF devices and ignores other devices in the
DPF section.
set_ba_option -dpf_elem_type mos resistor diode
Back-annotates only MOSFET/resistor/capacitors DPF devices and ignores

other devices in the DPF section.
set_ba_option -dpf_elem_type mos instance
Back-annotates only MOSFET and Xx instance DPF devices and ignores other
devices in the DPF section.
set_bus_format
Sets the bus delimiters.
Syntax
set_bus_format -open open_delimiter
[-close close_delimiter]
-open open_delimiter Specifies the opening delimiter character, for example,

[, <, _, or nothing (no open delimiter).
-close Specifies the close delimiter character, for example, ],

close_delimiter >, _ , or nothing (no close delimiter).
Description
You can specify two types of bus delimiters: both open delimiter and close
delimiter, or just the open delimiter. If you do not use a set_bus_format
command, by default the CustomSim tool uses [ ] as bus delimiters, for
example, a[0], a[1], a[2], and so on.

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Examples
set_bus_format -open < -close >
Specifies a<0>, a<1>, a<2>, and so on.

set_bus_format -open /
Specifies a/0, a/1,a/2, and so on.

set_bus_format -open -close ]
Specifies a0], a1], a2], and so on.

set_bus_format -open -close
Specifies a0, a1, a2, and so on.

set_bus_format -open #
Specifies a#0, a#1, a#2, and so on.
Lets you control capacitor handling at different phases of the simulation.
Syntax
set_capacitor_option -rule 1|2 [-min value]
[-report enable_value]
or
set_capacitor_option [-keep_negative_cap enable_value]

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-rule 1|2 Specifies one of the following optimization rules for

capacitor elements:
■
Specify a value of 1 to process (short or open based
on the elements) the capacitor elements at the
parsing stage, before the optimization and after
resolving the parameters. This rule does not save
elements in the database, which means you cannot
recover them during a simulation. It has the
advantage of using less memory. It is the default.
■
Specify a value of 2 to save the capacitor elements in
the database and process them during the
optimization. This rule has the advantage of
recovering capacitor elements for other analysis in the
simulation. However, this type of analysis can impact
the performance of the simulation.
Note that you can specify both rules in one simulation,
but only rule 1 can override rule 1, and rule 2 can override
rule 2. Because rule 1 is executed before rule 2, make
sure that you follow:
min(rule1) < min(rule2) and max(rule1) > max(rule2).
See Figure 3 or further details about specifying both
rules in the same simulation.
-min value Specifies the lower threshold value of the capacitors to

be kept. All capacitors with an absolute value above the
specified value are shorted by -rule argument.
-report Generates a .rlcignore file with the list of resistor,

enable_value inductor, and capacitor elements that were optimized.
The default is 0.
-keep_negative_cap Enables or disables the control for negative resistors for

enable_value a simulation. Negative resistor often comes from
parasitic extraction. The default is 1 to keep negative
capacitors (from both a netlist and back-annotation) for
optimization by the -rule, -min, and -max arguments.
If you want to disable negative capacitors for simulation,
you need to set this argument.
See Table 6 for information about the defaults for
handling capacitors.

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Description
Table 6 shows the defaults for handling schematic capacitors in a simulation.
Table 6 Defaults for handling capacitors
Netlist option=default set_sim_level=3 set_sim_level=7

Format through
set_sim_level=6
HSPICE RESMIN=1e-5 Keeps all capacitors. Keeps all capacitors.
Eldo RSMALL=1e-6 Keeps all capacitors. Keeps all capacitors.
Spectre rmin=0 Keeps all capacitors. Keeps all capacitors.
Back- min_cap=1e22 Specifies the following Same as

annotation defaults: set_sim_level=3
(DSPF or ■
If the minimum back- through
SPEF with annotation capacitance set_sim_level=6.
load_ba_f value is between -1e22
ile) and 1e22, those
capacitors are treated as
option-circuit by
set_ba_option.
Figure 2 shows the relationships between -rule 1 and -rule 2 in the

same simulation.
max(rule1) min(rule1) min(rule1) max(rule1)
0
(min of rule1) < (min of rule2) and (max of rule1) > (max of rule2) for positive resistors and capacitors
(min of rule1) > (min of rule2) and (max of rule1) < (max of rule2) for negative resistors and capacitors
Figure 2 Using -rule 1 and -rule 2 for capacitors in the same simulation

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set_ccap_level
See Also
load_ba_file
set_ba_option
set_inductor_option
set_resistor_option
set_ccap_level
Lets you override the default coupling capacitor tolerances.
Syntax
set_ccap_level -level ccap_level
-level Sets the level of the coupling effect. The ccap_level is an

ccap_level integer from 1 to 7, where 1 produces the fastest
simulation and 7 the most accurate. The default is the
level you specify using set_sim_level, or, if none was
specified, level 3. See Table 7 for details about each
level.
-inst Defines the instance name at which the ccap_level

inst_name applies.
{inst_name}
-subckt Defines the subcircuit name at which the ccap_level

subckt_name applies.
{subckt_name }
Description
During simulation, the CustomSim tool uses the default coupling capacitor
tolerances pre-set in each set_sim_level. You can use set_ccap_level to
override the default coupling capacitor tolerances. You can use this command
locally on specific instances or subcircuits.

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set_ccap_level
Table 7 provides guidelines for when to use set_ccap_level and what level
to choose.
Table 7 Guidelines for using set_ccap_level
Level Description
1 Specifies the most aggressive setting. All coupling capacitors

are split. No coupling effects are modeled at this level.
2 Specifies an aggressive setting. All coupling capacitors, except

those with both terminals that belong to the same resistive
network, are split to ground. Almost no coupling effects are
considered during simulation, in particular no inter-block
coupling effects are modeled.
3 Performs maximum optimizations of coupling capacitors. A

small amount of coupling effects in blocks propagating digital
signals and power distribution networks, and some coupling
effects in blocks propagating analog signals are modeled. This
level is suitable for functional verification or for simulation of only
the strongest coupling effects in digital, memory, low-sensitivity
analog, mixed-signal and full-chip circuits.
4 Performs moderate optimizations of coupling capacitors. It

models strong coupling effects, particularly in blocks
propagating analog signals. This level is suitable for functional
verification or for simulation of only the strongest coupling
effects in all circuits.
5 Performs balanced optimizations of coupling capacitors.

Coupling effects in both digital and analog circuits are
accurately modeled for all types of circuits. This level is suitable
for accurate timing and power simulation for all circuits with
coupling effects.
6 Performs conservative optimizations of coupling capacitors.

Detailed coupling effects are accurately modeled to provide
SPICE-like accuracy for all types of circuits. All circuits with
coupling effects would generate SPICE-like accuracy.
7 No coupling capacitor optimizations are performed. This level

yields full-SPICE accuracy.

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set_ccap_option
Note: In all cases, the set_ccap_level corresponds to the matching

level used by the set_sim_level command. That is, if you set
set_ccap_level to 3, the results are the same as if you had
set set_sim_level to 3.
Examples
set_sim_level 3
set_ccap_level 6
In this example, the CustomSim tool overrides the coupling capacitor

tolerances from 3 (set by set_sim_level) to level 6.
See Also
set_sim_level
set_ccap_option
Use this command with set_ccap_level to get maximum performance
simulating designs with many small coupling capacitors.
Syntax
set_ccap_option -ccap_to_gcap ccap_threshold_value
[-ccap_to_scap switch_value]
-ccap_to_gcap Converts all coupling capacitors to ground capacitors if

ccap_threshold the coupling capacitor value is smaller than the
_value ccap_threshold_value.
There is no default value for the
ccap_threshold_value. You must specifies a value
to perform the conversion.

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set_dc_option
-ccap_to_scap Converts all coupling capacitors to simplified capacitors.

switch_value The simplified capacitor is an approximated model that
allows partitioning across two regions previously
connected by the coupling capacitor.
The switch value can specify:
■
1 for a more efficient way of handling the capacitor
model.
■
2 for a more conservative way of handling the
capacitor model.
Description
The set_ccap_level command controls how the CustomSim tool handles the
coupling capacitors. In general, this command provides a good performance/
accuracy tradeoff. However, in designs with many small coupling capacitors,
especially from a large back-annotation file, set_ccap_level might not provide
enough tuning capability to get maximum performance. set_ccap_option
provides more advanced controls.
The set_ccap_option command splits small coupling capacitors to ground
capacitors before theset_ccap_level takes effect, so specify
set_ccap_option before you use set_ccap_level. The set_ccap_option
command converts small coupling capacitors prior to the RC optimization.
Examples
set_ccap_option -ccap_to_gcap 1e-18
Splits all coupling capacitors to ground capacitors if the couple capacitor value
is less than 1e-18.
set_ccap_option -ccap_to_scap 1
Splits all coupling capacitors to simplified capacitors.
set_dc_option
Controls DC convergence reporting.

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set_dc_option
Syntax
set_dc_option
[-method method_type [method_type ...]]
[-skip_dc value] [-cont_dc enable_value]
[-min_res min_res_value]
[-report report_type]
-report report_type
-method method_type Specifies one of the following method_type options:

auto is the default sequence that the CustomSim tool
uses to achieve DC convergence. The CustomSim tool
starts with the most aggressive method and, if DC
convergence is not achieved, goes to a more
conservative method in the following order: static ->
adaptive -> spice.
static partitions the circuit before solving the
operating point. It uses the switch level for its initial
estimate and the Newton Raphson iteration and
pseudo-tran approaches for single-matrix solving.
adaptive automatically adjusts the partition during the
solving stage for better DC convergence. When you
specify this method, the block size is often larger than
with the static method. It also uses a more robust
Newton Raphson iteration and pseudo-tran approach
for single-matrix solving.
spice is the most accurate DC method. It does not
partition and uses the Newton Raphson iteration and
pseudo-tran approaches for solving in one single matrix.
For more information about these options, see the note
in the Description section.
-skip_dc value Specifies one of the following values:

0 (default) uses the usual DC methods.
1 specifies to skip the DC evaluation and go straight to
transient analysis. Use this setting only for debugging
the IC file from another simulator imported in the
CustomSim tool for initial condition testing.

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set_dc_option
-cont_dc When DC does not converge, the CustomSim tool stops

enable_value and sets all the unsolved nodes to 0V and continues
with the transient simulation. This is the default behavior
of CustomSim DC when enable_value is off.
If enable_value is on, the CustomSim tool continues
solving the rest of the nodes at the last algorithm chosen
in the case of non-convergence and applies the initial
condition appropriately to the nodes. For example, when
–method static –cont_dc 1 is specified and the
CustomSim tool does not converge using the static
method, it continues solving the rest of the nodes using
the static method. And if -method static adaptive
–cont_dc 1 is used and the CustomSim tool does not
converge in both methods, the CustomSim tool
continues solving the rest of the nodes using adaptive
method.
See Common Syntax Definitions for more about
enable_value.
-min_res Without this argument, the DC solution keeps all the

min_res_value resistors when it solve the operating point. This
arguments tells DC processing to short small resistors
below the specified min_res_value. Note that this
argument does not have a default value.
This option only supports the static method of
-method.
[-report Specifies one of the following report_type options:

report_type] always specifies to always dump the DC convergence
report.
fail specifies to only dump the DC convergence report
when the DC operating point fails to converge (the
default).
off does not dump the DC convergence report.
Description
This command controls options related to the DC solver. You can use it to
output a DC convergence report to aid in debugging a DC convergence
problem. The report is written to a .dc0 file in the same directory as the other
simulator output files. The converged and non-converging nodes are listed in

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set_dc_option
separate sections together with the node voltage, delta-v, delta-I, and the
element contributing the largest current to the node.
You can also choose the DC method or skip DC analysis to go straight to
transient analysis.
Note: If you specify multiple options for the -method argument, the
CustomSim tool starts with the most aggressive DC method and
proceeds to more conservative DC methods if necessary to
achieve DC convergence. The following guidelines apply to the -
method options.
Table 8 How To Choose a DC Convergence Method
-method option Guideline
auto Specifies the method to let the CustomSim tool choose the DC
convergence method automatically.
static Specifies the method that provides the best performance for
most circuits of any size.
adaptive Specifies the method for medium sized analog or mixed-signal

circuits.
spice Specifies the most accurate DC method in the CustomSim

tool. It is not recommended for large circuits because of its
impact on performance.
If the spice method still does not provide DC convergence,
the CustomSim tool issues a non-DC convergence warning
and starts the transient analysis from the non-converged
operating point derived from this option.
Examples
set_dc_option –report always
Specifies to always dump the DC convergence report.

set_dc_option –method static
Specifies to use the static method for DC analysis.

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set_duplicate_rule
set_duplicate_rule
Lets you process multiple subcircuit definitions with the same name, multiple
ports in a subcircuit with the same port name, or multiple model definitions with
the same name.
Syntax
set_duplicate_rule -select_subckt select_value
[-subckt sub_name {sub_name}]
[-select_model select_value
[-model model_name {model_name}]
[-subckt_port enable_value]
-select_subckt Specifies if the select_value of the first or last

select_value subcircuit definition is used when duplicate definitions exist.
The default setting is 0, which raises an error if duplicate
subcircuit definitions exist.
-subckt Scopes the -select_subckt setting to only the named

sub_name subcircuit definitions.
{sub_name}
-select_model Specifies if the select_value of the first or last

select_value subcircuit definition is used when duplicate definitions exist.
The default setting is 0, which raises an error if duplicate model
definitions exist.
-model Scopes the -select_model setting to only the named model

model_name definitions.
{model_name}
-subckt_port If a subcircuit definition contains a duplicate port name, the

enable_value CustomSim tool raises an error unless this option is enabled. If
enabled, duplicate ports are shorted together.
Description
This command controls the simulator behavior when duplicate model or
subcircuit definitions are found in the netlist. It also controls the behavior when
duplicate subcircuit port names in exist in a subcircuit definition. A duplicate
model or subcircuit definition raises an error unless this command is used. It
can be used to specify if the first or last definition of a subcircuit or model is

H-2013.03
set_duplicate_rule
used and can be issued multiple times. The last command issued takes
precedence. As with other the CustomSim tool specifications, a global
command does not override a previously set local command.
Duplicate subcircuit port names are allowed by default in Eldo simulation mode.
In other netlist formats, duplicate subcircuit port definitions result in an error
unless you specify the -subckt_port argument to enable duplicate ports. All
duplicate ports are electrically shorted.
Examples
Example 25 Global Setting

set_duplicate_rule -select_subckt last
Specifies a global setting to select the last subcircuit.
Example 26 Global Precedence Setting

set_duplicate_rule -select_subckt first
Overrides all previous set_duplicate_rule commands and uses the first

subcircuit definition.
Example 27 Global and Local Precedence Setting

set_duplicate_rule -select_subckt first -subckt B
A global setting does not override a previously set local setting. In this example,
subcircuit B uses the first definition and the remaining duplicated subcircuits
use the last definition.
Example 28 Requesting Errors for Unexpected Duplicates

set_duplicate_rule -select_subckt last -subckt A B C
If a global setting is made, the CustomSim tool does not raise any parsing
errors for duplicated definitions. If only local settings are made the CustomSim
tool raise a parsing error for any other duplicate definition. If the netlist
contained:

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set_flash_option
.subckt A
*first a definition
...
.ends
.subckt A
*second A definition (expected)
...
.ends
.subckt D
...
.ends
.subckt D
* not intentional or expected
...
.ends
The CustomSim tool selects the last definition of subcircuit A, but raises an
error because subcircuit D has duplicate definitions.
set_flash_option
Sets options for the flash core cell.
Syntax
set_flash_option -delvto value
[-inst inst_name {inst_name}]|
[-subckt subcircuit_name {subcircuit_name}]
-delvto value Specifies the change in threshold voltage.
-inst inst_name Selects flash cells to be initialized. Wildcards can be used

{inst_name} in the inst_name.
-subckt Selects flash cells for initialization by subcircuit name.

subcircuit_name
{subcircuit_name}

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set_floating_node
Description
This command specifies the initial change in threshold voltage to be applied to
flash cells. If -inst or -subckt is not used to specify specific instances the
command applies to all flash cells in the netlist. A delvto setting applied by
this command overrides the instance parameter delvto for a flash cell.
Examples
set_flash_option -delvto -0.5
Sets an initial vth change of -0.5V on all flash cells in the netlist.
set_flash_option -delvto 2 -inst x1.x2.x3.mcell
Sets an initial vth change of +2V on the x1.x2.x3.mcell flash cell.

set_flash_option -delvto -1.5 -subckt memword_16
Sets an initial vth change of -1.5V on all flash cells in all memword_16
instances of the subcircuit.
set_floating_node
Sets the voltage value of floating nodes at the DC operating point or throughout
the transient simulation.
Syntax
set_floating_node -val value [-type gate|all]
[-format ic|vsrc] [-outfile enable_value]
-val value Specifies a voltage value applied to the floating nodes.
-type gate | all Specifies one of the following options:

gate – Sets floating gates
all – Sets all floating nodes (default)

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set_floating_node
-format ic | vsrc Specifies one of the following options:

ic – Initializes floating nodes with the value (default)
vsrc – Sets floating nodes to the value throughout the

simulation. Using this option is equivalent to applying
voltage sources of value to the floating nodes.
-outfile enable_value Enables (1, on) or disables (0, off) creation of an

output file. See Common Syntax Definitions for more
about the enable_value. The filename is the output
filename specified with the -o option when invoking
the CustomSim tool (or the input filename, if -o was
not specified). The file extension is .fnode. If you
create an output file and set -format ic, the
CustomSim tool saves output data in the form of .ic
statements; if -format vsrc, the CustomSim tool
saves output data in the form of voltage sources. You
can modify the output file to include it into the
simulation.
Description
Behavior of floating nodes can vary considerably with simulation algorithms
and models. In a few cases, simulation results for a critical part of a circuit can
depend on the voltage value at one or more floating nodes in the circuit. This
can lead to hard-to-detect design issues and cause different results from
different simulators. Forcing such nodes to a known value by means of
set_floating_node can help isolate design problems.
Examples
Example 29 initializes all floating nodes at 0v in OP. No output file is generated.
Example 29
set_floating_node 0 -type all -format ic
Example 30 sets all floating gates to 3.3v throughout the simulation. the
CustomSim tool prints an output file with an extension .fnode0, containing data
in the form of voltage sources.
Example 30
set_floating_node 3.3 -type gate -format vsrc -outfile 1

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set_hotspot_option
set_hotspot_option
Controls which nodes are reported by check_node_hotspot.
Syntax
set_hotspot_option -factor value
-factor value Specifies the value used in the calculation to

determine which nodes are reported by the
check_node_hotspot command. The default is 0.5.
Description
Nodes specified by the check_node_hotspot command are not reported when
the sum of the capacitive charging and discharging currents is less than the
value multiplied by the sum of the node with the largest capacitive currents.
Examples
check_node_hotspot –node *
set_hotspot_option –factor 0.3
These commands enable hot spot checks on all nodes, but only report the
nodes for which the sum of the capacitive charging and discharging current is
more than 0.3 multiplied by the sum of the node with the largest capacitive
current. The following example shows the format of the output file.
Node Name Cap(fF) Toggle Icin(uA) Icout(uA)
_______________________________________________________________
VDD 3.03e+05 0 1.825 3.187
_GND 2.646e+04 0 2.047 2.159
SAMPLINGA 307.1 6 1.553 1.562
Total non-input nodes : 791

Total node toggles : 392
Total charging current : 18.87uA
Total discharging current : 19.46uA
set_inductor_option
Lets you control inductor handling at different phases of the simulation.

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set_inductor_option
Syntax
set_inductor_option -rule 1|2 [-min value]

inductor elements:
■
Specify a value of 1 to process (short or open based
on the elements) the inductor elements at the parsing
stage, before the optimization and after resolving the
parameters. This rule does not save elements in the
database, which means you cannot recover them
during a simulation. It has the advantage of using less
memory. It is the default.
■
2 to save the inductor elements in the database and
process them during the optimization. This rule has
the advantage of recovering inductor elements for
other analysis in the simulation. However, this type of
analysis can impact the performance of the
simulation.
-min value Specifies the lower threshold value of the inductors to be

kept. All inductors below the specified value are shorted
by -rule argument.

The default is 0.
Description
Table 9 shows the defaults for handling schematic inductors in a simulation.
Table 9 Defaults for handling inductors

Format through
set_sim_level=6
HSPICE RESMIN=1e-5 Keeps all inductors. Keeps all inductors.
Eldo RSMALL=1e-6 Keeps all inductors. Keeps all inductors.
Spectre rmin=0 Keeps all inductors. Keeps all inductors.

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set_logic_threshold
Table 9 Defaults for handling inductors

Format through
set_sim_level=6
Back- - Keeps all inductors. Same as

annotation set_sim_level=3
(DSPF or through
SPEF with set_sim_level=6.
load_ba_f
ile)
See Also
set_resistor_option
set_logic_threshold
Specifies a default logic high/low threshold value.
Syntax
set_logic_threshold -loth low_threshold_value
-hith high_threshold_value [-node node_names]
[-event_type value]
-loth Sets the logic low threshold value. The default unit is
low_threshold_value Volt.
-hith Sets the logic high threshold value. The default unit is
high_threshold_value Volt.
-node node_names Specifies the node names to apply the threshold value.
If this argument is not used, the default is all nodes. A
wildcard is supported. You can specify multiple nodes
separated by spaces.

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set_measure_format
-event_type value Determines when a node generates a digital event.

When value is set to 0 (the default), a node generates
a digital event when its voltage rise above, or falls
bellow, the middle voltage, such as 0.5*(high_voltage
+ low_voltage). This setting is suitable to simulate
most circuits.
When value is set to 1, a node generates a digital
event for a node when its voltage rises above
high_threshold_value or falls below its
low_threshold_value. With this setting, the digital
event is generated later than the one with the default
setting.
Description
The node state is determined by the relationship between its voltage and the
high/low logic threshold value:
■ If a node voltage is equal to or larger than the high_threshold_value, its state
is ONE.
■
If the node voltage is between the high_threshold_value and
low_threshold_value, its state is undefined (U-state).
■
If a percentage sign (%) is applied to the high_threshold_value and
low_threshold_value arguments, a percentage value of the high/low voltage
is taken, rather than taking the absolute value.
When the set_logic_threshold command is not used, the default
high_threshold_value and low_threshold_value are 70% and 30%,
respectively.
set_measure_format
Sets the .measure file output format. If this command is not used, the default
.measure file output uses CustomSim formatting.
Syntax
set_measure_format -format hspice|xa -bisect_meas final|all

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set_message_option
-format Specify hspice for *.mt output format (for HSPICE

hspice|xa formatting) or xa for *.meas output format (for CustomSim
formatting).
-bisect_meas final is the default and means the CustomSim tool only
final|all writes the .measure results of the bisection iteration (transient
simulation) that meets the goal of the bisection process. all
outputs the .measure results for each iteration of the
bisection process. This is useful for debugging the bisection
process/results.
Examples
set_measure_format -format hspice
set_message_option
Controls the number of warning messages the CustomSim tool prints.
Syntax
set_message_option -limit lim_val
or
set_message_option -action warn|stop|exit
or
set_message_option -pattern pat {pat} -limit lim_val
or
set_message_option -pattern pat {pat} -action warn|stop|exit
or
set_message_option -pattern pat {pat} -limit lim_val
-action warn|stop|exit
or
set_message_option -limit lim_val -action warn|stop|exit

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set_message_option
-limit lim_val Limits the maximum number of error messages to print.

The default is 10.
-action Specifies one of the following options:

warn|exit|stop ■ warn (the default) to output warnings and continue the
simulation.
■ exit to exit the simulation if a warning message is
encountered.
■
stop to pause the simulation and prompt to either
continue or exit.
If you specify exit or stop, the action takes place on any
occurrence of the warnings specified with -pattern or
any warning if no -pattern is specified.
-pattern pat {pat} If you specify a pattern, the settings of the current
command instance apply only to the specified warning
message. If the pattern contains white spaces, it needs to
be enclosed with a grouping delimiter, double quotes ("") or
braces ({}). You can specify multiple patterns.
Description
If you specify only the -limit argument, the CustomSim tool prints the
specified number of warning messages for every warning type. If you specify
both the -limit and -pattern arguments, the CustomSim tool prints the
specified number of messages that match the specified pattern. By default, the
messages that do not match the pattern are printed 10 times.
If you specify both the -pattern and -action arguments, the CustomSim
tool applies the action when the specified pattern is matched in a warning
message: either continue, exit, or pause the simulation.
Important: It is recommended that the set_message_option

command be used inside the command file included with
the -c command line option.
Examples
In Example 31, when the CustomSim tool finds an ignored option or command,
it stops the simulation and exits.
Example 31
set_message_option -pattern "Option/Command ignored" -action exit

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set_model_level
In Example 32, for any warning that contains the "floating" or "not matched"
patterns, the CustomSim tool stops and exits the simulation.
Example 32
set_message_option -pattern "floating" -action exit
set_message_option -pattern "not matched" -action exit
In Example 10, the CustomSim tool reports up to 100 warnings for the "Option/
Command ignored" pattern and stops and exits the simulation if any messages
contains the "floating" pattern.
Example 33
set_message_option -limit 100 -pattern "Option/Command ignored"
set_message_option -pattern "Floating" -action exit
In Example 34, the CustomSim tool stops the simulation if it finds the "forward
biased" or "exceeding" patterns. It displays the following prompt:
Message with stop action has been met. Do you want to exit
the simulation? [y|n]
Example 34
set_message_option -pattern "forward biased" "exceeding" -action
stop
In Example 35, the CustomSim tool will tabulate and print at most 50
occurrences of warnings containing the pattern "unsupported" and then
exit with an error.
Example 35
set_message_option -limit 50 -pattern "unsupported" -action exit.
set_model_level
Overrides the automatic choice of table model or equation used for each
set_sim_level command. This command provides the arguments to either
choose the type of model used for other set_sim_level settings or override it
with a specific type of model.

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set_model_level
Syntax
set_model_level -level model_level
[-type model_type]
[-force 0|1]
-level model_level Specifies an integer value of 1 through 7, which

corresponds to a set_sim_level value.
-inst instance_name Specifies instance names.

{instance_name}
-subckt subcircuit_name Specifies subcircuit names.

{subcircuit_name}
-type model_type Overrides the automatic model choice with a specific

model specified by type. The type can be digital,
analog, or equation. If you specify a less
accurate type of model than the automatic model
choice, the automatic model choice has precedence
over your specification (unless you specify -force
1).
■ digital sets both the MOSFET current and
charge model to fast table.
■ analog sets both the MOSFET current and
charge model to table.
■
equation sets both the MOSFET current and
charge model to equation.
-force 0|1 This option is only valid when you use -type. If you
specify-force 1, CustomSim forces all MOSFETs
to use the specific type of model specified with -
type.
Description
By default, XA chooses the type of table model or equation used for each
set_sim_level command. set_model_level overrides the automatic choice
of table model or equation used for each set_sim_level. It either chooses the
type of model used for other set_sim_level commands or overrides it with a
specific type of model.

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set_model_option
Examples
set_sim_level 3
set_model_level 5
Overrides the model strategy of level 3 with level 5. All other strategies remain
as level 3.
set_sim_level 4
set_model_level -type analog
Overrides the model strategy of level 4 to promote digital table to analog

(dynamic) table. If some MOSFETs use equation model, they are simulated
using equation model.
set_sim_level 4
set_model_level -type analog -force 1
Overrides the model strategy of level 4 to force all the MOSFETs to use analog
(dynamic) table.
set_model_option
Controls the type of model, the enhanced table feature, the BSIM4 NQS
feature, the grid, MOS binning, and model parameter checking.
Syntax
set_model_option model_spec [-grid value]
[-grid_scale scale] [instance_spec]
where
model_spec ::= current_spec|charge_spec|stress_param_spec|
b4nqs_model|binning_spec|model_param_check_spec
instance_spec ::= [-inst inst_name {inst_name}]
where
current_spec::= -current current_model | -i current_model
charge_spec ::= -charge charge_model | -q charge_model
stress_param_spec ::= -lod lod_value|-wpe wpe_value
b4nqs_model ::= -b4nqs b4nqs_value
binning_spec ::= -mos_bin_ratio tolerance
model_param_check_spec ::= -model_param_check check_value

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set_model_option
where
current_model ::= full|table| ids|fast|none
charge_model ::= full|table| fast|lump|none
-current Specify one of the following keywords to override the

current_model-i automatic choice for the current model:
current_model ■
full for a MOS equation current model with no
optimization.
■
table for a dynamic table built for each current in the
MOS model.
■
ids for a dynamic table built only for drain-source
current (ids) for a MOS model.
■
fast for a static table used for the current in a MOS
model.
-charge Specify one of the following keywords to override the

charge_model-q automatic choice for the charge model:
charge_model ■
full for a MOS equation charge model with no
optimization.
■ table for a dynamic table built for all the charge
components in the MOS model.
■ fast for a static table used for all the charge
components in a MOS model.
■ lump for approximate lump capacitors used for a MOS:
Cgate, Csource, and Cdrain.
-b4nqs b4nqs_value Disables or ignores (0) b4nqs effects. Specify 1 (default) to

invoke the b4nqs model.
-wpe -lod Disables or ignores STI/LOD (for -lod) or WPE (for -wpe)
-0 | off effects.
-wpe -lod Uses look-up tables, obtained from device equations, to

1 | on handle stress effects. This is the default. See the
Description section below for more details.
-wpe -lod Uses an enhanced table model method, which uses a

2 single base look-up table, to handle stress effects. See the
Description section below for more details.

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set_model_option
-mos_bin_ratio Specifies the ratio tolerance for binning the MOS model. It
tolerance is an integer value between 0 and 500 and must always be
followed by a percent sign (%). The default is 0.
Post-layout simulations use extracted netlists with final
sizes for devices. The final sizes extracted from layout are
slightly different from the schematic sizes, so devices with
the same size in pre-layout (or schematic) netlist have
slightly different sizes in the post-layout netlist. The
difference is same but results in many devices each having
its own size parameters. As a consequence, the
CustomSim tool generates a large number of unique
models, which can increase the memory usage and run
time.
The purpose of this option is to create fewer models and
improve the memory usage and run time for post-layout
simulations. All devices with parameters that differ by less
than a given ratio share the same model. All parameters
are assumed to have the same importance and the same
ratio is used for all parameters.
-grid grid_value Sets the absolute LUT grid size in volts. You can only
specify this option globally.
-grid_scale scale Multiplies the grid sized determined by the CustomSim

tool. You can only specify this option globally.
-model_param_check This option is equivalent to the HSPICE option .option

check_value MODPARCHK. Use this option to determine whether a
simulation aborts when it encounters fatal errors in model
side parameter checking. When set to 1 (default), the
simulation aborts if it encounters a fatal error during
parameter checking and reports the error. When set to 0, it
checks limited model parameters and re-sets them to avoid
fatal errors and the simulation runs to conclusion. Note that
this option is only available for BSIM4 models.
-inst Specifies the instance names.

instance_name
{instance_name}

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set_model_option
-subckt Specifies the subcircuit names.

subcircuit_name
{subcircuit_name}
Description
The CustomSim tool automatically chooses the appropriate current and charge
model. You can overwrite this automatic selection and take the following stress
effects into consideration:
■
Shallow trench isolation (STI), a compact way of separating transistors for
submicron geometries.
■ Length of oxide definition (LOD), a measure of transistor layout sizing, used
to modify device characteristics due to submicron effects.
■
Well proximity effect (WPE), a measure of device degradation due to
closeness of the transistor well or body to the transistor itself.
By default, the CustomSim tool builds a unique model (either an equation level
model or a look-up table model) for each unique transistor geometry. A different
model is required for a transistor even if the dimensions are the same as
another transistor, differing only in the STI/LOD/WPE value. In this way, the
CustomSim tool preserves all STI/LOD/WPE effects.
The CustomSim tool enables turning off the BSIM4 NQS parameter, if
TRNQSMOD=1, without modifying the model file, to see if performance is
impacted by using this parameter.
The CustomSim tool can also use an enhanced table model method, applied
for a given transistor dimension. This model uses derating factors to account for
STI/LOD/WPE effects during simulation. The algorithm provides performance
and memory capacity advantages with minimal loss of accuracy.
You set the -lod and -wpe values to 0 or off to ignore STI/LOD/WPE effects,
to 1 or on (default) to use preserve all stress effects, and to 2 to use the
enhanced table model method.
The CustomSim tool can also:

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■
Control binning of MOS devices whose parameters fall within a given
percent ratio of one another.
■ Automatically choose the appropriate grid and grid scale. You can overwrite
this automatic selection.
■
Abort or continue when fatal model parameter checking errors occur.
Note: This command replaces the use_mos_instpar and

set_mos_binning commands.
Examples
The following example uses the full current model and full charge model.
set_model_option -i full -q full
The following example turns off the BSIM4 NQS parameter.

set_model_option -b4nqs 0
The following example uses the enhanced look-up table for all effects.
set_model_option -lod 2 -wpe 2
The following example uses the mos binning ratio feature set to 10%.
set_model_option -mos_bin_ratio 10%
The following example uses the grid and grid_scale feature, set to 0.01V and
0.5, respectively.
set_model_option -grid 0.01
set_model_option -grid_scale 0.5
The following example uses the model parameter checking feature, set to 0 for
the simulation to continue with .reset model parameters that are fatal.
set_model_option -model_param_check 0
Specifies how to run traditional Monte Carlo analysis for transient simulation.

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Syntax
set_monte_carlo_option [-enable enable_value]
[-sample_output output_files]
[-parameter_file enable_value]
[-simulate_nominal enable_value]
[-dump_waveform enable_value]
-enable The default setting for this option is enabled and must be
enable_value set to process monte carlo samples. If this option is
disabled and the netlist contains a sweep monte
statement, the sweep monte statement is ignored with a
warning.
-sample_output Specifies which Monte Carlo output files to keep:

output_files ■
first keeps the output file from the first Monte Carlo
run.
■ all keeps all the Monte Carlo output files from all runs.
■
last keeps the output file from last Monte Carlo run.
■ none specifies not to keep any output files. This is the
default setting.
■ n {n} keeps the Monte Carlo output files from the
specified runs.
-parameter_file If you enable this option it creates a .mc_params

enable_value parameter file.
-simulate_nominal By default, this option is enabled and runs the nominal, 0

enable_value sweep simulation. If you disable it, the CustomSim tool
does not run the 0 sweep simulation and starts with the first
sweep (1).
-dump_waveform You must enable this option to dump waveforms. It dumps

enable_value only the waveform files for those samples you specify with
the -sample_output option.
Description
You can run Monte Carlo analysis as an additional check to ensure that your
design functions as expected. The CustomSim tool only supports traditional
Monte Carlo analysis for transient simulations with the HSPICE netlist format.
For more information about traditional Monte Carlo analysis, see the Monte
Carlo - Traditional Flow and Statistical Analysis section in the HSPICE User

H-2013.03
Guide: Simulation and Analysis.

Traditional Monte Carlo defines a random variable with a distribution function.
You can assign a random variable just as in HSPICE. The CustomSim tool
supports the same distribution functions as HSPICE:
■
UNIF(nominal_val, rel_variation [, multiplier])
■
AUNIF(nominal_val, abs_variation [, multiplier])
■
GAUSS(nominal_val, rel_variation, num_sigmas [, multiplier])
■
AGAUSS(nominal_val, abs_variation, num_sigmas [, multiplier])
■
LIMIT(nominal_val, abs_variation)
Whenever a parameter defined by one of these functions is assigned, a new
unique random variable is generated. For more information distribution
functions, see the .PARAMETER Distribution Function section in the HSPICE
User Guide: Simulation and Analysis.
The .mc file contains a measurement summary of the Monte Carlo simulation.
It is the primary output file and reports a summary of the statistical data for
each measurement:
■
nominal
■
mean
■
variance
■
stddev
■
avgdev
■
min
■
max
■ median
■
sample number of min
■ sample number of max
■
sample number of median
■
10 bin horizontal ascii histogram:
• First column of the histogram is the bin center point.
• Second column, nb, reports the number of samples in the bin.
• Third column, freq, reports the percentage of samples in the bin.

H-2013.03
Table 10 Generated Waveform Files
-sample_output -dump_waveform Output File Format Output Waveform File

setting setting
none 0 Any No waveform file.
none 1 Any No waveform file.
all 0 Any No waveform file.
all 1 Any xa.m0.format

xa.m1.format
xa.m2.format
...
xa.mn.format
0,10 0 Any No waveform file.
0,10 1 Any xa.m0.format

xa.m10.format
Table 11 Monte Carlo Output Files
File Name Description
.mc Contains the Monte Carlo measurement summary of all

measurements and an ASCII histogram of each
measurement. Monte Carlo analysis always produces
this file.
.mc.csv Contains all of the data in the .mc file, except the
histogram. You can read this .csv file in a spreadsheet
program.

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Table 11 Monte Carlo Output Files
File Name Description
.meas/.mt Contains all the Monte Carlo sample measurement

results. Monte Carlo analysis always produces this file. It
contain only the measure values, not the Monte Carlo
parameter values.
This file uses standard CustomSim measure formatting
and has a .meas extension. If you specify HSPICE
formatting in the set_measure_format command, it has a
.mt extension.
When you specify set_measure_format -format
hspice, the CustomSim tool must create a measure file
that is syntactically compatible with HSPICE so that a
waveview histogram can be viewed. When you choose
the HSPICE measure format, the per sample and
summary measure file has a .mt extension rather than
the standard .meas extension.
.mc_params The .mc_params file is a listing of all of the random

variable values used in the simulation. It is equivalent to
the HSPICE .mct0 file. The default file format is the
CustomSim measure file format. You can choose an
HSPICE file format with the set_measure_format
command.
Monte Carlo analysis generates the following output files on a per Monte Carlo
sample basis if you specify -sample_output:
.m#.wdf/fsdb/wdb/out Waveform output file.
.m#.meas/mt Measure file with a .meas extension when you specify

the standard CustomSim measure format, or a .mt
extension if you specify the HSPICE measure format with
the set_measure_format command.
.m#.ic Initial conditions file (if requested).

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Examples
Example 36 Running Monte Carlo Analysis

.tran 1n 100n sweep Monte=2
.opt xa_cmd="set_Monte_Carlo_option -sample_output all"
This example creates the following output files:

■
xa.log
■
xa.mc
■
xa.meas
■
Sample 0 files (nominal simulation)
• xa.m0.wdf
• xa.m0.meas
• xa.m0.ic
■
Sample 1 files (first random set)
• xa.m1.wdf
• xa.m1.meas
• xa.m1.ic
■
Sample 2 files (second random set)
• xa.m2.wdf
• xa.m2.meas
• xa.m2.ic

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Example 37 .mc File Example

* XA 64-bit LINUX D-2010.03-20100316 (built 17:04:04 Mar 16 2010)
* Build id: 1762407
* Copyright (C) 2010 Synopsys Inc. All rights reserved.
meas_variable = out
nominal = 0.000000e+00
mean = 8.228455e-05
varian = 5.832803e-08
stddev = 2.415120e-04
avgdev = 1.893783e-04
min = -1.568056e-04
max = 6.508503e-04
median = 3.212345e-04
run_min = 4
run_max = 8
run_median = 7
-7.603999e-05, nb = 2, freq = 2.000000e-01 |**********

4.725601e-06, nb = 4, freq = 4.000000e-01 |****************
8.549119e-05, nb = 0, freq = 0.000000e+00 |
1.662568e-04, nb = 2, freq = 2.000000e-01 |**********
2.470224e-04, nb = 0, freq = 0.000000e+00 |
3.277879e-04, nb = 1, freq = 1.000000e-01 |*****
4.085535e-04, nb = 0, freq = 0.000000e+00 |
4.893191e-04, nb = 0, freq = 0.000000e+00 |
5.700847e-04, nb = 0, freq = 0.000000e+00 |
6.508503e-04, nb = 1, freq = 1.000000e-01 |*****
The .mc_csv file in Example 38 contains the same data as the .mc file, except
for the ASCII histogram. It has CSV formatting. The first line is a header row:
Example 38 .mc_cvs File
meas_variable,nominal,mean,varian,stddev,avgdev,min,max,…
out,0.000000e+00,8.228455e-05,5.832803e-08,…

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set_multi_core
The .meas file in Example 39 is the standard CustomSim measure file. It

contains all the per sample measurement values. For example:
Example 39 .meas File
*
* XA 32-bit LINUX D-2010.03-SP1-ENG2 (built 14:07:40 Jul 19 2010)
* Build id: 1833524
* Copyright (C) 2010 Synopsys Inc. All rights reserved.
*
mc_index = 1
rt = 8.7888150e-12 targ = 1.5616071e-09 trig =

1.5528183e-09
dly = 3.4741727e-10 targ = 5.7741727e-10 trig =
2.3000000e-10
temper = 1.2500000e+02
alter# = 1.0000000e+00
set_multi_core
Runs a multicore simulation.
Syntax
set_multi_core [-core num_cores] [-check_model value]
[-check_netlist value]
-core num_cores Specifies the number of cores to use with either a

numerical value of 2 or more or the max keyword. The
number of cores requested is automatically adjusted
to the maximum available in the machine.
The max keyword specifies to use maximum number
of cores available in the machine. Note that you need
1 CustomSim licence per each 2 cores.

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set_multi_core
-check_model value Lets you check for non-thread-safe and thread-safe

models with one of the following values:
■ 0 does not perform the check (default).
■
1 checks to see if thread-safe models are internally
tagged as such and causes the CustomSim tool to
error out if the models are not tagged properly.
■
2 reports internally tagged non-thread-safe models
with a warning.
■
3 combines 1 and 2.
-check_netlist value Helps you determine whether a netlist is a good

candidate for a multicore simulation. If you enabled a
multicore simulation already, this option is ignored.
Otherwise one of following three messages is dumped
in *.log file:
This netlist is likely to benefit from a multicore
simulation.
This netlist can possibly benefit from a multicore
simulation.
This netlist is unlikely to benefit from a multicore
simulation.
■ 0 does not perform the check (default).
■
1 checks the netlist, dumps the result in the log file,
and continues the simulation.
■
2 checks the netlist, dumps the result in the log file,
and stops the simulation.
Examples
set_multi_core -core 4
Runs a multicore simulation with four cores.

set_multi_core -check_netlist 2
Reports the multicore check results and stops the simulation.

set_multi_core -check_model 1
Checks if models are internally tagged as thread-safe and errors out if they are
not tagged as thread-safe.

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Enables the multi-rate technology mode.
Syntax
set_multi_rate_option -mode 1|2
-mode 1|2 The default is 2. The recommended setting of 2

enables the new multi-rate technology that can
provide enhanced simulator performance and
precision, particularly in digital designs. The value of
1 is available to maintain backward compatibility with
the 2012.06 multi-rate algorithms.
set_oscillator
Applies the trapezoidal integration method to oscillator circuits.
Syntax
set_oscillator -inst inst_name|-subckt subckt_name
[-disable value] [-report value]
-inst inst_name Specifies an instance as an LC oscillator.
-subckt Specifies a subcircuit definition as an LC oscillator.

subckt_name
-disable value Specifies a value of 1 to disable automatic detection of

oscillator circuits. This option applies globally. You cannot use
it to disable detection of instances or subcircuits. The default
is 0.
-report value Specifies a value of 1 to output additional log information.

When automatic detection is on, all detected elements are
listed in the log. The default is 0.

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set_oscillator
Description
Trapezoidal integration is often the best integration method for LC oscillator
circuits but can apply to other types of oscillators as well. If the characteristic
frequency on an inductive network is between 0.5Hz and 800 MHz, an
oscillator circuit is often identified automatically. Because the capacitors in an
LC oscillator have a critical impact on the oscillation frequency, this command
causes conservative treatment of the capacitors in the oscillator.
If the CustomSim tool fails to identify an oscillator automatically, you can use
the set_oscillator command to manually specify the trapezoidal
integration method. Trapezoidal integration is also applied to the regions
(partitions) that contain the designated oscillators. You can also use this
command for other circuit elements that require trapezoidal integration.
In a hierarchical netlist, apply trapezoidal integration to the inductor of the
oscillator or the lowest-level subcircuit that contains the oscillator. In a flat
netlist, apply it to the inductor.
Note: If you do not specify -subckt or -inst, the CustomSim tool

issues a warning and does not apply trapezoidal integration to
any instance. If automatic detection is enabled, the CustomSim
tool still applies trapezoidal integration to any detected
oscillators.
Examples
The following example applies the trapezoidal integration method to an inductor
instance.
Example 40
set_oscillator -inst x1.xosc.L1
The following example applies the trapezoidal integration method to an

oscillator instance.
Example 41
set_oscillator -inst x1.xxtal
The following example applies the trapezoidal integration method to all

instances of a subcircuit.
Example 42
set_oscillator -subckt crystal

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The following example disables automatic detection of LC oscillator circuits.

Example 43
set_oscillator -disable 1
The following example prints additional log information.

Example 44
set_oscillator -report 1
The following example disables automatic detection and applies the trapezoidal
integration method to the specified instance.
Example 45
set_oscillator -inst xxtal -disable 1
Overrides the automatic setting for circuit partitioning.
Syntax
set_partition_option -sp enable_value [-ap enable_value]
[-print_power enable_value]
[[-rule] gate|channel|never]]
[-subckt subckt_name {subckt_name }]
-sp enable_value Turns static partitioning on (1, the default) or off (0).
Static partitioning is not instance specific and does
not affect the idealized power-net block region.
-ap enable_value Turns advanced partitioning on (1, the default) or off

(0). Advanced partitioning is not instance specific.
-print_power Writes a list of power cut nodes to the .cut file.

enable_value

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-rule gate|never Allows partitioning of MOSFETs at the gate (high-

impedance) terminal. The node touching the gate of
the MOSFET is in a different partition than the
source/drain terminals. If it is set to a Verilog-A
instance, it allows partitioning of the ports of Verilog-
A instance. The nodes touching the high-impedance
ports of the Verilog-A instance are in different
partitions, but the Verilog-A instance is still in one
partition. Note that this option only allows the device
to be partitioned, but does not guarantee it. The
partitioning rules of surrounding devices can cause
the device to remain un-partitioned in spite of the
gate rule being applied to it. Specify channel to
allow partitioning of MOSFETs at the channel (low-
impedance) terminal.
never turns off the partitioning. The nodes touching
the MOSFET are in one partition.
-inst inst_name Applies the partition rule defined by -rule to the

{inst_name} specified instances.
-subckt subckt_name Applies the partitioning rule defined by -rule to the

{subckt_name } specified subcircuits.
Description
You can use the set_partition_option command to enable/disable the
CustomSim tool partitioning algorithms. The CustomSim tool has two stages of
partitioning: static partitioning and advanced partitioning. The static partitioning
algorithm uses mature circuit heuristics to perform partitioning. The advanced
partitioning algorithm uses more aggressive partitioning methods to try to
further reduce partition sizes.
If -sp 0 is set all partitioning is disabled and the -ap setting is ignored. You
can disable the advanced partitioning with -ap 0 to isolate partitioning issues
or to assist in tightening simulation accuracy at a cost of simulation run time.
Disabling static partitioning disables all circuit partitioning in the CustomSim
tool. This is not recommended for large circuits because of the prohibitive
simulation runtime.
Examples
set_partition_option -ap 0

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set_powernet_level
set_powernet_level
Controls the performance/accuracy tradeoff for IR drop simulation.
Syntax
set_powernet_level -level level_value
-level Specifies the performance/accuracy tradeoff level for IR drop

level_value simulation. The default is the level you specify with the
set_sim_level command. Levels 3 through 7 are valid. If you
do not specify a set_sim_level command, the default value is
3.
Description
The higher the set_powernet_level, the more parasitic elements are taken
into consideration for IR drop simulation. If the resistor connected to the power
supply is below the predetermined value for each set_sim_level, the resistor is
not taken into consideration for IR drop simulation.
The CustomSim tool automatically adjusts the resistance value based on the
simulation strategy. You can override the automatically chosen idealized power-
net strategy to meet your accuracy requirements, especially for IR-drop
simulations. The smaller the value, the better the accuracy for IR-drop
simulations.
The main usage for the set_powernet_level command is to use it along
with set_sim_level to speed up the IR drop simulation. Set set_sim_level
command based on the circuit types (see Table 12) and use a higher
set_powernet_level to override the pre-determined resistance value of
set_sim_level. Otherwise, the resistance value of set_powernet_level by
default matches the levels by set_sim_level. For a more detailed IR drop
simulation, set a higher set_powernet_level to take more parasitic
resistors connected to an idealized power-net block for simulation.
Table 12 Guidelines for Appropriate Circuit Types for Each set_sim_level
Level Digital Memory Low-Sensitivity High-Sensitivity Mixed-Signal Full-Chip

Analog Analog
7 X X X X

H-2013.03
set_powernet_option
Table 12 Guidelines for Appropriate Circuit Types for Each set_sim_level
Level Digital Memory Low-Sensitivity High-Sensitivity Mixed-Signal Full-Chip

Analog Analog
6 X X X X X X
5 X X X X X X
4 X X X X X X
3 X X X X X
Examples
set_sim_level 3
set_powernet_level 6
In the previous example, the CustomSim tool overrides only the idealized
power-net resistor tolerances used in set_sim_level 3 with the tolerances used
in set_sim_level 6. All resistors connected to power supply with values larger or
equal to 1 ohm are taken into the simulation. set_sim_level 3 is suitable for IR
drop simulation for digital, memory or low-sensitivity analog designs.
set_powernet_option
Controls how resistors are partitioned into the idealized power-net block.
Syntax
set_powernet_option -ideal_rmax res_value
[-collapse_node node {node}]
[-id enable_value]
res_value Specifies the maximum resistance value of the resistor to be

partitioned into the idealized power-net block.
-collapse_node Collapses the resistor network to the specified node name.

node {node}
-id enable_value Enables advanced power net identification. The default is off.

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set_probe_option
Description
This command controls how resistors are partitioned into the idealized power-
net block. Power-net elements and nodes connected to ground through low-
impedance elements (such as voltage sources and resistors smaller than the
specified value) are put into the idealized power-net block. Table 13 shows the
defaults used at the different accuracy levels.
Table 13 Default set_powernet_option Values
Accuracy Level Default set_powernet_option resistance value
set_sim_level 3 10 ohms
set_sim_level 4 7.5 ohms
set_sim_level 7 1e-5 ohms
In some cases the CustomSim tool might automatically adjust the resistance
value based on the simulation strategy. You can override the automatically
chosen idealized power-net strategy to meet your accuracy requirements,
especially for IR-drop simulations. The smaller the value, the better the
accuracy for IR-drop simulations.
set_probe_option
Controls probing options.
Syntax
set_probe_option -probe_undefined_node enable_value
[-variable_separator separator_char]
[-netlist_probe_control control_value]
[-skip_flat_pl_node control_value]

H-2013.03
set_probe_option
-probe_undefined_node If you enable this option a probe of an undefined

enable_value signal writes a 0 valued constant signal to the plot
file. This option is only recognized in the Eldo
netlist format.
-variable_separator You use this option to change the separator

separator_char between the hierarchical path and the Verilog-A
variable or parameter name in the plot file to a
colon (:). The default separator is the regular
hierarchical delimiter (.) or the delimiter set by the
set_sim_hierid command.
-netlist_probe_control Controls whether the CustomSim tool honors the

control_value netlist probe statements (v(), i(), and x()).
■
0 causes the CustomSim tool to honor netlist
probe statements (default).
■
1 causes the CustomSim tool to ignore all the
netlist probe statements and any other
commands that trigger probing.
■ 2 causes the CustomSim tool to ignore all the
netlist probing statements but to honor all
commands that potentially trigger probing
(.measure/.print/vec/vcd).
-skip_flat_pl_node Controls whether CustomSim ignores the

control_value postlayout nodes for wildcard probing. You can
specify one of the following values:
■
0 (default) to not skip any flattened postlayout
nodes for wildcard probing. This is consistent
with the current CustomSim usage.
■
1 to skip all flattened postlayout nodes for
wildcard probing (name with ':').
■
2 to skip only internal nodes (ending with
:{number}) but keep others, such as instance
pins, for wildcard probing.
Description
When you specify -probe_undefined_node the CustomSim tool creates a
signal in the plot file with a constant value of 0V for any explicitly probed node.
This feature is only available for Eldo syntax netlists.

H-2013.03
set_probe_window
Examples
set_probe_option -probe_undefined_node 1
Causes probes of undefined signals to be written to the waveform file with a

constant value of 0 (zero).
set_probe_option -variable_separator :
Causes the probes of Verilog-A module variables and parameters to use a

colon separator between the hierarchical path and the variable/parameter
name. If the following probe is used: probe_waveform_va -var
x1.x2.va_var_name the signal name in the waveform file is
x1.x2:va_var_name.
The next example shows how set_sim_hierid, probe_waveform_va and
-variable_separator interact.
set_sim_hierid -hierid / #sets delimiter to foreslash
probe_waveform_va x1/x2/xva_module/va_var #must use foreslash
delimiter
set_probe_option -variable_separator : # use colon as variable
separator in plot file
#The wdf output is:
# x1/x2/xva_module:va_Va
set_probe_option -netlist_probe_control 1
Ignores all probe statements and other statements that may trigger probing.
set_probe_window
Defines a printing window that reduces the waveform output file size.
Syntax
set_probe_window -window {time_start_value time_end}
time_start_value [time_end]
where:
time_end ::== time_end_value | end
time_start_value Start time.

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set_probe_window
time_end_value Stop time.
Description
This command affects only the output waveform file. It does not have any effect
on any measure/extract or any other diagnostic command. If you specify
multiple set_probe_window commands, the last one takes precedence.
Multiple commands do not cause print windows to accumulate.
If the final time_end value is not specified it is assumed to be end. If multiple
windows are specified, they cannot overlap. The window end time must be
greater than the start time. The window times must be greater than 0.
The CustomSim tool supports the tstart option of HSPICE, Eldo, and TI-
SPICE, as well as the outputstart option of Spectre. set_probe_window
can be used to set the print window.
Examples
set_probe_window 1u
The previous example starts writing to the output file at 1us.

.tran 1n 1u 200n
.opt xa_cmd="set_probe_window 500n"
The previous example overrides the .tran statement because it occurs last.
Printing starts at 500ns.
.opt xa_cmd="set_probe_window 500n"
.tran 1n 1u 200n
In the previous example, the .tran statement overrides the xa_cmd. Printing
starts at 200ns.
set_probe_window 500n
The previous example starts printing at 500ns.

set_probe_window 100n 300n 400n 1u
The previous example prints from 100ns to 300ns and 400ns to 1us.
set_probe_window 100n 300n 400n
The previous example prints from 100ns to 300ns and 400ns to 1us.
set_probe_window –window 10n 20n
set_probe_window 30n 40n

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set_resistor_option
In the previous example, command precedence is applied and a single print

window of 30n to 40n is used.
set_resistor_option
Lets you control resistor handling at different phases of the simulation.
Syntax
set_resistor_option -rule 1|2 [-min value] [-max value]
or
set_resistor_option [-keep_negative_res enable_value]

resistor elements:
■ Specify a value of 1 to process (short or open based
on the elements) the resistor elements at the parsing
stage, before the optimization and after resolving the
parameters. This rule does not save elements in the
database, which means you cannot recover them
during a simulation. It has the advantage of using less
memory. It is the default.
■
Specify a value of 2 to save the resistor elements in
the database and process them during the
optimization. This rule has the advantage of
recovering resistor elements for other analysis in the
simulation. However, this type of analysis can impact
the performance of the simulation.
Note that you can specify both rules in one simulation,
but only rule 1 can override rule 1, and rule 2 can override
rule 2. Because rule 1 is executed before rule 2, make
sure that you specify:
min(rule1) < min(rule2) and max(rule1) > max(rule2).
See Figure 3 or further details about specifying both
rules in the same simulation.

H-2013.03
set_resistor_option
-min value Specifies the lower threshold value of the resistors to be

kept. All resistors with an absolute value above the
specified value are shorted by -rule argument.
-max value Specifies the upper threshold of the resistors to be kept.

All resistors with an absolute value above the specified
value are treated as an open-circuit by -rule argument.

The default is 0.
-keep_negative_res Enables or disables the control for negative resistors for

enable_value a simulation. Negative resistor often comes from
parasitic extraction. The default is 1 to keep negative
resistors (from both a netlist and back-annotation) for
optimization by the -rule, -min, and -max arguments.
If you want to disable negative resistors for simulation,
you need to set this argument.
See Table 14 for information about the defaults for
handling resistors.

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set_resistor_option
Description
Table 14 shows the defaults for handling schematic resistors in a simulation.
Table 14 Defaults for handling resistors

Format through
set_sim_level=6
HSPICE RESMIN=1e-5 Specifies the following Specifies the

defaults: following defaults:
■ ■
If the resistance value is Set to -1e-5 for
between -1e-5 and 1e-5, negative resistors
those resistors are and 1e-5 for
shorted by positive resistors.
■
set_resistor_option Short resistors
-rule 2. with a resistance
■
if the resistance value is value of 0.
larger than or equal to
1e12, or is smaller than
-1e-12, those resistors
are open by
set_resistor_option
-rule 2.
Eldo RSMALL=1e-6 Specifies the following Specifies the

■ ■
If the resistance value is Set to -1e- for
between -1e-6 and 1e-6, negative resistors
those resistors are and 1e-6 for
shorted by positive resistors.
■
set_resistor_option Short resistors
-rule 2. with a resistance
■ if the resistance value is value of 0.
1e12, or is smaller than
-1e-12, those resistors
are open by
set_resistor_option
-rule 2.

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set_resistor_option
Table 14 Defaults for handling resistors

Format through
set_sim_level=6
Spectre rmin=0 Specifies the following Specifies the

■ If the resistance value is ■ Short resistors
0, those resistors are with a resistance
shorted by value of 0.
set_resistor_option
-rule 2.
■ if the resistance value is
1e12, or is smaller than -
1e-12, those resistors are
open by
set_resistor_option
-rule 2.
Back- min_res=0.01 Specifies the following Same as

annotation max_res=1e12 defaults: set_sim_level=3
(DSPF or ■
If the minimum back- through
SPEF with annotation resistance set_sim_level=6.
load_ba_f value is between -0.01
ile) and 0.01, those resistors
are shorted by
set_ba_option.
■ if the maximum back-
annotation resistance
value is larger than or
equal to 1e12, or is
smaller than -1e-12, those
resistors are open by
set_ba_option.
Examples
set_resistor_option -rule 1 -min 0.1 -max 1e10
Sets the minimum and maximum threshold to 0.1 and 1e10 for all schematic
resistors. By default, all the schematic resistor values between -0.1 and 0.1 are
shorted by -rule 1. All the schematic resistors with values less that or equal

H-2013.03
set_resistor_option
to -1e10, or greater than or equal to 1e10 are open by -rule 1.

set_ba_option -min_res 0.1
resistors. The minimum threshold for back-annotation resistors is set to 0.01 by
set_ba_option. By default, all the schematic resistor values between -0.1 and
0.1 are shorted by -rule 1. All the schematic resistors with values less that or
equal to -1e10, or greater than or equal to 1e10 are open by -rule 1.
set_ba_option -min_res 0.01
load_ba_file -file ba1.spf
load_ba_file -file ba2.spf -min_res 1 -min_cap 1e-20
resistors. The minimum threshold for back-annotation resistors is set to 0.01 by
set_ba_option. The load_ba_file -res_min command overrides the minimum
threshold for the ba2.spf file to 1. By default, all the schematic resistor values
between -0.1 and 0.1 are shorted by -rule 1. All the schematic resistors with
values less that or equal to -1e10, or greater than or equal to 1e10 are open by
-rule 1.
set_resistor_option -rule 1 -min 0.5
set_resistor_option -rule 2 -min 10
load_ba_file -file ba.spf
All the schematic resistor values between -0.5 and 0.5 are shorted according
to -rule 1. All the schematic resistors with values less that or equal to -1e12,
or greater than or equal to 1e12 are open according to -rule 1. All the
schematic resistor values between 0.5 and 10 and -10 and 0.5 are shorted
according to -rule 2.
Figure 3 shows the relationships between -rule 1 and -rule 2 in the
same simulation.

H-2013.03
set_restore_option
0
(min of rule1) < (min of rule2) and (max of rule1) > (max of rule2) for positive resistors and capacitors
(min of rule1) > (min of rule2) and (max of rule1) < (max of rule2) for negative resistors and capacitors
Figure 3 Using -rule 1 and -rule 2 for resistors in the same simulation
See Also
load_ba_file
set_ba_option
set_restore_option
Restarts the saved run at time 0, regardless of the saved time.
Syntax
set_restore_option -time 0
-time 0 Note that the CustomSim tool does not do any

time shift of the input stimuli, it just restarts the
run at time 0.
set_sample_point
Use this command when you need to make very precise periodic
measurements, such as in FFT applications.

H-2013.03
set_save_state
Syntax
set_sample_point -period period_value
[-twindow {start_time stop_time} start_time [stop_time]]
-period period_value Sets the period between sampling points (the

sampling frequency). If you specify multiple
start_time and stop_time arguments, the
period applies to all the -twindow values.
-twindow {start_time Sets the start and stop time of the first sampling
stop_time} start_time point.
[stop_time]
Description
Very precise measurements such as those made during FFT analysis can be
adversely affected by sampling the simulator output waveforms, if the sample
points interpolate between time points solved by the simulator. This command
forces the simulator to synchronize all partitions and solve each time point that
will be sampled during a post-processing measurement. This prevents any
interpolation errors and maximizes the precision of a measurement.
Examples
Assume you are simulating a DAC and need to analyze the spectral output by
computing an FFT. The following example starts the first sample at 10
microseconds and sets the sampling rate to 10 mega samples per second.
That is, a sample point occurs at 10μ, 10.1μ, 10.2μ, 10.3μ, and so forth.
set_sample_point -period 100n -twindow 10u
Assume you are simulating a DAC and need to analyze the spectral output by
computing an FFT. In the following example, the first sample is at 10μ sampling
at a rate of 100Msps. The end of the sampling time is 20μ.
set_sample_point -period 100n -twindow 10u 20u
set_save_state
Saves a partial simulation run to be restarted later.

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set_save_state
Syntax
set_save_state [-time t_val {t_val}] |
[-period time_period ] | [-period_wall_time wall_time]
[-save_on_kill enable_value]
{[-time t_val {t_val}] | [-period time_period ] |
[-period_wall_time wall_time]
[-save_on_kill enable_value]}
[-type op|OP] [-file file_name]
-time t_val Saves the simulation at the time or times you specify. For
{t_val} ... each t_val time you specify the CustomSim tool creates a
file with .t_val#.ic extension. The dc (for time 0) and end
(for last transient point) keywords are valid values for t_val.
-period Saves the simulation at the time period you specify. The
time_period image is saved in a file with a .time.ic extension.
-period_wall_time Saves the simulation in a single file at the "wall time" period
wall_time you specify. The image is saved with a .save.ic extension.
The file is overwritten at each specified period time interval.
You must specify the wall time period in hours, and decimal
points are accepted.
-save_on_kill Saves the simulation when run a UNIX kill -15

enable_value command. You cannot use a kill -9 command. The image
is saved in a file with a .save.ic extension.
-type op|OP Specifies the saving type. Only op is currently available.
-file file_name Specifies the names of the saved files. The saved files have
.ic and .ic.sup. extensions. If you specify multiple
filenames, the last one is used for all saved files.
Description
The set_save_state command generates two files, one with a .time.ic
extension and one with a .time.ic.sup extension for each saved time you
specify with the -time or -period option.
When you specify -period_wall_time, two files are created with a
.save.ic and .save.ic.sup extension. The files are overwritten at each
wall time period. When you specify -save_on_kill, two files are created with
a .save.ic and .save.ic.sup extension.

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set_save_state
Note: Do not delete the .ic or .ic.sup files. You need both files to
restore a saved simulation. For more information abut restoring
a saved simulation, see the CustomSim User Guide.
The following rules apply to diagnostics commands and measurements:

■
The diagnostic files (.errz, .errt, .err, and CCK command outputs)
must be written out and updated at each saved time point.
■
Output measurements (.power, .meas, .mt) that have completed must be
written out and updated at each saved time point.
■
When restoring a simulation, if a measurement command starts before the
restore time and finishes after the restore time, that measurement is ignored
and a warning is issued.
The set_save_state command has the following restrictions:
■
You cannot specify multiple -time, -period and -period_wall_time
options on a single command line.
■
You can specify multiple values for -time. Only one value is allowed for the
other options.
■
You cannot specify multiple set_save_state commands with different -
period or -period_wall_time values. If multiple commands with
multiple -period or -period_wall_time are specified, the last period or
wall_time is applied.
■
You can specify multiple set_save_state commands with different -
time options.
■
You can specify one set_save_state command with -period or -
period_wall_time and one or more set_save_state commands with
the -time option.
■
You can combine the -save_on_kill option with the other options.
Examples
set_save_state -time 100n 1400n -type OP
Saves the simulation at 100ns and at 1400ns.

set_save_state -period 200n -type OP
Saves the simulation every 200ns.

set_save_state -period_wall_time 0.1 -type OP
Saves the simulation every 0.1 hours (every 6 minutes).

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set_sim_case
set_save_state -save_on_kill 1 -type OP
Saves the simulation when the run is killed with the UNIX kill -15
command.
set_save_state -period 200n -type OP
Saves the simulation at 10ns, 20ns, and every 200ns.

set_save_state -time 300n -type OP
Saves the simulation at times 10ns, 20ns and 300ns.
set_sim_case
Controls case-sensitivity in a netlist.
Syntax
set_sim_case -case upper|lower|sensitive
-case Specify one of the following keywords:

upper|lower|sensitive ■
upper to convert all the names to uppercase.
■ lower to convert all the names to lowercase.
■
sensitive to treat all names as case-
sensitive.
The default is based on the netlist format. For
HSPICE and Eldo, the default is lowercase. For TI-
SPICE, the default is uppercase. For Spectre and
Verilog, the default is case-sensitive.
Description
set_sim_case lets you control the case-sensitivity of the CustomSim tool for
all the supported netlist formats. When the -case upper|lower argument is
set, the CustomSim tool is case- insensitive and converts all names to
uppercase or lowercase, respectively. The -case sensitive argument
enables the CustomSim tool to be case-sensitive for all netlist formats.
Note: The temper and hertz keywords are always case insensitive
when evaluating expressions.

H-2013.03
set_sim_hierid
Examples
* Example 2 : HSPICE format
R1 port1 0 10
R2 porT1 0 10
r3 Port1 0 10
.probe v(*) i(r*)
If you specify set_sim_case -case upper or -case lower, the

CustomSim tool is case- insensitive and all 3 resistors are connected to the
same node, port1. If you specify set_sim_case -case sensitive, case-
sensitivity is enabled and the 3 resistors are connected to 3 different nodes:
port1, porT1, and Port1.
set_sim_hierid
Specifies the hierarchical separation character.
Syntax
set_sim_hierid -hierid sep_char
-hierid sep_char The legal hierarchical separation characters are:

■
Period (.) (default)
■ Colon (:)
■
Forward slash (/)
■ Caret (^)
Description
If you specify both the Eldo .hier option and the set_sim_hierid
command in the netlist file, the set_sim_hierid command takes
precedence. The same precedence applies if the set_sim_hierid command
is in the CustomSim command file.
Examples
set_sim_hierid /
Sets the hierarchical separation character to "/".

set_sim_hierid :

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set_sim_level
Sets the hierarchical separation character to ":".
set_sim_level
Controls the speed and model complexity trade-off.
Syntax
set_sim_level -level level instance_spec
Argument-- level Description
3 Specifies a functional and timing verification of digital, memory,

low-sensitivity analog, mixed-signal, and full-chip circuits.
4 Specifies a functional, timing and power verification of all

circuits, especially for small current or low voltage applications.
5 Specifies an accurate timing and power simulation of all

circuits, and block characterization.
6 Specifies a SPICE-like accuracy for timing and power

simulation of all circuits, and cell characterization.
7 Specifies a setting for small designs (less than 1000 elements)

or a small block of a large design, and device model
verification.
Description
See the Common Syntax Definitions section for details about the
instance_spec argument.
Controls the simulator speed and model complexity tradeoff. This command
can be applied to the entire netlist, or to specific subcircuits or instances. The
default level is 3, if this command is not specified.
Note: The local specification of the set_sim_level command

always takes precedence over the global setting.

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Examples
Example 46 sets the simulation level to 5 on the entire netlist:
Example 46
set_sim_level 5
Example 47 sets the simulation level on a specific instance:

Example 47
set_sim_level 4 -inst xpll
Example 48 sets the simulation level on all instances of a particular subcircuit

type:
Example 48
set_sim_level 6 -subckt chgpump
Specifies the performance/accuracy settings for simulating SRAM designs.
Syntax
set_sram_characterization [-enable] enable_value
[-app[lication] timing|power|pwra]
[-acc[uracy] 1|2|3|4|5]
[resistor_rule 1|2] [capacitor_rule 1|2]
enable_value Turns on the set_sram_characterization

command.
-application Specifies the SRAM simulation types:

timing|power ■
timing for a timing simulation (default).
■
power for a power or leakage simulation.
Note that use can use the app alias for this option. The
name is case insensitive.

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-accuracy Specifies the performance/accuracy tradeoff. The default

1|2|3|4|5 of 3 provides the best combination of performance/
accuracy. Specify 1 for the fastest simulation, or 5 for the
most accurate.
Note that use can use the acc alias for this option.
resistor_rule 1|2 You can specify one of the following values to control how
the CustomSim tool processes resistors:
■
1 (default) to specify that resistor optimizations are
done during parsing.
■
2 to specify that resistor optimizations are done during
front-end optimization. Specify this option when you
want to protect the resistors that are probed.
capacitor_rule 1|2 You can specify one of the following values to control how
the CustomSim tool processes capacitors:
■
1 (default) to specify that capacitors optimizations are
done during parsing.
■
2 to specify that capacitor optimizations are done
during front-end optimization. Specify this option
when you want to protect the capacitors that are
probed.
Description
For details about how to use the set_sram_characterization command
to simulate SRAM designs, see the CustomSim User Guide.
Examples
set_sram_characterization 1 -application timing
Specifies an SRAM timing simulation with the default setting.

set_sram_characterization 1 -application timing -accuracy 4
Specifies an SRAM timing simulation with accuracy level 4.

set_sram_characterization 1 -app timing -acc 4
Same as the previous example, but uses an abbreviated name.

set_sram_characterization 1 -application power
Specifies an SRAM power simulation with the default setting.

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set_sram_characterization 1
Specifies an SRAM simulation with the default settings.
Controls the synchronization settings between the gate/channel/bulk of the
elements.
Syntax
set_synchronization_level -level level_value
-level level_value Sets the synchronization level. By default, the

set_synchronization_level value matches
the specified set_sim_level value.
-inst inst_name Applies the synchronization settings to the specified

{inst_name} instances.
-subckt subckt_name Applies the synchronization settings to the specified

{subckt_name} subcircuits.
Description
You use the set_synchronization_level command with set_sim_level to
speed up or to increase the accuracy of a simulation. For example, in some
designs that use set_sim_level 5, you can get better performance, and close to
the same accuracy, with set_synchronization_level 3.
set_synchronization_option
Provides flexibility to control the synchronization between blocks.

H-2013.03
set_tolerance_level
Syntax
set_synchronization_option -rule gate|never
-rule gate|never gate specifies that If the gate of a MOSFET is in a

different partition than the channel, those two
partitions will be evaluated at the same time points.
Applying synchronization on the gate of this
MOSFET might help to improve accuracy.
never turns off the synchronization between the
different partitions. This is useful for speeding up the
simulation when the signal is only fed forward from
gate to the channel when
set_partition_option -rule is applied.
-inst inst_name Applies the synchronization rule to the specified

{inst_name} instances.
-subckt subckt_name Applies the synchronization rule to the specified

{subckt_name } subcircuits.
Description
This command is often used with the set_partition_option command. When
manual partitioning is applied to an instance, different partitions might need to
be synchronized to improve the accuracy, or un-synchronized to speed up the
simulation. You can apply this command can be applied globally or locally.
set_tolerance_level
Provides flexibility for tuning the CustomSim tool relative tolerance level to the
set_sim_level setting. The relative tolerance level controls the sensitivity of the
simulator to small voltage changes.
Syntax
set_tolerance_level -level tolerance_level [instance_spec]

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set_tolerance_level
-level The default relative tolerance levels that correspond to the

tolerance_level set_sim_level settings are as follows:
■
3 applies the same relative tolerance value used with
set_sim_level 3.
■
set_sim_level 4.
■
set_sim_level 5.
■
set_sim_level 6.
■
set_sim_level 7.
The following section describes the cases when a lower or
higher tolerance_value can improve performance and
accuracy.
instance_spec See the Common Syntax Definitions section for details about
the instance_spec argument.
Description
set_tolerance_level provides more flexibility to tune the CustomSim tool
to specific simulation requirements, similar to set_tolerance_option. It lets you
adjust the relative tolerance level appropriate to the corresponding
set_sim_level level.
The set_tolerance_level command is helpful when:
■
A CustomSim simulation is functionally correct at a lower set_sim_level
setting, but a higher set_sim_level setting is needed to achieve the required
accuracy. There are cases when you can use a lower set_sim_level setting
with a higher tolerance_level to obtain the desired accuracy with better
performance.
For example, if a data converter is functional at set_sim_level=5 and
higher, but the FFT requirements are only met at set_sim_level=7. You
might find that set_sim_level=5 and set_tolerance_level 7
achieves the required accuracy with significantly better performance than
set_sim_level=7.
■
An CustomSim simulation meets the accuracy requirements, but runs
slowly. You can set tolerance_level to a lower value below the
corresponding set_sim_level setting to gain better performance with

H-2013.03
some sacrifice in accuracy. A lower tolerance_level setting might be

useful when another simulator gets good results with or close to its default
settings, but the CustomSim tool runs more slowly.
set_tolerance_level can control the relative tolerance level globally or
locally. The most significant impact of the relative tolerance level is to adjust the
time step of the simulator. There are secondary impacts on MOS lookup table
granularity and RC reduction.
Examples
set_sim_level 6
set_tolerance_level 7 –subckt a2d
This example applies a set_sim_level of 6 setting to the entire circuit. For the
a2d subcircuit, the tolerance parameters are overwritten with a more
conservative setting of set_tolerance_level 7.
Lets you control the simulation tolerance independent of the set_sim_level
command for more flexibility in tuning performance/accuracy.
Syntax
set_tolerance_option -tol tol_value [-tol_rule 0|1]
-tol tol_value Specifies the tolerance value. The most significant impact of
this value is to adjust the time step of the simulation. However,
the specified tolerance value also has secondary impacts on
the MOS look-up table granularity and RC reduction. Table 15
shows the default tolerance values.

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-tol_rule 0|1 Applies the CustomSim simulator heuristics as follows:

■
A value of 0 applies the specified tol_value as a base
setting, but the simulator heuristics might override this value
in certain parts of the design. The value override used by
the simulator heuristics is typically smaller than the user-
specified tol_value.
■
A value of 1 applies the specified tol_value to the entire
design. The simulator heuristics do not override the
tol_value.
-inst inst_name Instance names to which set_tolerance_option applies.

{inst_name}
-subckt Subcircuit names to which set_tolerance_option applies.

subckt_name
{subckt_name}
Description
By providing more flexibility in tuning a CustomSim simulation to specific design
requirements, set_tolerance_option lets you control the simulation
tolerance independent of the set_sim_level command. You can apply
set_tolerance_option globally or locally.
The tolerance value (-tol) controls the sensitivity of the simulation to small
voltage changes. This value is arbitrary and is not based on a unit. Valid values
are 0.1 to 800. Note that a value of 800 is extremely aggressive in favor of
performance, and most circuits are not functional with this setting.
The default tolerance values for each set_sim_level setting are shown in
Table 15.
Table 15 Default Relative Tolerance Values
Accuracy Level Default set_tolerance_option Value
set_sim_level 3 -tol=200 (less accurate)
set_sim_level 4 -tol=150

H-2013.03
set_vector_option
Table 15 Default Relative Tolerance Values
Accuracy Level Default set_tolerance_option Value
set_sim_level 7 -tol=0.1 (very accurate)
The set_tolerance_option command is helpful when:

■
An CustomSim simulation is functionally correct at a lower set_sim_level
setting, but a higher set_sim_level setting is needed to achieve the required
accuracy. There are cases when you can use a lower set_sim_level setting
with a smaller tol_value to obtain the desired performance and accuracy.
For example, if a data converter is functional at set_sim_level=5 and
higher, but the FFT requirements are only met at set_sim_level=7, you
might find that set_sim_level=5 and set_tolerance_option -tol
0.1 achieve the required accuracy with performance significantly better
than set_sim_level=7.
■
An CustomSim simulation meets the accuracy requirements, but runs
slowly. You can increase tol_value above the default set_sim_level
setting to gain better performance with some sacrifice in accuracy. A higher
tol_value setting might be useful when another simulator gets good
results with or close to its default settings, but CustomSim runs more slowly.
Examples
set_sim_level 6
set_tolerance_option -tol 0.1 -subckt a2d
This example applies set_sim_level=6 to the entire circuit, but overrides

the tolerance parameters for the a2d subcircuit with a more conservative
setting of 0.1.
set_vector_option
Allows the plotting of a logic signal to represent the "output expected" signal for
any specified output variable inside the VEC/VCD file.
Note: Only the WDF, FSDB, WDB, OUT and VPD formats support this
feature.

H-2013.03
set_vector_option
Syntax
set_vector_option [-node node_name {node_name}]
[-check_u_state value] [-check_z_state value]
[-check_method value] [-define_x_state state_value]
[-vec_mode mode] [-print_expected switch_value
[-node node_name {node_name}]]
-node node_name Specifies a node name inside a vector file or inside

{node_name} the sig_info file. You can specify multiple node
names with wildcard characters. The default is to
match all nodes specified inside the vector file or the
signal specified by the sig_info file.
-check_u_state value Checks the U-state between the signals in the VCD
and CustomSim VEC files against the actual state of
the nodes. You can specify a value of 0 or 1:
■ 0 (default) specifies that if a node is in a U-state, it
passes the vector checking regardless of the value
in the VCD or CustomSim VEC files. In addition, if
U-state is specified in the VCD or CustomSim
VEC files, a node passes checking regardless of
its state.
■
1 specifies that the node state level must match
the expected U-state specified in the CustomSim
VEC file. If a VCD file is used, the
check_u_state check is ignored and no
checking is preformed.
-check_z_state value Checks the Z-state between the signals in the VCD
and CustomSim VEC files against the actual state of
the nodes. You can specify a value of 0 or 1:
■
0 (default) specifies that the floating status for
nodes is not checked.
■
1 specifies that floating status for nodes must
match the floating status specified in VCD and
CustomSim VEC files.

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set_vector_option
-check_method value Specifies the vector checking mechanism between

the VCD and VEC formats. You can specify a value of
1 or 2:
■
1 specifies continuous checking, which is the
default for the VCD format. This check method
only supports the VCD format.
■
2 specifies strobe-based time point checking,
which is the default method for the HSPICE VEC
format. This check method supports both HSPICE
VEC and VCD formats.
-define_x_state Defines how to treat the X state. The acceptable

state_value state_value is range from 1 through 4:
■
1 to always set to low_voltage.
■ 2 to always set to high_voltage.
■
3 to set (high_voltage + low_voltage)/2.
■ 4 to set the voltage value to the previous voltage.
The default state_value is set to 1. When the x-
state is set, it also reflects the printing of the logic
waveform on the x-state as well.
-print_expected Generates an expected (ideal) output signal used to

switch_value compare with the actual output signal. You can
specify one of the following values:
■
0 (default) does not generate and expected
output.
■ 1 generates the expected output waveform (with a
_#e extension) based on the VEC/VCD file.
-node node_name Multiple nodes are allowed with multiple node names.
{node_name} Without this option,
-print_expected is a global option.
-vec_mode mode Specifies one of the following formats:

■
hspice to use the HSPICE vector file format
(default).
■
hsim to use the HSIM file vector file format.
Examples
set_vector_option -print_expected 1

H-2013.03
set_waveform_format
Generates the expected output signal in the waveform file for visual comparison
with the actual output signal waveform.
set_vector_option -print_expected 1 -node d[0]
Generates the expected output for the d[0] signal name.

set_vector_option -print_expected 1 -node d[0] d[1] d[2] s[0]
Generates the expected output for the following signal names: d[0], d[1],
d[2], and s[0].
set_vector_option -check_z_state 1 -check_u_state 1
Instructs the CustomSim tool to report the mismatch of the high impedance
state (Z) and U-state between simulated node states and the states specified in
the VEC/VCD file.
set_waveform_format
Specifies the fsdb file format.
Syntax
set_waveform_format -format version
Default and latest version of FSDB will be selected. Output file will be FSDB Version 5.0
-format version Specifies one of the following versions:

■
fsdb specifies to use the default and latest
version of FSDB. The output file is in FSDB
version 5.0.
■ fsdb_4.3 specifies to use version 4.3 of FSDB.
The output file is in FSDB version 4.3.
set_waveform_option
Sets the output waveform options. You can specify the file format, file-split size,
voltage resolution, current resolution and flush percentage.

H-2013.03
set_waveform_option
Syntax
set_waveform_option [-grid_v grid_val] [-grid_i grid_val]
[-compress_v compress_val] [-compress_i compress_val]
[-tres time_resolution_value]
[-flush flush_time | flush_percentage_value%]
[-format format] [-file split | merge]
[-size max_file_size_MB] [-disk_full space_in_MB]
-grid_v grid_val Controls the grid size of the

output voltage signal. All output
points are rounded to the
nearest integer of the grid. If set
to 0, the rounding is turned off.
-grid_i grid_val Controls the grid size of the

output current signal. All output
points are rounded to the
nearest integer of the grid. If set
to 0, the rounding is turned off.
-compress_v compress_val Controls the voltage

compression. If set to 0, the
compression is turned off.
-compress_i compress_val Controls the current signal

compression. If set to 0, the
compression is turned off.
-tres time_resolution_value Specifies waveform file minimum

time resolution value by
rounding. The default is 0.1p. If
set 0, the rounding is turned off.

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set_waveform_option
-flush flush_time | By default, the CustomSim tool

flush_percentage_value% writes to the output file when the
output file buffer is full. This
argument forces periodic writes
to the output file. If a flush_time
is specified, the output file is
written at integer multiples of
flush time. The flush time is in
terms of the transient simulation
time, not real time. The value is
seconds.
If a percentage is specified by
using a % character, the file is
written at integer multiples of the
percentage of the simulation
transient end time.
-format Sets the output waveform file

[fsdb|wdb|out|wdf|tr0|psfbin|vpd|utf] format. See Supported
Waveform Formats in the
CustomSim User Guide for more
details. Note that the utf format
is only available on the amd64
platform.
-file [split | merge] If you specify the vpd output

waveform file format, you can
use the -file argument to set
the file generation mode during
CustomSim-VCS cosimulation.
If you specify split, two vpd
files are generated by the
CustomSim tool and VCS
separately. If you specify merge,
one vpd file is generated.
-size max_file_size_MB Sets the maximum file size

before file splitting. See
Table 16.

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set_waveform_option
-disk_full space_in_MB The CustomSim tool periodically

checks the remaining disk space
in the output file disk. If the
available disk space is less than
twice the specified value, the
CustomSim tool issues a
warning. If you specify this
argument and the available disk
space is less than the specified
value, and the CustomSim tool
was invoked with the interactive
mode command line option, -
intr, the CustomSim tool
enters interactive mode.
Otherwise the CustomSim tool
exits with an out of disk space
error.
Note that if you do not specify
this argument, the CustomSim
tool only issues warnings.
The default value of this option is
100MB.
Description
The format switch can be used to set the waveform output file format.
The waveform format can be specified in several ways. The order of
precedence for specifying the waveform output file format is:
1. -wavefmt option on the command line
2. set_waveform_option command in a command script file (the command
script file is evaluated as if the file were used on the final line of the netlist)
3. The last .opt post=format or .opt
xa_cmd="set_waveform_option ..." command that appears in the
netlist
The size switch can be used to force the splitting of the waveform output file to
a more convenient size. The value is specified in megabytes. The minimum file
size for the formats that support file splitting is 10Meg. See Table 16 for the

H-2013.03
set_waveform_option
CustomSim default resolutions and supported file-splitting features.

Table 16 Supported file-splitting features (N/S means not supported, N/A means not
applicable)
Output -compress_v -compress_i -grid_v -grid_i -tres -flush Split 32- 64-
Format (-size) bit1 bit1
fsdb 1uV 1pA 1uV 1pA 0.1p Yes Yes 2G No

split
out 1uV 1pA 1uV 1pA 0.1p N/S Yes 2G No

split
wdb 1uV 1pA 1uV 1pA 0.1p Yes Yes 2G 2G
wdf 1uV 1pA 1uV 1pA 0.1p Yes Yes 2G No

split
tr0 1uV 1pA N/S N/S 0.1p N/S N/S N/A N/A
psfbin 1uV 1pA N/S N/S 0.1p N/S N/S N/A N/A
vpd 1uV 1pA 1uV 1pA 0.1p Yes Yes 2G No

split
utf 1uV 1pA 1uV 1pA 0.1p Yes Yes 2G No

split
1. Default automatic split sizes.
The -compress_v and -compress_i options are used to specify the

resolution values for the slope-based lossy compression. Any data points that
deviate from a straight line by less than this lossy compression value are
dropped. The default voltage resolution is 1uV, and the default current
resolution is 1pA.
The -grid_v and -grid_i options are used to specify the resolution values
for rounding lossy compression. Any data points that deviate from resolution
grid are rounded off to the closest grid. The default voltage resolution is 1uV,
and the default current resolution is 1pA.
The -flush switch can be used to force more frequent writing to the output
waveform file. Use this switch when you want to view the simulation progress

H-2013.03
set_waveform_option
during the simulation. If this command is not specified, the default setting is
every 10%.
The disk full option alerts you that the output disk is nearing capacity. If the
disk becomes completely full, unpredictable behavior may result. The -
disk_full option can be used to raise warnings when the disk is nearing
capacity (2x the set or default value) and to stop when the disk is nearly full
(space is less than the set value). This may help to preserve the integrity of
output files, but their integrity cannot be guaranteed.
If the -disk_full option is not specified the CustomSim tool only raises
warnings when the disk has less than 200MB (2x the default value of 100MB).
If this option is specified, the CustomSim tool stops with a disk full error if the
disk space is detected to be less than the specified threshold.
The default value of disk full is 100MB. If the disk full option is not explicitly set
the CustomSim tool starts to issue warnings when the disk has less than
200MB of space, but it does not stop with an error:
Warning: The available disk space 175MB is less than
200MB. Ctrl-C can suspend a simulation. Use the
set_waveform_option command to adjust the disk full
threshold.
If you specify:
set_waveform_option -disk_full 1000
The CustomSim tool issues a warning when the disk space is less than 2Gig
and stops when it is less than 1G.
Examples
set_waveform_option -format out -size 1000 -grid_i 1n -grid_v 1n
-tres 1p -flush 5%
Sets the output format to out, a split size of 1000Meg, current grid to 1nA,
voltage grid to 1nV, and writes to the waveform output file every 5% of the
simulation time. The time resolution is set to a minimum of 1ps.
set_waveform_option –flush 100n
The previous example causes the CustomSim tool to update the waveform file
after every 100ns of simulation time.
set_waveform_option –flush 150ns
after every 150ns of simulation time.

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set_wildcard_rule
set_waveform_option –flush 10%
after every 10% of the simulation time. If the transient end time is 2us, in this
example the CustomSim tool updates the waveform file after at least every
200ns.
See Also
Supported Waveform Formats in “Running the Simulator” in the CustomSim
User Guide.
set_wildcard_rule
Enables the CustomSim tool to match all levels of the hierarchy—or only one
level—depending on your specifications. By default, the CustomSim tool
follows HSPICE behavior, which matches all levels of the hierarchy.
Syntax
set_wildcard_rule -match* all | one
-match* Specifies * to match any number of hierarchy levels (default) or

all|one one level of hierarchy.
Description
Sets rules for wildcard * matching in instance and node hierarchical names.
If the one argument is set, the CustomSim tool matches the asterisk ( * )
character to one level of the hierarchy; otherwise, all levels of the hierarchy are
matched.
Examples
set_wildcard_rule -match* one
See Also
probe_waveform_current, probe_waveform_logic,
probe_waveform_voltage, report_power

H-2013.03
set_zstate_option
set_zstate_option
Sets the conducting rules for the check_node_zstate command.
Syntax
set_zstate_option -idsth value_1 [-vbeth value_2]
[-rule rule_value {rule_value}] [-diode_vth value]
[-va_rule value] [-xdummy value]
-idsth value_1 Specifies the threshold for a MOSFET to be considered

conducting when ids exceeds value_1. If not specified, the
default is 1e-8 ampere. See the Description section for
more information about the conducting criteria.
-vbeth value_2 Specifies the threshold for BJT to be considered

conducting when Vbe exceeds value_2. If not specified,
the default is 0.64 volt. See the Description section for
-rule rule_value Selects the rule of conducting for a MOSFET. The

{rule_value} MOSFET is considered conducting if one of the rules is
met. Other rules are as follows:
NMOS:
■
Vgs > Vth (rule=1)
■
Ids > idsth (rule=2)
■
Vg > VDD-0.1 (rule=3)
PMOS:
■
Vgs < Vth (rule=1)
■ Ids > idsth (rule=2)
■
Vg < 0.1 (rule=3)
The default is 1 and 2.
-diode_vth value Specifies the threshold for a diode to be considered

conducting when Vac exceeds the specified value. If you
specify a value less than 0, diode is considered as not
conducting. The default is 0.2V.

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set_zstate_option
-va_rule value By default, or when this argument is set to 0, the output

nodes of Verilog-A modules are reported if there is no
conducting path from the voltage source to the output
nodes. When this argument is set to 1, those nodes are not
reported in the output file.
-xdummy value Enables additional checking on the fanout devices (MOS

and BJT) of the HiZ node. A MOS is a dummy device if and
only if: (source && gate are in HiZ) or (drain && gate are in
HiZ). BJT is a dummy device if and only if: (collector &&
base are in HiZ) or (emitter && base are in HiZ).
Set this argument to 0 (default) to disable it or to 1 to
enable the check. A HiZ node is reported only when it
connects to at least one non-dummy transistor (MOS or
BJT). For a node that is HiZ, fanout devices are also
reported along with the HiZ node.
Description
This command specifies the conducting rules so that the CustomSim tool can
diagnose specified nodes staying in a high-impedance (floating) state for a
specific period of time. The detected nodes are reported to an error file with
suffix of .errz.
Device Rule
NMOS Vgs > Vth (rule=1) || Ids > idsth (rule=2) || Vg > VDD-0.1
(rule=3)
PMOS Vgs < Vth (rule=1) || Ids > idsth (rule=2) || Vg < 0.1 (rule=3)
NPN Vbe > Vbeth

The default for vbeth is 0.64
PNP Vbe < -Vbeth

The default for Vbeth is 0.64

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set_zstate_option
Device Rule
Diode I(diode) > diode_ith || V(a,c) > diode_vth

The default for diode_ith is 1e-8A.
Resistor Always conducting by default.
Examples
In the previous example, node nhz is a HiZ node. It is always reported by

default or when -xdummy is set to 0. When -xdummy is set to 1, it enables the
check of the fanout devices of the node nhz. If the fanout devices are off, then
node nhz is not reported. In this case, node nhz is not reported if mp12 and
mp22 are both off (dummy). The dummy states of mp12 and mp22 are
controlled by node in_1 and in_2. When the controlling node is logical high, the
transistor being controlled is dummy. For those that remains as HiZ, the fanout

H-2013.03
skip_circuit_block
transistors are reported along with the HiZ node.
skip_circuit_block
Provides the equivalent effect of commenting out instances without editing
netlist files.
Syntax
skip_circuit_block instance_spec
Description
Be careful how you use this command, because it can affect the circuit
connectivity. It checks for floating nodes, gates, and dangling nodes after the
circuit block has been removed and issues appropriate warnings.
Examples
Example 49
skip_circuit_block -inst x1.xregulator
Removes the x1.xregulator instance from the netlist.
Example 50
skip_circuit_block -subckt pdetect
Removes all instances of the pdetect subcircuit from the netlist.
Example 51
skip_circuit_block -inst d1 -subckt nmosmac
Removes d1 from all instances of the nmosmac subcircuit.
source
source is a native TCL command, not a CustomSim-specific command. You
use it to include other command script files.
Syntax
source file_name

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source
Description
This command reads and references another command script file. Use it with
the -c command line option, not the .opt xa_cmd option.
Examples
Example 52
#Test case-specific file
set_sim_level 4
#Load common settings
source xa_common_settings.tcl

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3
CustomSim Interactive Command Syntax
3
Provides the syntax for all of the CustomSim interactive commands.
The CustomSim commands are:

alias
icheck_node_zstate
iclose_log
icontinue_sim
idelete_break_point
iforce_node_voltage
ilist_break_point
ilist_force_node
imatch_elem
imatch_node
iopen_log
iprint_connectivity
iprint_dcpath
iprint_elem_info
iprint_exi
iprint_flash_cell
iprint_help
iprint_node_info
iprint_subckt
iprint_time
iprint_tree
iprobe_waveform_voltage
iquit_sim
irelease_node_voltage
ireport_node_cap
ireport_operating_point
isearch_node

H-2013.03
Chapter 3: CustomSim Interactive Command Syntax
alias
iset_break_point
iset_diagnostic_option
iset_interactive_option
iset_save_state
iset_zstate_option
alias
Creates an alias name for the interactive commands. When arguments are
specified, an alias is defined for each alias_name for whose actual_name is
given.
Syntax
alias alias_name actual_name
alias_name Creates an alias for an interactive command.
actual_name Defines the interactive command.
Examples
Example 53
alias pns iprint_node_info
Example 53 creates an alias pns for the iprint_node_info command.
Example 54
alias ipe iprint_elem_info -index
Example 54 creates an alias ipe for the iprint_elem_info command

with the argument -index.
icheck_node_zstate
Performs a high-impedance node check in interactive mode.

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icheck_node_zstate
Syntax
icheck_node_zstate -node node_name {node_name}
[-fanout <0|1|2>]
[-rule rule_value {rule_value}]
[-except_subckt subckt_name {subckt_name}]
[-diode_vth value]
[-idsth ids_value]
[-vbeth vbeth_value]
[-except_node node {node}]
[-file file_name]
[-report report_value {report_value}]
-node node_name Specifies the node names at which the high-impedance

{node_name} state is checked. The node name can be a single node or
a node name with a wildcard character that represents a
group of node names. The rule of asterisk (*) character is
controlled by set_wildcard_rule.
-fanout <0|1|2> Selects the type of nodes for high-impedance checking:

■
A value of 0 enables all nodes.
■ A value of 1 enables nodes that have a direct
connection to a transistor gate.
■
A value of 2 enables all nodes that have a direct
connection to a transistor bulk.
If you do not use this option, the default is 0.

NMOS:
■
Vgs > Vth (-rule 1)
■ Ids > idsth (-rule 2)
■
Vg > VDD-0.1 (-rule 3)
PMOS:
■
Vgs < Vth (-rule 1)
■ Ids > idsth (-rule 2)
■
Vg < 0.1 (-rule 3)

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icheck_node_zstate
-subckt subckt_name Specifies the subcircuits to be checked. Wildcard

{subckt_name} characters are not allowed in subcircuit names.
-except_subckt Specifies the subcircuits to be excluded from high-

subckt_name impedance checking. This argument should be used only
{subckt_name} when –node node_name contains wildcard characters.
-diode_vth value Sets the forward bias threshold for diodes. A diode with
v(a,c) greater than value is considered conducting for a
high impedance check. A value less than 0 causes diodes
to be always considered non-conducting.The default value
is 0.2V.
-idsth ids_value Specifies the threshold for a MOSFET to be considered

-vbeth vbeth_value Specifies the threshold for BJT to be considered

-except_node Specifies the nodes to be excluded from high-impedance

node_name checking. This argument should be used only when –node
{node_name} node_name contains wildcard characters.
-file file_name If you specify a file name the output is written to that file
instead of standard output. If you specify an existing file
name, that file is overwritten.
-report You can specify the following keywords:

report_value ■
node lists Hi-z nodes.
{report_value} ■
channel lists all channel-connected devices for the
node.
■
gate lists all gate-connected devices for the node.
The default is node.
Description
This interactive command enables the CustomSim tool to diagnose specified
nodes staying in a high-impedance (floating) state.

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icheck_node_zstate

Device Rule
NMOS ■ Vgs > Vth (rule=1)

■
■ Vg > VDD-0.1 (rule=3)
■
PMOS Vgs < Vth (rule=1)
■
■ Vg < 0.1 (rule=3)
For more information about the rule values, see
iset_zstate_option.
NPN Vbe > vbeth
PNP Vbe < -vbeth
Diode Forward-biased.
Resistor Always conducting.
To diagnose if a high impedance condition is harmful, you need to know which

gates it is driving. To diagnose how to fix the high impedance condition, the
channel-connected elements must be reported. The voltage on the high
impedance nodes is always reported. The hierarchical subcircuit names are
always be printed when you specify
-report gate and channel. The MOS terminal voltages are also printed.

H-2013.03
iclose_log
iclose_log
Closes the interactive mode log file that was opened by the iopen_log
command. The log file contains all records of interactive mode commands and
the results reported by the commands entered between iopen_log and
iclose_log.
Syntax
iclose_log
See Also
iopen_log
icontinue_sim
Continues the transient simulation from the initial stop point to the following
stop point. If time and unit are specified, the simulation stops and enters the
interactive mode at time t+(time)(unit). The -to option specifies the
absolute time to which the simulation proceeds, then enters interactive mode.
Syntax
icontinue_sim -i time[unit] [-to time[unit]]

H-2013.03
icontinue_sim
-i time[unit] Stops the simulation and enters the

interactive mode at time t+(time)(unit)
t is the current simulation time.
If t+(time)(unit) is less than the
simulation stop time, the simulation
continues until t+(time)(unit), then
enters the interactive mode at
t+(time)(unit).
White space is not allowed between time
and unit.
If time[unit] is not specified, the
simulation continues until it is completed, or
until the ctrl-C is entered.
The default for unit is seconds, if not

specified.
-to time[unit] Specifies the absolute time to which the

simulation proceeds, then enters interactive
mode. For example, if you specify
icontinue_sim -to 11ns at time 9ns,
the transient simulation runs to 11ns. This
command issues a warning, and is ignored, if
the time specified by -to is less than the
current time.
Examples
icontinue_sim 10n
This example continues the simulation for another 10ns.

icontinue_sim -to 10n
This example runs the simulation to 10ns and returns to interactive mode,
assuming current time is less than 10ns.

H-2013.03
idelete_break_point
idelete_break_point
Removes the stop points.
Syntax
idelete_break_point -point all|stop_point1
[stop_point2 ... stop_pointn]
-point all Removes all the stop points.
-point stop_point1 Removes the specified stop points.

stop_point2... stop_pointn
Examples
XA> ilist_break_point
1: break at time: 1 ns
XA> idelete_break_point 2
Example 55
idelete_break_point -point 2
Example 55 removes stop point 2.

See Also
ilist_break_point
iforce_node_voltage
Forces the specified nodes to stay at the specified constant voltage. The node
voltage stays at the same value from the current time until either the end of
simulation or when the constant node voltage status is released by
irelease_node_voltage.

H-2013.03
ilist_break_point
Syntax
iforce_node_voltage -node node_name {node_name}
-v[oltage] voltage_value [-slope t_value]
-node node_name Specifies the node name to force.

{node_name}
-voltage Specifies the voltage value to set.

voltage_value
-slope t_value Forces the voltage with a ramp of t_value (in seconds
per volt). The default is 1ps and must be positive a positive
value.
Examples
XA> iforce_node_voltage -node cn -voltage 2
The cn node is forced at 2 V starting at the current time. It remains at this value
until the end of the simulation unless you use irelease_node_voltage command
for the same node.
ilist_break_point
Lists the existing stop points.
Syntax
ilist_break_point -list [number]
-list number Lists the last number of the stop points. If

not specified, lists all the stop points.
Examples
XA> ilist_break_point -at 1n
XA> iset_break_point -at 10n

H-2013.03
ilist_force_node
Example 56
ilist_break_point -list
Example 56 lists the existing stop points.
ilist_force_node
Lists all nodes you specified with force_node_voltage.
Syntax
ilist_force_node -file file_name
-file file_name Specifies the file name that contains the list
of forced nodes.
Description
If you specify the -file argument, the forced node list is written to the
specified file. Otherwise the list is echoed to the standard output.
Note that a node forced with force_node_voltage is not listed in the output of
this command unless the simulation time advanced since the node was forced.
Examples
XA> iforce_node_voltage xbuffer.pd_d -v 1.2
XA> iforce_node_voltage xbuffer.sigi -v 0
XA> ilist_force_node
XA> icont 1n
XA> ilist_force_node
xbuffer.pd_d (4) = 1.2
xbuffer.sigi (3) = 0
imatch_elem
Prints a list of the element indexes and hierarchical element names that match
the specified pattern.

H-2013.03
imatch_node
Syntax
imatch_elem -pattern pattern ...
pattern Patterns can contain the * wildcard

character. The printed list shows all matches
to the specified pattern. You can set wildcard
matching for the hierarchy with
iset_interactive_option.
Examples
XA> imatch_elem *x1*
5 x1.r1
6 x1.r2
7 x1.x1.r1
In this example, the *x1* pattern matches 3 elements.

See Also
imatch_node
Prints a list of the node indexes and node names that match the specified
pattern.
Syntax
imatch_node -pattern pattern ... [-limit level] [-port
enable_value]
pattern Patterns can contain the * wildcard character.

The printed list shows all matches to the
specified pattern. You can set wildcard
matching for the hierarchy with
iset_interactive_option.

H-2013.03
imatch_node
-limit level Specifies wildcard matching only down to the

specified hierarchical depth. The default
hierarchical limit level is 3.
-port enable_value Enables or disables the matching of

subcircuit port names. The default value of is
taken from the iset_interactive_option
command.
Description
imatch_node prints a list of matched nodes. The CustomSim tool first reports
the value of
-limit applied, then lists the node index and node name matched with one
item per line. Finally, the CustomSim tool reports the total number of matched
nodes.
The iset_interactive_option command settings apply to this command. The "*"
wildcard can be set to match or not to match the hierarchical delimiter. The "*"
wildcard * only matches primary node names, unless you specify the -port
argument. When you specify -port, the "*" wildcard also matches alias node
names.
Examples
XA> imatch_node *a
1 a
2 x1.a
3 x1.fa
pattern *a matched 3 nodes
In this example, the *a pattern matches 3 nodes.

XA> imatch_node *a -limit 0
imatch_node using -limit 0
1 a
pattern *a matched 1 nodes
This example finds all nodes ending in a at the top-level of the netlist, level 0.
XA> imatch_node *out -limit 4 -port 1
15 x0.x1.x2.aout
15 x0.x1.x2.x3a.out
16 x0.x1.x2.bout
16 x0.x1.x2.x3b.out

H-2013.03
iopen_log
This example finds all nodes ending in out down to the hierarchical depth of 4
and also reports ports.
See Also
iopen_log
Opens the interactive mode logfile_name, which contains the record of the
interactive mode commands and the results reported by these commands until
the log file is closed by the iclose_log command. Only one log file can be
opened at one time.
Syntax
iopen_log -file logfile_name [-mode append|write]
-file logfile_name Specifies the interactive mode log file name.
-mode append Specifies that contents are appended to pre-

existing files using the same file name.
-mode write Specifies that contents overwrite pre-existing

files using the same file name. Default is
-mode write.
Examples
iopen_log -file logfile
This example opens the log file named logfile.

See Also
iclose_log

H-2013.03
iprint_connectivity
iprint_connectivity
Prints the detailed node connectivity information for the given node names or
indices. The elements are categorized into channel-connected, gate-
connected, and other elements.
Syntax
iprint_connectivity -node node_name {node_name}
[-print gc|cc|o|all] [-on current_value]
[-file file_name] [-file_append file_name]
iprint_connectivity -index node_index {node_index}

[-print gc|cc|o|all] [-on current_value]
[-file file_name] [-file_append file_name]
-node node_name {node_name} Specifies the node name, which can contain
wildcard characters.
-print gc|cc|o|all Specifies to selectively print the gate-

connected, channel-connected, other, or all
elements. If not specified, the default prints
gate-connected and channel-connected
elements.
-index node_index Specifies node index.
-on current_value Prints only those instances that have a

current exceeding the specified
current_value.
-file file_name Writes output only to the specified file. If the

file exists it is overwritten. The file is located
in the directory specified by the -o command
line argument.
-file_append file_name Writes output only to the specified file. If the

file exists this argument appends the output
to the existing file, otherwise it creates the
specified file. The file is located in the
directory specified by the -o command line
argument.

H-2013.03
iprint_dcpath
Examples
iprint_connectivity -node xspine_0.xdqr_0.xl850.osc_2
iprint_connectivity xspine_0.xdqr_0.xl850.osc_2 -print cc
iprint_connectivity -index 3
See Also
iprint_node_info
iprint_dcpath
Finds and prints the DC path information.
Syntax
iprint_dcpath -ith ival [-node node_name {node_name}]
[-at tval {tval}] [-file file_name]
or
iprint_dcpath -ith ival [-node node_name {node_name}]
[-period period_value [-start start_time]
[-end end_time]] [-file file_name]
ith ival Sets the current threshold value. The default is 50uA.
-node node_name Specifies the terminal node names of the DC current path.
{node_name} The DC path search starts from any node specified in this
node list and ends when it reaches either another node in
the list or a DC voltage source node. If you do not specify
a node, the CustomSim tool reports DC current paths
between any pair of voltage source nodes.
-at tval {tval} Specifies the specific time points at which the path
checking occurs.
-period When you specify the -period argument the DC path

period_value search occurs at integer multiples of period_value
beginning at the current time if you do not use the -start
argument.

H-2013.03
iprint_elem_info
-start start_time Specifies the first time that periodic path checking occurs.
If you do not use -start periodic checking starts at the
current time.
You can only use -start with the -period argument.
-end end_time Specifies that no path checking occurs past the

end_time. If you do not use -end path checking occurs
until the end of the simulation.
You can only use -end with the -period argument.
-file file_name Writes the DC path report to the specified file.
Description
The iprint_dcpath command searches for and reports DC paths. The DC
path search starts from any specified node and ends when the search reaches
either another node in the list or a DC voltage source node. If you do not
specify a node, the CustomSim tool reports the DC current paths between any
pair of voltage source nodes. The path is only reported through MOS and
resistor elements.
Examples
XA> iprint_dcpath -ith 1e-6
path 1 from vdd to 0 @ 1.04e-07s
xmos.mn (NMOS: lds=3.33804e-06

drain vdd 3
source xmos.n1 0.0530892
gate g 0.6
xmos.mn2 (NMOS: lds=3.33793e-06)
source 0 0
drain xmos.n1 0.0530892
iprint_elem_info
Prints the detailed element information for the given element names at the
specific time of activation.

H-2013.03
iprint_elem_info
Syntax
iprint_elem_info -elem element_name {element_name}
[-report brief] [-file file_name]
or
iprint_elem_info -index elem_index {elem_index}
[-report brief] [-file file_name]
-elem element_name Specifies the element name, which can

include wildcard characters.
-index elem_indexn Specifies element index.
-report brief Provides a brief version of the output that

reports only the element terminal
connectivity, voltage, and currents. Other
information is suppressed.
-file file_name Writes iprint_elem_info output to the

specified file.
Description
You can also provide a subcircuit instance as an element. In this case, the
CustomSim tool prints the subcircuit name, the list of its ports, and the voltages
on each port. The detailed element information includes:
■
Element name, element type, and model name
■
Element terminal connectivity
■
Element parameters and values
■
Element terminal voltages
MOSFET-specific information:
■ MOS logic state (ON/OFF)
■
MOS effective length and width (Leff and Weff)
■
MOS conductance (gds and gm)
■ MOS threshold voltage (Vth)
■
MOS Voltage-dependent diode capacitance (cbs and cbd)

H-2013.03
iprint_elem_info
■
MOS Voltage-dependent gate capacitance (cgs, cgb, and cgd)
■
MOS Ids current (Ids)
Examples
XA> iprint_elem_info [email protected]
[email protected] (203) Type=PMOS Model=PENH

D=X1.X001 (232) G=X1.N@1514 (130) S=VDD (14) B=VDD (14)
Vd=0.0108579 Vg=1.69226 Vs=1.69213 Vb=1.69213

Weff=11.9178u Leff=0.205123u PD=13.4u PS=13.4u AD=4.2u^2 AS=4.2u^2
Vt=-0.73418 OFF
Ids=-2.7808e-07u
gds=2.86161e-13 gm=6.111e-12
cgs=3.03919f cgd=3.03903f cgb=4.59196f cbs=6.99465f cbd=4.48262f
id=0.105008u ig=-0.0446823u is=0.000726083u ib=-0.0610515u
XA> iprint_elem_info X1.RI@5234
Elem=X1.RI@5234 (161) Type=R

N1=X1.N@5446 (195) N2=X1.N@5445 (194)
R=33
Vn1=1.69267 Vn2=1.69267
I=0.0036124u
Example 57
iprint_elem_info -elem x1.x2.m1
Example 57 prints information for element x1.x2.m1.
Example 58
iprint_elem_info -index 1 3 2
Example 58 prints information for element indices 1, 3, and 2.
Example 59
XA>iprint_elem_info x1
Elem=x1 Type=subckt subckt=mysub1
PORT 1 port=a - 11 (1) v=1
PORT 2 port=b - 12 (2) v=1
PORT 3 port=c - 13 (3) v=2.65
PORT 4 port=d - 14 (4) v=1

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iprint_exi
Example 59 prints subcircuit information and port voltages for a subcircuit

instance.
See Also
iprint_connectivity, iprint_node_info
iprint_exi
Prints elements with excessive currents.
Syntax
iprint_exi -inst inst_name {inst_name} [-ith ivalue]
[-file file_name] [-report report_value {report_value}]
-inst inst_name Specifies the hierarchical element names to

be searched. You can use wildcard
characters (*) in the instance names. The
set_wildcard_rule conventions apply.
-ith ivaule Specifies the current threshold that must be

exceeded for the element to be reported. The
default value is 50uA.
-file file_name Specifies the output file name.
-report report_value report_value can be:

{report_value} ■
subname to specify a list of subcircuit
names of the hierarchical instance
components to be printed in the output.
■
brief to report only element terminal
connectivity, voltages, and currents. Other
information is suppressed.
Description
iprint_exi reports the current through any device terminal that exceeds the
threshold. The following device types are checked and reported:
■
MOS
■
Resistor

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iprint_flash_cell
■
BJT
■
Diode
Examples
The output format for elements found that exceed the current threshold is the
same as iprint_elem_info. If you specify a list of subcircuit names with the
-report argument, the hierarchical element instance names have the
following general format:
Elem=X0.X1.X2...Xn.modelname
Subckt: X0=x0name X1=X1name X2=x2name ... Xn=Xnname
For example:
XA> iprint_exi -ith 1n xmos.m* -report subname
Elem=Xmos.mn (6) Type=NMOS Model=nch.7
D=vdd (5) G=g (3) S=Xmos.n1 (16) B=vb (4)
Vd=3 Vg=1.81293e-90 Vs=-0.00837316 Vb=1.81293e-90
M=1
Weff=2.016u Leff=0.948223u PD=2.365u PS=2.365u AD=0.351792u^2
AS=0.351792u^2 SA=0u SB=0u
Vt=0.19898 OFF
Ids=0.26352u
gds=5.38557e-10 gm=0
cgs=4.30157f cgd=0.416708f cgb=3.65854f cbs=1.20401f
cbd=0.487088f
id=0.26352u ig=-0.0663667u is=-0.00752308u ib=-0.189631u
Subckt: Xmos=mymos
iprint_flash_cell
Prints information for flash core cell elements.
Syntax
iprint_flash_cell -dvth value -inst inst_name
{inst_name} [-file filename] [-save save_filename]
-dvth value Specifies the minimum vth change for cells to

be printed.

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iprint_help
-inst inst_name Specifies the instance names. You can use

an asterisk (*) wildcard character to
represent all instances matching the pattern.
-file filename Specifies a file name to which the command

output is written.
-save save_filename Specifies a file name to which a command

file is written with the configuration command
to initialize the cells to their current state. You
can include this file to run subsequent
simulations.
Description
iprint_flash_cell identifies and reports the flash core cell instances from
specified instance names having a threshold voltage shift (-dvth) with either
of the following parameters:
■
Greater than or equal to the specified value if it is positive or zero.
■
Less than or equal to the specified value if it is negative or zero.
The reported Vth value is the current threshold voltage of the cell. The dVth
value is the change in threshold voltage and the delvto value is the initial
change in threshold voltage for the cell. The delvto value should correspond to
the delvto value from the instance parameter or from the set_flash_option
command.
Examples
XA> iprint_flash_cell -dvth 0 -inst *
XF0.MCELL, Vth=-1.0986, dVth=-2.8487, delvto=0.5
XF1.MCELL, Vth=-0.74198, dVth=-2.4921, delvto=-0
XF2.MCELL, Vth=-0.92028, dVth=-2.6704, delvto=0.25
iprint_help
Displays the syntax and a brief description of the specified interactive
commands.
Syntax
iprint_help -cmd command_name1 ... command_namen

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iprint_node_info
command_namen Specifies the interactive commands to be

displayed on the screen.
Examples
iprint_help iprint_node_info
This example prints information about the iprint_node_info command.
iprint_node_info
Prints the node voltage, node index, and simulation time for the given node
names. Each value is evaluated at the current simulation time, when the node
voltage is last updated.
Syntax
iprint_node_info -node node_name {node_name}
and
iprint_node_info -index node_index {node_index}
-node node_namen Specifies node name. Supports wildcard

characters.
-index node_indexn Specifies node index.
Examples
XA> iprint_node_info x1.sout
Node=X1.SOUT (225)
V=1.69417 V dV/dt=-0.00244323 V/ns t=1 ns
Example 60
iprint_node_info -node xalu3.xlatch2.q
Example 60 prints information for node xalu3.xlatch2.q.

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iprint_subckt
Example 61
iprint_node_info -index 1 3 2
Example 61 prints node information for node indices 1, 3, and 2.

See Also
iprint_connectivity, iprint_elem_info
iprint_subckt
Prints the list of hierarchical instance names for all instances of the specified
subcircuit. Note that this command does not support wildcard characters.
Syntax
iprint_subckt subckt_name
subckt_name Specifies the subcircuit name.
Examples
XA> iprint_subckt nand2
x1.x2.x3.xnand1
x1.x2.x3.xnand2
x1.x5.xnand1
iprint_time
Prints the current simulation time.
Syntax
iprint_time
N/A
Examples
iprint_time

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iprint_tree
iprint_tree
Prints information about the hierarchical instance tree. Only subcircuit
instances are displayed. If the instance list is omitted, it is assumed to be an
asterisk ( * ). The output can also be dumped to a file.
Syntax
iprint_tree -inst inst_list [-limit val]
[-a enable_value] [-def enable_value] [-file filename]
-inst inst_list Specifies an instance list. The underlying

hierarchy of instances matching the pattern
is printed.
-limit val Specifies that the hierarchical depth to which

the tree is printed. If not specified, this setting
defaults to 3.
-a enable_value Specifies that the full hierarchical name of

each instance is displayed.
-def enable_value Specifies that the subcircuit name is also

displayed.
-file filename Specifies that the command output is also

written to the named file.
Examples
XA > iprint_tree -limit 0 -a 1 -def 1
x1 (dco_xtl)
x2 (dco)
XA > iprint_tree x1* -limit 1 -a 1 -def 1

x1 (main)
x1.xadd_204_u1 (muxi21x4)
x1.xadd_204_u7 (nor2x3)

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Creates a voltage waveform output.
Syntax
iprobe_waveform_voltage -v node_name {node_name}
[-vn instance_name {instance_name}]
[-vall instance_name {instance_name}]
[-port enable_value] [-index index {index}]
[-delete enable_value]
-v node_name{ Specifies the node name at which the voltage is probed.

node_name}
-vn Specifies the name of the instance at which the voltage of

instance_name terminal n is probed, where n is a positive integer. Note this
argument applies only to instances not specified by
-subckt.
-vall Specifies the name of the instance at which the voltage of

instance_name all terminals are probed. Note this argument applies only to
instances not specified by -subckt.
-subckt Probes the nodes in all instances of the named subcircuit.

subckt_name If you specify this argument, the nodes or instances should
be in the subcircuit instance hierarchy level.
-limit level Specifies the hierarchy level down to which the voltage is
probed. When -subckt is specified, the -limit level is
relative to where the particular node is located in the
hierarchy. A value of 0 specifies the top level of the
subcircuit. The default for level is 3.
-port If you specify an enable_value value of 1, a wildcard

enable_value character matches the subcircuit port names.
-delete If enabled, removes the specified signals from the plot list.
enable_value

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-index index Writes the signals that match the specified indexes to the
{index} plot file.
Description
Probes the voltage on a node or on the pin of a primitive instance. The voltage
waveform is written to the output file in the format specified by the post option
in the netlist. Note that only the fsdb and wdf formats support adding new
waveforms to the file on the fly.
You can use wildcards (*) with the -v, -vn, and -vall arguments. When used
with -v, the port alias matching is controlled by the -port argument or the
iset_interactive_option setting. A -port specified with the command takes
precedence. The set_wildcard_rule setting also applies.
Long simulations, or simulations where some nodes have a high level of
If you use Custom WaveView to display the waveform file, you must close and
reopen the file to be able to see the voltages you have added.
Examples
Example 62
XA> iprobe_waveform_voltage x1.*
Example 62 adds probes for all nodes in instance x1. Wildcard matching is
influenced by set_wildcard_rule and iset_interactive_option.
Example 63
XA> iprobe_waveform_voltage * -delete 1
Example 63 deletes all voltage probes.
Example 64
XA> iprobe_waveform_voltage x1.* -level 2
Example 64 adds voltage probes for all nodes in instance X1 down to level 2 of
the hierarchy.

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iquit_sim
iquit_sim
Terminates the simulation.
Syntax
iquit_sim
N/A
Examples
iquit_sim
This example terminates the simulation.
irelease_node_voltage
Releases the node voltages from the values fixed by iforce_node_voltage.
When you specify this command, the simulation results determine the node
voltages.
Syntax
irelease_node_voltage -node node_name {node_name}
Examples
XA> irelease_node_voltage cn
The cn signal previously forced to a given value is released at the current time.
The simulation results determine the cn voltage value until the end of the run
unless a new iforce_node_voltage command is specified.
ireport_node_cap
Reports capacitance information for the specified nodes.

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ireport_node_cap
Syntax
ireport_node_cap -node node_name {node_name}
[-group group_name] [-limit limit_value]
[-report basic|detail]
-node node_name Reports capacitance for the node names you specify. You can
{node_name} use wildcard characters in the node names.
-group group_name Creates a group name for the nodes you specify with -node.
If you specify this option, all nodes for a report_node_cap
command are grouped together. The CustomSim tool reports
the capacitance information based on this group.
Use this option only for a flat, postlayout design.
-limit Specifies the hierarchy level down to which the CustomSim

limit_value tool reports the capacitance information. The default is 3.
-report Specifies the type of report to print. Use the basic keyword
basic|detail (the default) to print only the basic capacitance information.
Use the detail keyword to print a detailed report.
Description
The reported node capacitance information includes total node capacitance,
wire capacitance, gate capacitance of a MOSFET, and junction capacitance of
a MOSFET. You can specify multiple commands in a simulation. The
CustomSim tool processes each command separately.
report_node_cap outputs the capacitance information in a *.cap# file.
In a prelayout design, capacitance is reported as:
Cwire = Cdesign
In postlayout design, the CustomSim tool expands a single node from the
prelayout design into multiple nodes because of the RC parasitics. The
postlayout flow is divided into 2 scenarios:

H-2013.03
ireport_node_cap
■
A back-annotated postlayout.
■
A flat postlayout.
In the back-annotated postlayout flow, you can trace the connectivity back to
the prelayout design with the information from the prelayout netlist and the
back-annotation file:
*|NET na 0.00458507PF <-- Net Capacitance (CBAnet)
*|I (x02/mp:GATE x02/mp GATE I 4.8e-16 22.75 3.25) //
*|I (x02/mn:GATE x02/mn GATE I 2.4e-16 22.75 1.05) //
*|I (x01/mp:DRN x01/mp DRN B 0 8.45 3.25) // $llx=8.45
$lly=2.65 $urx=9.2 $ury=3.85 $lvl=7
*|I (x01/mn:DRN x01/mn DRN B 0 8.45 1.05) // $llx=8.45
$lly=0.75 $urx=9.2 $ury=1.35 $lvl=6
*|S (na:1 22.75 2.65) // $llx=22.55 $lly=2.65 $urx=22.95
$ury=2.65 $lvl=3
*|S (na:2 22.75 3.925) // $llx=22.55 $lly=3.85 $urx=22.95
$ury=4 $lvl=5
Cg1 na:1 0 4.33011e-17
Cg2 na:2 0 3.99892e-17
...
R158 na:1 x02/mp:GATE 4.8 $l=0.6 $w=0.4 $lvl=5
R159 na:1 na:3 30 $l=0.8 $w=0.4 $lvl=3
R160 x02/mp:GATE na:2 5.016 $l=0.675 $w=0.4 $lvl=5
R161 na:3 na:4 16.875 $l=0.5 $w=0.4 $lvl=3
R162 na:3 na:5 18.75 $l=0.5 $w=0.4 $lvl=3
R163 na:3 na:8 3.96 $a=0.04 $lvl=10
R164 na:4 na:6 3.96 $a=0.04 $lvl=1
...
R186 na:18 x01/mn:DRN 5.38888 $a=0.09 $lvl=12
R187 na:19 na:20 0.992002 $l=0.8 $w=0.5 $lvl=2
R188 na:19 na:21 13.1234 $l=6.45 $w=0.3 $lvl=2

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ireport_node_cap
R189 na:20 na:24 0.744002 $l=0.6 $w=0.5 $lvl=2

R190 na:20 x01/mp:DRN 5.38888 $a=0.09 $lvl=12
...
In back-annotated post-layout flow, the capacitance information is reported as:
Cwire = CBAnet + Cdesign
Based on the previous back-annotation file example:
Cgate = Cgate(x02/mp) + Cgate(x02/mn)
Cjunction = Cjunction(x01/mp) + Cjunction(x01/mn)
Cwire = CBAnet (0.00458507PF) + Cdesign
In a flat postlayout flow, the CustomSim tool treats all nodes as unique and
independent. To accurately calculate the capacitance information, you need to
group the nodes and then run report_node_cap. For example, see Figure 4.

H-2013.03
ireport_node_cap
Figure 4 Flat Postlayout Flow Example
In Figure 4, a prelayout node, BT, has been expanded into different nodes in
the postlayout. Because the postlayout netlist is flat, and there is no trace of
connectivity from the prelayout netlist and back-annotation flow, all nodes are
treated as unique and independent.
To accurately report the capacitance information, you need to tell the
CustomSim tool which nodes can be grouped together for report_node_cap
command to calculate the capacitance information. To group a list of nodes into
one group, use -group argument and list the names of nodes to be grouped:
BT_0, BT_1, BT_2, BT_3, BT_4, BT_5, BT_6, XPERI.BT_7, XCELL1.BTR,
XCELL2.BTR, XCELL3.BTR, and XCELL4.BTR and do the following steps:
1. Specify the following report_node_cap command.
report_node_cap -node BT_? XPERI.BT_7 XCELL?.BTR -group BT
This command groups all the specified node names into one group named
BT.
2. Assuming all parasitic capacitor has a value of 1 fF, the CustomSim tool
calculates the capacitance information is as:

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Cgate = Cgate(XPERI.MA1)
Cjunction = Cjunction(M2) + Cjunction(XCELL1.M1) +
Cjunction(XCELL2.M1)
+ Cjunction(XCELL3.M1) + Cjunction(XCELL4.M1) +
Cjunction(XPERI.MA1)
Cwire = (12 * 1 fF) + Cdesign
Cdesign = 0 pF
Writes the circuit operating point at the current time to the specified file.
Syntax
ireport_operating_point -file filename
[ -type ic | nodeset ] [-node node_name {node_name}]
-file file_name Specifies the report output file name.
-type ic | Specifies if the file is a .ic or a .nodeset file. The default is

nodeset .ic .
-node node_name Specifies that only those nodes matching the pattern are
{node_name written to the file. You can specify wildcards in the node
names. The wildcard match behavior is determined by the
alias matching rules. See the iset_interactive_option -port.
description.
Examples
Example 65
XA> ireport_op op_100us.ic
The previous example writes the op_100us.ic file with .ic statements for
the default nodes available in the database.

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isearch_node
Example 66
XA> ireport_op op_200us.nodeset -type nodeset
The previous example writes the op_100us.nodeset file with .nodeset

statement for the default nodes available in the database.
Example 67
XA> ireport_op file1 -node add*
The previous example writes the file1 file with .ic for those nodes matching
the add* pattern from the default node set.
isearch_node
isearch_node searches nodes in the netlist and reports various attributes.
Syntax
isearch_node -v [voltage_value]|-dv [dv_value]|
-dt [dt_value]|-conn [conn_value]
-v voltage_value Specifies the maximum voltage. Any node

with an absolute value higher than the
specified voltage_value is reported. If
you do not specify a value, the CustomSim
tool reports the node with the highest voltage
absolute value. The voltage_value unit is
volts.
-dv dv_value Specifies the maximum voltage change. Any

node with a voltage change larger than the
specified dv_value is reported. f you do not
specify a value, the CustomSim tool reports
the node with the highest voltage change.
The dv_value unit is seconds.

H-2013.03
isearch_node
-dt dt_value Specifies the maximum time step. Any node

with a time step smaller than the specified
dt_value is reported. f you do not specify a
value, the CustomSim tool reports the node
with the smallest time step value. The
dt_value unit is seconds.
-conn conn_value Returns the list of nodes that have more

connections than the specified value. If you
do not specify a value, it lists the most
connected node in the circuit.
Description
This command searches the nodes in the netlist and reports nodes with:
■
The highest voltage.
■ All nodes with a voltage that exceeds the specified value.
■
The highest voltage change.
■
All nodes with a voltage change that exceeds the specified value.
■ The nodes with the minimum time step.
■
All nodes with a time step less than the specified value.
■
The most connected node in the netlist.
isearch_node only counts connections to elements. A connection to a
dangling subcircuit port does not count as a connection. In the following
example, node c is connected only once to the vc voltage source.
.subckt dangling a
.ends
vc c 0 dc=1
xc c dangling
xc2 c dangling
The connected node output provides the name of the subcircuit that contains
the node, the primary node name and node index, the number of connections,
and a flag to indicate if a voltage source is connected to the node. For example:
XA > isearch_node -conn

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isearch_node
Highest connectivity node: Subckt=con20 Node=a (1)

#Conn=21 Vsrc=0
XA > isearch_node -conn 10

High connectivity node: Subckt=TLC Node=0 (0) #Conn=14
Vsrc=1
High connectivity node: Subckt=TLC Node=a (1) #Conn=10
Vsrc=1
High connectivity node: Subckt=con20 Node=a (1) #Conn=21
Vsrc=0
High connectivity node: Subckt=con20 Node=c (3)#Conn=21
Vsrc=0
Examples
isearch_node -v
Maximum V=4.567 sy nofr vcc_int
The previous example prints the node with the maximum voltage.
XA> isearch_node -v 2.5
V=3 at node x8.qb
V=3 at node x8.CKn
V=3 at node vcc
V=3 at node d[2]
The previous example reports all nodes with a voltage absolute value greater
than 2.5V.
XA> isearch_node -dv
Maximum DV=0.276185 at node x2.x1.n2
The previous example reports the node with the largest voltage change.
XA> isearch_node -dv 1e-3
DV=0.00243276 at node x3.x9.n1
DV=0.00230895 at node x3.x8.n1
The previous example reports all nodes with a voltage change greater than
1mV.
XA> isearch_node –dt
Minimum time_step=33ps at node x4.x1.n2 , DV=0.272122
The previous example reports the node with the minimum time step.

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iset_break_point
XA> isearch_node –dt 2000p

time_step=1934ps at node x3.x8.n1, DV=0.00230895
time_step=1934ps at node x1.x9.n1, DV=0.00144889
The previous example reports the nodes with a time step smaller than 2000ps.
XA > isearch_node -conn
Highest connectivity node: Subckt=con20 Node=a (1) #Conn=21 Vsrc=0
The previous example reports the most connected node in the circuit.
XA > isearch_node -conn 10
High connectivity node: Subckt=TLC Node=0 (0) #Conn=14 Vsrc=1
High connectivity node: Subckt=TLC Node=a (1) #Conn=10 Vsrc=1
High connectivity node: Subckt=con20 Node=a (1) #Conn=21 Vsrc=0
High connectivity node: Subckt=con20 Node=c (3)#Conn=21 Vsrc=0
The previous example reports all nodes that have 10 or more connections in
the circuit.
iset_break_point
Pauses the simulation at the specified time.
Syntax
iset_break_point -at time[unit]
time[unit] Specifies the time and unit at which the

simulation is paused. White space is not
allowed between time and unit. The
default for unit is second, if it is not
specified.
Examples
iset_break_point -at 10n
This example pauses the simulation at 10ns.

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Lets you abort a simulation in progress and output the power report up to the
current simulation time.
Syntax
iset_diagnostic_option -report_power enable_value
-report_power enable_value This command only works with the

report_power command.
Examples
report_power -label vdd_1u_2u -by_node vdd -from 1u -to 2u
xa net.sp -c cmd -intr 1u
XA> iprint_time
1us
XA> cont 500n
XA> iprint_time
1.5us
XA> iset_diagnostic_option -report_power 1
XA> iquit
The CustomSim tool completes the vdd_1u_2u power report using the 1.5us
as the window end time. the CustomSim tool needs to report the time value that
was used to close the window for the calculation.
Controls the wildcard matching behavior in interactive mode for hierarchy and
signal alias names. In interactive mode, this command overrides the wildcard-
matching hierarchy set by the set_wildcard_rule on page 169 batch mode
command.
Syntax
iset_interactive_option -match* one|all
[-port enable_value] [-tcl enable_value]
[-tclbuf enable_value]

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-match* one|all Specifies whether the * wildcard character

matches the hierarchical delimiter for one or
all levels of hierarchy.
-port enable_value Specifies whether the * wildcard character

matches the signal alias names.
-tcl enable_value Specifies whether the full Tcl interpreter is

enabled. This option is the same as the -tcl
command line argument. For more
information about Tcl, see Enabling Tcl Mode
on page 3.
-tclbuf enable_value Specifies if data from interactive mode

commands is put in Tcl memory. Set
-tclbuf 0 to avoid Tcl memory overflow in
large circuits (default). To run Tcl scripts and
enable data dumping, you need to set
-tclbuf 1.
Examples
XA> imatch_node x1.*
7 X1.g
8 X1.ha
9 X1.x2.b1
This example matches 3 nodes with the x1.* pattern.

XA> iset_interactive_option -match* one

7 X1.g
8 X1.ha

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iset_save_state
XA> iset_interactive_option -match* one -port 1
0 X1.6
0 X1.0
1 X1.a
1 X1.3
2 X1.4
3 X1.5
7 X1.g
8 X1.ha
iset_save_state
Save a simulation at the specified time point.
Note: To use iset_save_state you must also set set_save_state in

your command file.
Syntax
iset_save_state -time time_value
-time time_value Specifies the time point at which the state is

saved to restore a simulation.
iset_zstate_option
Sets the conducting rules for the icheck_node_zstate command.
Syntax
iset_zstate_option [-rule rule_value {rule_value}]
[-diode_vh value]
[-idsth ids_value]
[-vbeth vb_value]
[-report report_value {report_value}]

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iset_zstate_option

NMOS:
■ Vgs > Vth (rule=1)
■
■
Vg > VDD-0.1 (rule=3)
PMOS:
■ Vgs < Vth (rule=1)
■
■
Vg < 0.1 (rule=3)
-diode_vth value Specifies the threshold for a diode to be considered

conducting when Vac exceeds the specified value. If you
specify a value less than 0, diode is considered as not
conducting. The default is 0.2V.
-idsth ids_value Specifies the threshold for a MOSFET to be considered

-vbeth vb_value Specifies the threshold for BJT to be considered

-report You can specify the following keywords:

report_value ■
node lists high impedance nodes.
{report_value} ■
channel lists all channel-connected devices for the
node.
■
gate lists all gate-connected devices for the node.
The default is node.
Description
This interactive command specifies the conducting rules so that the
CustomSim tool can diagnose specified nodes staying in a high-impedance
(floating) state.

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iset_zstate_option

Device Rule
NMOS ■ Vgs > Vth (-rule 1)

■
Ids > idsth (-rule 2)
■ Vg > VDD-0.1 (-rule 3)
■
PMOS Vgs < Vth (-rule 1)
■
Ids > idsth (-rule 2)
■ Vg < 0.1 (-rule 3)
NPN Vbe > vbeth
PNP Vbe < -vbeth
Diode Forward-biased.
Resistor Always conducting.

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iset_zstate_option

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A
A Converting WDF and FSDB Waveform Output File
Formats
This convert2out utility provides a post-processing capability to convert the

specified signals from the .wdf or .fsdb waveform formats to the .out waveform
format.
Using the convert2out Utility

Note: The convert2out syntax the arguments are order-dependent.
convert2out
Converts .wdf or .fsdb waveform files to .out format.
Syntax
convert2out -i input_filename {[-s signal_filename]
[-o output_dir/[output_filename]]} [-compress z|gz|0]
or
convert2out [-h|-help] [-v|-version]
-i input_filename Specifies the name of the input file in .wdf or .fsdb

format. The convert2out utility automatically determines
the input file format.

H-2013.03
Appendix A: Converting WDF and FSDB Waveform Output File Formats
-s signal_filename Specifies the signal file names. Each signal file contains a
list of signals to be converted. By default, all the signals in
the input file are converted. Table 17 describes the signal
file format.
This argument is order-dependent. All signals specified in
a signal file are converted in an output file specified by the
–o argument. If you do not specify a –o argument, the
default file name is:
input_filename.signal_filename.out.
You can specify wildcards in the signal names. See the
Using Wildcards section for the supported patterns. The "*"
wildcard character follows the rule defined by the
set_wildcard_rule command. You can specify one
set_wildcard_rule command in a signal file.
You can use the set_sim_case command to control case
sensitivity:
set_sim_case [-case upper|lower|sensitive]
upper specifies to convert all nodes to upper case in the
.out file.
lower specifies to convert all nodes to lower case in the
.out file.
sensitive specifies to keep the same case as in the
FSDB or WDF waveform file.
The default behavior is to output the same case as in the
FSDB or WDF waveform file. Note that you must specify
set_sim_case and set_wildcard_rule before the signal list
in the signal file.

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-o output_dir/ Specifies the name of the output directory and output file
output_filename name. The output file contains the signals specified in the
signal file in .out waveform format. Note that you cannot
repeat the same file name in one convert2out
command. The default output file name is:
input_filename.signal_filename.out.
The default of output directory is the current running
directory. If the specified output directory does not exist,
convert2out creates it.
This argument is order-dependent. The output file only

contains the list of signals in the signal file specified by –s
in the previous argument. If you do not specify –s in the
previous argument, the default rule of –s is applied, which
means all signals are converted.
-compress z|gz|0 Specifies the type of compression applied to the .out file:
■ z enables compression with the UNIX compress utility.
■
gz enables compression with the GNU gzip utility.
■ 0 disables compression.
Compression applies to all output files and cannot be used
for individual files.
-help Prints help information.
-version Prints version information.
Description
All of the specified signals to be converted must be presented as they exist in
the waveform file. The convert2out utility does not support arithmetic
functions. Any necessary arithmetic functions need to be done in the waveform
viewer tool.
Table 17 shows the signal file format.
Table 17 Signal File Format
Signal Access Function Description
v(node) Voltage of a node.

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Table 17 Signal File Format
Signal Access Function Description
vn(instance) Voltage of a terminal n of an instance where n is an

integer greater than or equal to 1; or d, g, s, b for
MOSFET and c, b, e, s for BJT.
v(node1, node2) Expression of the difference voltage of two nodes.

The utilities do not do any arithmetic calculations.
V(node1, node2) must be presented in the original
waveform file already.
i(instance) Current flowing into the first terminal of an instance.
in(instance) Current flowing into an instance at terminal n where

n is an integer greater or equal to 1; or d, g, s, b for
MOSFET and c, b, e, s for BJT.
isub(subckt_port) or Total current flowing into the subcircuit port.

x(subckt_port)
Parameter Expression of a parameter.
Note: The node, instance, subckt_port and parameter functions are

case-sensitive. The v(), vn(), i(), in(), isub(), and x() functions are
always case-insensitive.
Here is a sample signal file:
V(1)
V(sampling)
V(x1.sout)
I(VDD)
I(x1.m@2899)
Isub(x1.VDD)
V(1,2)
X(x2.VDD)
I3(x1.m@1233)
Id(x1.m@1245)
testout
Examples
Example 68
convert2out –i waveform.wdf –s sig1 –o out1.out –s sig2 –o out2.out

H-2013.03
Converts the signals in the sig1 file to an out1.out file and the signals in the
sig2 file to an out2.out file.
Example 69
convert2out –i test.fsdb
Converts all the signals in the test.fsdb input file to a test.fsdb.out file.
Example 70
convert2out -i test.fsdb –s testsig1 –s testsig2 –s testsig3 –o
testout.out –s testsig4
Converts: all the signals in the testsig1 to test.fsdb.testsig1.out, all

the signals in testsig2 to test.fsdb.testsig2.out, all the signals in
testsig3 to testout.out, and all the signals in testsig4 to
test.fsdb.testsig4.out.
Example 71
convert2out –i pll.wdf –s sig1 –s sig2 –o sig2.out –o out.out –
o out1.out
Converts: all the signals in the sig1 to pll.wdf.sig1.out, all the signals in
sig2 to sig2.out, all the signals in pll.wdf to out.out, and all the signals
in pll.wdf to out1.out.
Example 72
convert2out –i test.fsdb –o out1.out –o out1.out
Generates an error messages because two output files have the same name
(out1.out).
Example 73
convert2out –i test.fsdb –o TEST/
Converts all the signals in the test.fsdb file to a TEST/test.fsdb.out

file.
Example 74
convert2out –i test.fsdb –o TEST/test.out
Converts all the signals in the test.fsdb file to a TEST/test.out file.

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Example 75
convert2out –i waveform.wdf –s sig1 –o out1.out –s sig2 –o out2.out
–compress z
Converts: all the signals in the sig1 file to a out1.out.out file and all the
signals in the sig2 file to a out2.out.z file.

H-2013.03
Index
A iprint_tree 198
absolute voltage 207 iquit_sim 201
isearch_node 207
alias 176, 182, 201, 206
iset_break_point 210, 211, 213
load_ba_file 37
B load_vector_file 44
back-annotation map_ba_terminal 45, 47
commands 7 netlist control 7
controlling connectivity error responses 12, 15, output control 7
16, 19, 22, 26, 29, 32, 176 post-layout and back-annotation 7
specifying a file for 37 probe_waveform_current 48
terminal name mapping 45, 47 probe_waveform_logic 51
break points probe_waveform_voltage 54, 199
listing 183, 184, 185 report_power 70
removing 182 set_ams_view 86, 88, 89, 94
setting 210, 211, 213 set_ccap_level 95, 98, 100, 110, 141
set_dc_option 101
C set_duplicate_rule 105, 107
set_floating_node 108, 110, 112
case-sensitivity 1
set_measure_format 113, 129, 131
circuits, open 146 set_message_option 114
commands
set_resistor_threshold 146
alias 176, 182, 201, 206
set_sample_point 146, 150
categories 6
set_sim_level 152, 156, 158
common definitions 4
set_wildcard_rule 169
diagnostic 6
speed control 7
enable_ba_error_net 12, 15, 16, 19, 22, 26, 29,
use_mos_instpar 137, 139
32, 176
using a script file 2
enable_print_statement 35
using Tcl mode 3
enable_value 4
vector stimulus 7
iclose_log 180
icontinue_sim 180 complexity vs. speed trade-off 152, 156, 158
idelete_break_point 182 connectivity errors, controlling 12, 15, 16, 19, 22,
ilist_break_point 183, 184, 185 26, 29, 32, 176
including in netlist 2 connectivity information 188
interactive mode 3 coupling capacitor tolerance, setting 95, 98, 100,
with Tcl 3 110, 141
iopen_log 187 customer support xi
iprint_connectivity 188
iprint_elem_info 190, 193, 194 D
iprint_help 195
debugging mode 2
iprint_node_info 196, 197
iprint_time 197 diagnostic commands 6
223
Index
E
E isearch_node 207
Eldo iset_break_point 210, 211, 213
.option statement 2
print statement 35 L
element information 190, 193, 194
load_ba_file 37, 43
enable_ba_error_net 12, 15, 16, 19, 22, 26, 29,
load_vector_file 44
32, 176
LOD models, handling 137, 139
enable_print_statement 35
log file 187
enable_value, possible values for 4
controlling the number of messages 114
enhanced look-up table 137, 139
look-up table methods 137, 139
H M
help for interactive commands 195
map_ba_terminal 45, 47
hierarchical instance tree 198
.measure file output format 113, 129, 131
HSPICE
.option statement 2 measurements, precise sampling points 146, 150
print statement 35 models, multiple definitions 105
vector stimulus file 44 module definition, using Verilog-A 86, 88, 89, 94
MOFSET-specific information 191
I
iclose_log 180 N
icontinue_sim 180 netlist control commands 7
idelete_break_point 182 netlist, including commands in 2
ilist_break_point 183, 184, 185 node connectivity information 188
inst_name 5 node information 196, 197
instance definition, using Verilog-A 86, 88, 89, 94
instance tree 198 O
instance_spec values 4 open circuits, threshold for 146
-inter flag 3 .option statement 2
interactive commands options statement 2
creating aliases for 176, 182, 201, 206
output control commands 7
help 195
output file format 113, 129, 131
interactive debugging 2
interactive mode 3
closing the log file 180 P
log file 187 partitioning instance/module definitions 86, 88, 89,
with Tcl 3 94
iopen_log 187 periodic measurements 146, 150
iprint_connectivity 188 post-layout commands 7
iprint_elem_info 190, 193, 194 post-layout, specifying a back-annotation file 37
iprint_help 195 power consumption 70
iprint_node_info 196, 197 print statements in Eldo or HSPICE netlists 35
iprint_time 197 probe_waveform_current 48
iprint_tree 198 probe_waveform_logic 51
iquit_sim 201 probe_waveform_voltage 54, 199
224
Index
R
R stress effects, handling 137, 139

report_power 70 subcircuit definition, using Verilog-A 86, 88, 89, 94
reporting DC results 101 subcircuit port names, multiple names 105
resistors, thresholds for shorting or for open circuits subcircuits, multiple definitions 105
146 subckt_name 5
support xi
S
sampling point 146, 150 T
script file, issuing commands from 2 Tcl mode 3
set_ams_view 86, 88, 89, 94 interactive mode with 3
set_ccap_level 95, 98, 100, 110, 141 terminal name mapping 45, 47
set_dc_option 101 tolerances, setting for coupling capacitors 95, 98,
set_duplicate_rule 105, 107 100, 110, 141
set_floating_node 108, 110, 112 transient simulation, continuing 180
set_measure_format 113, 129, 131
set_message_option 114 U
set_resistor_threshold 146 use_mos_instpar 137, 139
set_sample_point 146, 150
set_sim_level 152, 156, 158
V
set_wildcard_rule 169
VCD stimulus file 44
shorting resistors 146
simulation vector stimulus commands 7
continuing a transient simulation 180 vector stimulus file 44
current time 197 Verilog A
switching between SPICE and Verilog-A
level of 152, 156, 158
definitions 86, 88, 89, 94
pausing 210, 211, 213
terminating 201
Spectre W
options statement 2 warning messages 114
speed control commands 7 waveform
speed vs. complexity trade-off 152, 156, 158 generating node logic values 51
STI models, handling 137, 139 probing current through instance pins 48
stimulus file 44 probing voltage 54, 199
stop points wildcard rules 169
listing 183, 184, 185
WPE models, handling 137, 139
removing 182
225
Index
W
226

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CustomSim™ Command

ii CustomSim™ Command Reference

1. Using CustomSim Commands and Options . . . . . . . . . . . . . . . . . . . . . . . . 1

2. CustomSim Batch Command Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3. CustomSim Interactive Command Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . 175

A. Converting WDF and FSDB Waveform Output File Formats . . . . . . . . . . . 217

This manual describes the Synopsys CustomSim™ batch and interactive

CustomSim™ Command Reference ix

Courier Indicates command syntax.

Italic Indicates a user-defined value, such as object_name.

include_enclosing = true | false

[] Denotes optional parameters, such as:

... Indicates that parameters can be repeated as many times as

| Indicates a choice among alternatives, such as

\ Indicates a continuation of a command line.

/ Indicates levels of directory structure.

Ctrl+C Indicates a keyboard combination, such as holding down the

x CustomSim™ Command Reference

{} Indicates a definition that can be repeated as many times as

Contacting the Synopsys Technical Support Center

CustomSim™ Command Reference xi

• Find other local support center e-mail addresses at

xii CustomSim™ Command Reference

Describes how to use CustomSim commands and options.

This chapter describes:

Using CustomSim Commands

CustomSim™ Command Reference 1

Using a Command Script File

Using Commands Within the Netlist

Using Commands During Interactive Debugging Mode

2 CustomSim™ Command Reference

Interactive mode with Tcl Commands

Enabling Tcl Mode

CustomSim™ Command Reference 3

toggled on-and-off during a session—see Table 1.

Character Tcl ON behavior Tcl OFF behavior

$ Variable substitution Literal $

[ ] Command substitution Literal [ ]

\ Backslash substitution Same as Tcl ON

“ ” Argument grouping Same as Tcl ON

{ } Argument grouping Same as Tcl ON

# Comment if first character on Same as Tcl ON

; End of command delimiter Same as Tcl ON

Common Syntax Definitions

Several commands use the instance_spec argument. The instance_spec

4 CustomSim™ Command Reference

inst_name The name of the instance to which the command

subckt_name The name of the subcircuit to which the

Example 2 applies a command to all instances of the subcircuit pll:

Example 3 applies a command to all MOSFET transistor instances in the

CustomSim™ Command Reference 5

Example 4 applies a command to all instances X1 and X2 in subcircuits sub1

An equivalent instance_spec to that previously shown:

Command Category Command

6 CustomSim™ Command Reference

Table 3 CustomSim command categories

Command Category Command

Netlist Control keep_top_element

Output Control enable_print_statement