md6752 Ds en
md6752 Ds en
md6752 Ds en
Description Package
The MD6752 is a fully digital-controlled power SOP28
supply IC, which incorporates a bridgeless PFC control
circuit and an LLC current-resonant circuit. The PFC
circuit, driven by continuous conduction mode (CCM),
is controlled with frequencies suitable for applied input
voltages and loads. The IC incorporates current mode
for controlling constant voltages in the LLC stage and a
floating drive circuit that drives an external high-side
power MOSFET, in addition to functionally-rich
protections. These digitally controlled strategies allow
application-specific optimal settings. Compared to
conventional analog control circuits, the IC can achieve
more cost-effective, high-efficient, yet low-noise power
systems with fewer external components. Not to scale
Features Applications
● Fully Digital-controlled PFC and LLC Current- For devices requiring high power supplies such as:
resonant Circuits
● Soft Start ● Audiovisual Equipment
● Bridgeless PFC Circuit ● Office Automation Equipment (e.g., Server,
● Continuous Conduction Mode (CCM) PFC Control Multifunction Printer)
● Current Mode LLC Control ● Industrial Equipment
● Protections Include: ● Communication Equipment
PFC 4 U1 25 VOUT+
gate VGP A0
5 24
VCC VGL
6 23
MD6752
BASE SCID
7 22 Debug
GND GPIO04
8 21
AVCC VOCM
9 20
DVCC GPIO01
10 19
VREF GPIO03
11 18
CS GPIO02
12 17
VSEN VCORE
13 16
FB CM
14 15
VOUT-
Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Absolute Maximum Ratings----------------------------------------------------------------------------- 4
2. Electrical Characteristics -------------------------------------------------------------------------------- 5
3. Block Diagram --------------------------------------------------------------------------------------------- 9
4. Pin Configuration Definitions ------------------------------------------------------------------------- 10
5. Typical Application ------------------------------------------------------------------------------------- 11
6. Physical Dimensions ------------------------------------------------------------------------------------ 12
7. Marking Diagram --------------------------------------------------------------------------------------- 12
8. Operational Description ------------------------------------------------------------------------------- 13
8.1. General Description ------------------------------------------------------------------------------- 13
8.2. Pin Descriptions ----------------------------------------------------------------------------------- 13
8.2.1. A0 ----------------------------------------------------------------------------------------------- 13
8.2.2. A2 ----------------------------------------------------------------------------------------------- 13
8.2.3. GND and PGND ----------------------------------------------------------------------------- 13
8.2.4. VGP -------------------------------------------------------------------------------------------- 13
8.2.5. VCC -------------------------------------------------------------------------------------------- 14
8.2.6. DVCC and BASE ---------------------------------------------------------------------------- 14
8.2.7. AVCC ------------------------------------------------------------------------------------------ 14
8.2.8. VREF ------------------------------------------------------------------------------------------ 14
8.2.9. CS----------------------------------------------------------------------------------------------- 15
8.2.10. VSEN ------------------------------------------------------------------------------------------ 15
8.2.11. FB----------------------------------------------------------------------------------------------- 15
8.2.12. CM --------------------------------------------------------------------------------------------- 15
8.2.13. VCORE ---------------------------------------------------------------------------------------- 15
8.2.14. GPIO01 to GPIO04 ------------------------------------------------------------------------- 15
8.2.15. VOCM ----------------------------------------------------------------------------------------- 15
8.2.16. SCID ------------------------------------------------------------------------------------------- 16
8.2.17. VGL and VGH ------------------------------------------------------------------------------- 16
8.2.18. VB and VS ------------------------------------------------------------------------------------ 16
8.3. Startup Operation --------------------------------------------------------------------------------- 17
8.4. Soft Start Function -------------------------------------------------------------------------------- 17
8.5. AC Power Supply Input Undervoltage Lockout,
AC Power Supply Input Off-state Detection Function ------------------------------------- 17
8.6. VCC Pin Overvoltage Protection--------------------------------------------------------------- 18
8.7. PFC Overcurrent Protection, PFC Overload Protection ---------------------------------- 18
8.8. PFC Overvoltage Protection -------------------------------------------------------------------- 19
8.9. PFC Undervoltage Protection ------------------------------------------------------------------- 19
8.10. LLC Constant Voltage Control ----------------------------------------------------------------- 19
8.11. LLC Dead Time ----------------------------------------------------------------------------------- 20
8.12. LLC High-side Driver Undervoltage Lockout ----------------------------------------------- 21
8.13. LLC Overcurrent Protection, LLC Overload Protection --------------------------------- 21
8.14. Thermal Shutdown -------------------------------------------------------------------------------- 21
9. External Components ---------------------------------------------------------------------------------- 22
9.1. Resonant Transformer --------------------------------------------------------------------------- 22
9.2. Inductor in PFC Stage ---------------------------------------------------------------------------- 22
9.3. Power MOSFET ----------------------------------------------------------------------------------- 22
9.4. PFC Boost Diode (D1, D2) ----------------------------------------------------------------------- 22
9.5. Input Filter ----------------------------------------------------------------------------------------- 22
9.6. Output Capacitor (C51) -------------------------------------------------------------------------- 22
(1)
The AVCC pin is the 3.3 V power supply output pin dedicated for the internal LSI chip. Do not apply external
voltage to this pin.
(2)
Electric potential difference between the AVCC and DVCC pins should be maintained within ±0.3 V(t > 1 ms).
(3)
Refers to an analog input pin for 3.3 V systems.
(4)
The VCORE pin is the 1.8 V power supply output pin dedicated for digital circuits of the internal LSI chip. Do not
apply external voltage to this pin.
(5)
Should be rated from −0.3 V to 2.4 V when t < 1 ms (e.g., at startup).
(6)
Refers to a digital output pin for 3.3 V systems.
2. Electrical Characteristics
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, VCC = 17 V.
The checkmark in the Chg. column indicates that the item is dedicated GUI-changeable. In addition, the characteristic
value in this column is a reference value.
Parameter Symbol Conditions Pin Min. Typ. Max. Unit Chg.
Startup Circuit, Circuit Current
Operation Start Voltage VCC(ON) 6–8 13.0 14.0 15.0 V
(1)
Operation Stop Voltage VCC(OFF) 6–8 7.4 8.3 9.2 V
Circuit Current in Operation ICC(ON) 6–8 ― 1.8 4.0 mA
Circuit Current in Non-
ICC(OFF) VCC = 11 V 6–8 ― 0.5 1.0 mA
operation
VCC Pin Protection Release
VCC(P.OFF) 6–8 7.4 8.3 9.2 V
Threshold Voltage(1)
Circuit Current in Protection
ICC(P) VCC = 10 V 6–8 ― 0.5 1.0 mA
Operation
VCORE Pin Supply Voltage VCORE 16–8 1.72 1.80 1.88 V
SCID Pin High Level Detection
VSCID_IH 22–8 2.0 ― ― V
Voltage(2)
SCID Pin Low Level Detection
VSCID_IL 22–8 ― ― 0.8 V
Voltage(2)
3.3 V Analog Internal Regulator VAVCC 9–8 3.233 3.300 3.366 V
3.3 V Digital Internal Regulator VDVCC 10–8 3.135 3.300 3.465 V
External Transistor Drive
VBASE IBASE = −1 mA 7–8 3.6 ― 4.4 V
Voltage for DVCC Pin
VSEN Pin Input UVP
VSEN(OFF) 13–8 0.43 0.47 0.51 V ✓
Threshold Voltage
VSEN Pin Input UVP Release
VSEN(ON) 13–8 0.52 0.56 0.60 V ✓
Voltage
VSEN Pin AC Input Voltage
VSEN(AC_OFF) 13–8 0.16 0.19 0.22 V ✓
Off-state Detection Voltage
Delay Time of VSEN Pin Input
tVSEN(OFF) 13–8 9.5 10.0 10.5 ms ✓
UVP Detection
Delay Time of VSEN Pin AC
Input Voltage Off-state tVSEN(AC_OFF) 13–8 21.8 23.0 24.2 ms ✓
Detection
PFC Stage
VCC = 17 V,
PFC Drive Current (Source) IGP(SRC) VGP = 0 V
5–4 ― −500 ― mA
VCC = 17 V,
PFC Drive Current (Sink) IGP(SNK) VGP = 17 V
5–4 ― 1 ― A
CS Pin OCP Threshold Voltage
VCS(LO) VIN = 90 VAC 12–8 1.60 1.69 1.78 V ✓
(Low)
(1)
VCC (OFF) = VCC (P.OFF)
(2)
Guaranteed by design.
(3)
See Figure 2-2.
(4)
See Figure 2-1.
(5)
Refers to voltage between the GND pin and all the following pins: GPIO02, GPIO03, GPIO01, GPIO04.
(6)
Guaranteed by design.
4
4
ANEX0/1/2* Pin Input
3 3
Voltage (V)
2 2
1 1
0 0
-2 -1 0 1 2 3 4 -2 -1 0 1 2 3 4
A2 Pin Input Voltage (V) A0 Pin Input Voltage (V)
* Indicates voltages inside the IC; see the block diagram in Section 3.
3. Block Diagram
NC 1 26 VB
MIC1: Driver
A2 3 Level Shift
28 VGH
PGND 4
P_GND
VCC
VBUV(ON) /
VGP 5 VBUV(OFF) 27 VS
VCC
P_GND
23 VGL
VCC 6 P_GND
Start/Stop,
BASE 7 OVP, TSD, REG Main Control Logic
Level Shift,
VG_LLC_H
VG_LLC_L
Clamp
VG_PFC
Level
GND
Shift
24 A0
GND 8 A2_2 A2_1 A0_0 AVCC33 DVCC33
GPIO12
GPIO10
GPIO13
AVCC 9 AVCC
MIC2: MCU (MD6603)
DVCC 10 DVCC
VREF 11 ANEX10
CS 12 ANEX3
ANEX5 ANEX4
VSEN 13 ANEX9 GPIO21 GPIO20 VCORE GPIO02 GPIO03 GPIO01 GPIO05 GPIO04 SCID
14 15 16 17 18 19 20 21 22
FB CM VCORE GPIO02 GPIO03 GPIO01 VOCM GPIO04 SCID
5. Typical Application
C1 L1 C2 L2 D1
VAC L3 D2
L4 D7 D8 L5
D4 D3 DZ1 R7 DZ2
R8
C3
C6 C7
Q1 D5 D6 Q2
R1 R4 C5
C4
R3 R2 R5 R6
D9 C8 C9 D10
R24
C25
R23
R25
R21 PC1
Q6
6. Physical Dimensions
● SOP28
NOTES:
● Dimension is in millimeters.
● Pb-free
7. Marking Diagram
28
MD675 2
Part Number
S KY MD X XX
Lot Number:
X XX X Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N, or D)
1 D is the period of days represented by:
1: the first 10 days of the month (1st to 10th)
2: the second 10 days of the month (11th to 20th)
3: the last 10–11 days of the month (21st to 31st)
Control Number
8.2.8. VREF
8.2.5. VCC As shown in Figure 8-3, the output voltage of the PFC
This is the power supply pin for the built-in control stage, VOUT(PFC), divided by the detection resistors is
MICs, and is connected to an external power supply. applied to the VREF pin. Signals input to the VREF pin
When the VCC pin voltage increases to VCC(ON) or more, are used for the constant voltage control in the PFC
the IC starts operating. When the VCC pin voltage stage, the overvoltage protection (Section 8.8), and the
decreases to VCC(OFF) or less, the IC stops operating. This undervoltage protection (Section 8.9). VOUT(PFC) is
sequence of operations is the VCC pin undervoltage determined by the detection resistors, R12 to R16, and
lockout (VCC_UVLO). In addition to this function, the can be calculated by the equation below:
VCC pin also has the VCC pin overvoltage protection
(VCC_OVP). R REF1
VOUT(PFC) = ( + 1 ) × VREF . (1)
Section 8.3 describes the startup operation of the IC; R REF2
Section 8.6 provides more details on the VCC_OVP. To
prevent malfunction induced by supply ripples or other Where:
factors, connect 0.01 μF to 0.1 μF ceramic capacitors, VREF is the VREF pin threshold voltage (2.10 V),
C11 and C12, between the VCC and PGND pins, and RREF1 is the combined resistance of the resistors R12 to
between the VCC and GND pins, respectively, with a R15, and
minimal length of traces. RREF2 is the resistance of R16 (≈ 10 kΩ to 68 kΩ).
R11 C12 D3 L3 D2 C3
C2 R12
7 R13
Q5 BASE D4 Q1
10 R14
DVCC Q2
R17
9
AVCC R15 U1
R18
16 11
C14 VCORE VREF
C13 R19
R16
C17 8 GND C15
R20
13
VSEN
R21 C24 8 GND
Figure 8-2. Power Stage and Its Peripheral Circuit
8.2.9. CS C3
D14 R32
This pin serves as a drain current detector of the 28
Q3
C2 L2 D1 PC1 C16
8.2.13. VCORE
Figure 8-4. CS Pin and Its Peripheral Circuit
The VCORE pin is the internal 1.80 V power supply
pin. The capacitor C17 should have a capacitance of
8.2.10. VSEN 0.1 μF. Do not connect anything but C17 to the VCORE
pin.
As shown in Figure 8-3, the input voltage, VIN,
divided by the detection resistors is applied to the VSEN
pin. Signals input to the VSEN pin are used for the 8.2.14. GPIO01 to GPIO04
undervoltage lockout and the input voltage off-state
detection. For more detailed functional descriptions and These pins are the general-purpose I/O pins. For more
the setting of peripheral constants for the VSEN pin, see details, refer to the MD6603 data sheet.
Section 8.5. The GPIO1 pin controls the LLC stage on/off
operation. The capacitor C25 should have a capacitance
of 0.01 μF. When the GPIO1 pin becomes logic high,
8.2.11. FB the LLC stage turns on. When the GPIO1 pin becomes
logic low, the LLC stage turns off.
This pin is used for controlling LLC output voltage to The GPIO04 pin has the AC power supply input off-
be constant. As Figure 8-5 shows, the optocoupler PC1 state detection function, which outputs a signal at AC
and the capacitor C16 should be connected to the FB pin. power supply cutoff (see Section 8.5). GPIO02 to
The FB pin controls the on-times of the high- and low- GPIO04 pins must be all connected to the GND pin if
side power MOSFETs (duty cycle = 50%). not used.
Section 8.10 provides more details on the constant
voltage control.
8.2.15. VOCM
The VOCM pin is connected to the gate of the power
MOSFET (Q6) for small-signal used for current mode
control as shown in Figure 8-5. For more detailed setting
of peripheral circuit for the VOCM pin, see Section 8.10.
8.2.16. SCID 28 Q3
VGH
This is the debugging pin. For detailed functional 27 T1
descriptions, such as software debugging, and software VS
C22 D12
programming (erasing and writing) to the programs on
the flash memory, refer to the MD6603 data sheet. VB 26 C20
R30
Leave this pin open if not used. U1
6 D13 External
VCC power
supply
23 C21
8.2.17. VGL and VGH VGL
8 C12 Q4
These pins are the drive output pins for driving the GND
power MOSFETs in the LLC stage. The VGL pin acts as Bootstrap circuit
a low-side driver, whereas the VGH pin acts as a high-
side driver. Respective drive currents are defined as
Figure 8-7. Bootstrap Circuit
follows: the LLC Drive Current (Source),
IGL(SRC) = IGH(SRC) = –300 mA; the LLC Drive Current
(Sink), IGL(SNK) = IGH(SNK) = 550 mA. Figure 8-7 is a schematic diagram of the bootstrap
The description hereafter holds up the peripheral circuit that drives the high-side power MOSFET (Q3).
circuit of Q4 as an example (but is also applicable to In the condition where the high-side power MOSFET is
Q3). To increase a falling speed of the gate at power turned off and the low-side power MOSFET (Q4) is
MOSFET turn-off, connect the diode D11 as shown in turned on, the VS pin voltage has almost the same
Figure 8-5. R26, R27, and D11 should be adjusted based potential as the ground. Then, C22 is charged with the
on the operation performance checked with an actual VCC pin. When the voltage between the VB and VS
board, including a loss in the power MOSFET, gate pins (hereafter “VB–VS voltage”) increases to
waveform (e.g., ringing due to pattern layout), and EMI VBUV(ON) = 6.8 V or more, the internal high-side driver
noise. To prevent malfunction caused by steep dv/dt at starts operating. When VB–VS voltage decreases to
power MOSFET turn-off, connect R28, of about 10 kΩ VBUV(OFF) = 6.4 V or less, the internal high-side driver
to 100 kΩ, between the gate and source of the power stops operating (i.e., VB_UVLO). The VB_UVLO
MOSFET with a minimal length of traces. When protects the IC in case both ends of C22 and D12 are
adjusting gate resistances, note that gate waveforms of shorted. The bootstrap circuit components must meet the
the power MOSFETs must be checked whether a proper following:
amount of dead time is ensured based on the reference
waveforms depicted in Figure 8-6. ● D13
D13 should be a fast recovery diode with a short
High-side recovery time and a low reverse current. When the
Gate maximum supply input voltage is specified at 265 VAC,
it is recommended to use a fast recovery diode with
Vth (min.) VRM = 600 V.
Low-side Dead time Dead time ● C12, C22, R30
Gate The values of C12, C22, and R30 are determined by
the following parameters: the total amount of gate
Vth (min.)
charges of the external power MOSFETs, Qg; the
amount of a voltage dip between the VB and VS pins
Figure 8-6. Dead Time Confirmation during operation at the lowest oscillation frequency. C12,
C22, and R30 should be adjusted according to voltages
measured by a high-voltage differential probe so that
VB–VS voltage exceeds VBUV(ON) = 6.8 V. C12 and C22
8.2.18. VB and VS should be film or ceramic capacitors with a low ESR and
The VB pin is the input of the high-side floating a low leakage current. The reference value of C12 is
power supply, whereas the VS pin is the ground of the 0.47μF to 1 μF. The time constants of C22 and R29
high-side floating power supply. The MD6752 should be set within 500 ns. C22 should have a
incorporates the high-side driver undervoltage lockout capacitance of 0.047 μF to 0.1 μF; R30 should have a
(VB_UVLO) between the VB and VS pins (see Section resistance of 2.2 Ω to 10 Ω.
8.12).
● D12
D12 is used for protecting the VS pin from having a
negative potential. D12 should be a Schottky diode with
a low forward voltage so that VB–VS voltage does not Frequency controlled by
Switching feedback signal
fall below −0.3 V of its absolute maximum rating. Frequency OCP
operation
R19 0 t
U1
R20
GPIO04
VSEN Channel9
A/D0 CPU Figure 8-11. PFC_OCP Operational Waveforms
13 21
R21 C24
GND In all AC input voltage specifications, the current
8
transformer should be set so that CS pin voltage stays
within the range of VCS(LO) to VCS(HI). The winding turns
Figure 8-10. VSEN Pin and Its Peripheral Circuit ratio of the current transformer, n, is calculated as
follows:
current transfer ratio, CTR, of the optocoupler must take range, from td(MIN) = 0.47 μs to td(MAX) = 0.56 μs, for
its performance decline over time into account in actual which the power supply operates within all the allowable
designing. C16 should have a capacitance of about operating ranges and avoids the zero voltage switching
1000 pF. (ZVS) failure shown in Figure 8-17.
Figure 8-19 depicts how a dead time varies according
C3
to the FB pin voltage. Also, ensure a margin so that
D14 R32 period in which drain current flows through body diode
28
Q3 in Figure 8-18 is longer than the dead time, and actual
VGH
R31 operations must be checked to ensure that power
27 R33
VS MOSFETs operate with the zero current switching
U1 C22 D12 (ZCS) under the following conditions:
26
VB D51 OUT(+)
– When an output power is minimum in a maximum
D11 R27 T1 C51
Q4
23 R51
VGL
R26
C20 R54 input voltage specification
20
– When an output power is maximum in a minimum
VOCM R28 C21
R52
15 D15 PC1
CM
GND FB R29 C19
D52 R53 input voltage specification
8 14 C52
DZ3
U51 R55
C18
Q6 VGL
OUT(-)
PC1 C16
VGH
Figure 8-15. FB Pin and Its Peripheral Circuit High-side Losses increased due
D–S Voltage, to hard switching
VDS(H)
VGL Pin
Voltage
0
t Voltage resonance Voltage resonance
VGH Pin
Voltage
0 High-side Drain
High-side Current, ID(H)
Drain Current, t
ID(H) Period in which drain
current flows through
0 body diode
t
FB Pin Voltage
VFB Figure 8-18. Point to Be Checked in ZCS
0
t
CM Pin Voltage
VCM VFB 0.60
0
t 0.55
Dead Time (μs)
0.45
8.11. LLC Dead Time
A dead time is a period of time when both of the high- 0.40
and low-side power MOSFETs in the LLC stage turn off. 0 50 100 150 200 250
When the dead time is shorter than a voltage resonance
period as in Figure 8-17, the power MOSFETs turn on LLC Oscillation Frequency (kHz)
or off during the voltage resonance period. In such case,
switching loss increases due to hard switching of the Figure 8-19. Dead Time vs. LLC Oscillation
power MOSFETs. Frequency
Be sure to set a dead time so that it falls within the
CM Pin Voltage
VCM(MAX)
0
t
FB Pin Voltage tOLP1 tAR tOLP1
VFB(OLP)
0
t
VGL, VGH
Pin Voltage
0
t
VAC
L3 D2
C3
D4
D3
R12 External power supply
C8 C9 Q1
R13
Q2 4) Looped as small
D9 D10 R14 D13 as possible
R30 Q3
R15 6) Designed as wide
NC VGH
1 28 and short as possible
R10 VS
2 27
A2 VB T1
3 26
PGND C22 D51
4 25
C10 R9 VGP A0
5 24 Q4 C51
R17 C12 VCC VGL C20
6 23
2) Connected to the root of BASE U1 SCID
C21
7 22 Debug
R18 GND MD6752 GPIO04
C3 with dedicated pattern 8 21 D52
AVCC VOCM
R19 C13 9 20
DVCC GPIO01 C19
C14 10 19
VREF GPIO03 R29
R20 C15 11 18
CS GPIO02
5) Placed near the IC with a R16 12 17
VSEN VCORE CY
13 16
minimum length of traces FB CM
D15
C16 14 15 DZ3
C17
C18
C25
R22
R23
R24
R25
R21 PC1
Q6
C24
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