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Fully Digital-controlled Power Supply Control IC with

Bridgeless PFC and LLC Current-resonant Circuits


MD6752 Data Sheet

Description Package
The MD6752 is a fully digital-controlled power SOP28
supply IC, which incorporates a bridgeless PFC control
circuit and an LLC current-resonant circuit. The PFC
circuit, driven by continuous conduction mode (CCM),
is controlled with frequencies suitable for applied input
voltages and loads. The IC incorporates current mode
for controlling constant voltages in the LLC stage and a
floating drive circuit that drives an external high-side
power MOSFET, in addition to functionally-rich
protections. These digitally controlled strategies allow
application-specific optimal settings. Compared to
conventional analog control circuits, the IC can achieve
more cost-effective, high-efficient, yet low-noise power
systems with fewer external components. Not to scale

Features Applications
● Fully Digital-controlled PFC and LLC Current- For devices requiring high power supplies such as:
resonant Circuits
● Soft Start ● Audiovisual Equipment
● Bridgeless PFC Circuit ● Office Automation Equipment (e.g., Server,
● Continuous Conduction Mode (CCM) PFC Control Multifunction Printer)
● Current Mode LLC Control ● Industrial Equipment
● Protections Include: ● Communication Equipment

- AC Power Supply Input Undervoltage Lockout Typical Application


- AC Power Supply Input Off-state Detection
- PFC Output Undervoltage Protection (PFC_UVP) VAC

- PFC Output Overvoltage Protection (PFC_OVP)


- PFC Overcurrent Protection (PFC_OCP) Sense Sense

- PFC Overload Protection (PFC_OLP)


- LLC High-side Driver Undervoltage Lockout
PFC PFC
(VB_UVLO) gate gate

- LLC Overcurrent Protection (LLC_OCP)


External power supply
- LLC Overload Protection (LLC_OLP)
- VCC Pin Overvoltage Protection (VCC_OVP) Sense
NC
1 28
VGH
VS
2 27
- Thermal Shutdown (TSD) A2
PGND
3 26
VB

PFC 4 U1 25 VOUT+
gate VGP A0
5 24
VCC VGL
6 23
MD6752

BASE SCID
7 22 Debug
GND GPIO04
8 21
AVCC VOCM
9 20
DVCC GPIO01
10 19
VREF GPIO03
11 18
CS GPIO02
12 17
VSEN VCORE
13 16
FB CM
14 15
VOUT-

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MD6752

Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Absolute Maximum Ratings----------------------------------------------------------------------------- 4
2. Electrical Characteristics -------------------------------------------------------------------------------- 5
3. Block Diagram --------------------------------------------------------------------------------------------- 9
4. Pin Configuration Definitions ------------------------------------------------------------------------- 10
5. Typical Application ------------------------------------------------------------------------------------- 11
6. Physical Dimensions ------------------------------------------------------------------------------------ 12
7. Marking Diagram --------------------------------------------------------------------------------------- 12
8. Operational Description ------------------------------------------------------------------------------- 13
8.1. General Description ------------------------------------------------------------------------------- 13
8.2. Pin Descriptions ----------------------------------------------------------------------------------- 13
8.2.1. A0 ----------------------------------------------------------------------------------------------- 13
8.2.2. A2 ----------------------------------------------------------------------------------------------- 13
8.2.3. GND and PGND ----------------------------------------------------------------------------- 13
8.2.4. VGP -------------------------------------------------------------------------------------------- 13
8.2.5. VCC -------------------------------------------------------------------------------------------- 14
8.2.6. DVCC and BASE ---------------------------------------------------------------------------- 14
8.2.7. AVCC ------------------------------------------------------------------------------------------ 14
8.2.8. VREF ------------------------------------------------------------------------------------------ 14
8.2.9. CS----------------------------------------------------------------------------------------------- 15
8.2.10. VSEN ------------------------------------------------------------------------------------------ 15
8.2.11. FB----------------------------------------------------------------------------------------------- 15
8.2.12. CM --------------------------------------------------------------------------------------------- 15
8.2.13. VCORE ---------------------------------------------------------------------------------------- 15
8.2.14. GPIO01 to GPIO04 ------------------------------------------------------------------------- 15
8.2.15. VOCM ----------------------------------------------------------------------------------------- 15
8.2.16. SCID ------------------------------------------------------------------------------------------- 16
8.2.17. VGL and VGH ------------------------------------------------------------------------------- 16
8.2.18. VB and VS ------------------------------------------------------------------------------------ 16
8.3. Startup Operation --------------------------------------------------------------------------------- 17
8.4. Soft Start Function -------------------------------------------------------------------------------- 17
8.5. AC Power Supply Input Undervoltage Lockout,
AC Power Supply Input Off-state Detection Function ------------------------------------- 17
8.6. VCC Pin Overvoltage Protection--------------------------------------------------------------- 18
8.7. PFC Overcurrent Protection, PFC Overload Protection ---------------------------------- 18
8.8. PFC Overvoltage Protection -------------------------------------------------------------------- 19
8.9. PFC Undervoltage Protection ------------------------------------------------------------------- 19
8.10. LLC Constant Voltage Control ----------------------------------------------------------------- 19
8.11. LLC Dead Time ----------------------------------------------------------------------------------- 20
8.12. LLC High-side Driver Undervoltage Lockout ----------------------------------------------- 21
8.13. LLC Overcurrent Protection, LLC Overload Protection --------------------------------- 21
8.14. Thermal Shutdown -------------------------------------------------------------------------------- 21
9. External Components ---------------------------------------------------------------------------------- 22
9.1. Resonant Transformer --------------------------------------------------------------------------- 22
9.2. Inductor in PFC Stage ---------------------------------------------------------------------------- 22
9.3. Power MOSFET ----------------------------------------------------------------------------------- 22
9.4. PFC Boost Diode (D1, D2) ----------------------------------------------------------------------- 22
9.5. Input Filter ----------------------------------------------------------------------------------------- 22
9.6. Output Capacitor (C51) -------------------------------------------------------------------------- 22

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MD6752

9.7. Current-resonant Capacitor (C21) ------------------------------------------------------------ 22


10. PCB Pattern Layout ------------------------------------------------------------------------------------ 22
Important Notes ---------------------------------------------------------------------------------------------- 24

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MD6752

1. Absolute Maximum Ratings


Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−). Unless specifically noted, TA = 25 °C. Surge withstand capability
(HBM) of the MD6752 is guaranteed up to 2000 V. Note that the following pins are guaranteed to withstand surges up
to 1000 V: 26, 27, 28.
Parameter Symbol Pin Rating Unit
A0 Pin Voltage VA0 24–8 −6.0 to 6.0 V
A2 Pin Voltage VA2 3–8 −6.0 to 6.0 V
PGND Pin Voltage VPGND 4–8 −0.3 to 0.3 V
VGP Pin Voltage VGP 5–8 −0.3 to VCC + 0.3 V
VGP Pin Voltage (tW ≤ 50 ns) VGP(PULSE) 5–8 −1.5 V
VCC Pin Voltage VCC 6–8 −0.3 to 20 V
BASE Pin Voltage VBASE 7–8 −0.3 to 6.0 V
AVCC Pin Voltage (1)(2)
VAVCC 9–8 −0.3 to 3.6 V
DVCC Pin Voltage(2) VDVCC 10–8 −0.3 to 3.6 V
VREF Pin Voltage (3)
VREF 11–8 −0.3 to VDVCC + 0.3 and −0.3 to 3.6 V
CS Pin Voltage (3)
VCS 12–8 −0.3 to VDVCC + 0.3 and −0.3 to 3.6 V
VSEN Pin Voltage VSEN 13–8 −0.3 to VDVCC + 0.3 and −0.3 to 3.6 V
FB Pin Voltage VFB 14–8 −0.3 to VDVCC + 0.3 and −0.3 to 3.6 V
CM Pin Voltage VCM 15−8 −0.3 to VDVCC + 0.3 and −0.3 to 3.6 V
VCORE Pin Voltage (4)
VCORE 16–8 −0.3 to 2.0 (5)
V
GPIO02 Pin Voltage (6)
VGPIO02 17–8 −0.3 to 5.5 V
GPIO02 Pin Current(6) IGPIO02 17–8 −4.0 to4.0 mA
GPIO03 Pin Voltage(6) VGPIO03 18–8 −0.3 to 5.5 V
GPIO03 Pin Current(6) IGPIO03 18–8 −4.0 to 4.0 mA
GPIO01 Pin Voltage(6) VGPIO01 19–8 −0.3 to 5.5 V
GPIO01 Pin Current (6)
IGPIO01 19–8 −4.0 to 4.0 mA
VOCM Pin Voltage VOCM 20–8 −0.3 to 5.5 V
VOCM Pin Current IVOCM 20–8 −4.0 to 4.0 mA
GPIO04 Pin Voltage(6) VGPIO04 21–8 −0.3 to 5.5 V
GPIO04 Pin Current (6)
IGPIO04 21–8 −4.0 to 4.0 mA
SCID Pin Voltage VSCID 22–8 −0.3 to 5.5 V
VGL Pin Voltage VGL 23–8 −0.3 to VCC + 0.3 V
VB–VS Pin Voltage VBS 26–27 −0.3 to 20.0 V
VS Pin Voltage VS 27–8 −1 to 600 V
VGH Pin Voltage VGH 28–8 VS − 0.3 to VB + 0.3 V
Operating Ambient Temperature TOP ― −40 to 85 °C
Storage Temperature TSTG ― −40 to 125 °C
Junction Temperature TJ ― 125 °C

(1)
The AVCC pin is the 3.3 V power supply output pin dedicated for the internal LSI chip. Do not apply external
voltage to this pin.
(2)
Electric potential difference between the AVCC and DVCC pins should be maintained within ±0.3 V(t > 1 ms).
(3)
Refers to an analog input pin for 3.3 V systems.
(4)
The VCORE pin is the 1.8 V power supply output pin dedicated for digital circuits of the internal LSI chip. Do not
apply external voltage to this pin.
(5)
Should be rated from −0.3 V to 2.4 V when t < 1 ms (e.g., at startup).
(6)
Refers to a digital output pin for 3.3 V systems.

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MD6752

2. Electrical Characteristics
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, VCC = 17 V.
The checkmark in the Chg. column indicates that the item is dedicated GUI-changeable. In addition, the characteristic
value in this column is a reference value.
Parameter Symbol Conditions Pin Min. Typ. Max. Unit Chg.
Startup Circuit, Circuit Current
Operation Start Voltage VCC(ON) 6–8 13.0 14.0 15.0 V
(1)
Operation Stop Voltage VCC(OFF) 6–8 7.4 8.3 9.2 V
Circuit Current in Operation ICC(ON) 6–8 ― 1.8 4.0 mA
Circuit Current in Non-
ICC(OFF) VCC = 11 V 6–8 ― 0.5 1.0 mA
operation
VCC Pin Protection Release
VCC(P.OFF) 6–8 7.4 8.3 9.2 V
Threshold Voltage(1)
Circuit Current in Protection
ICC(P) VCC = 10 V 6–8 ― 0.5 1.0 mA
Operation
VCORE Pin Supply Voltage VCORE 16–8 1.72 1.80 1.88 V
SCID Pin High Level Detection
VSCID_IH 22–8 2.0 ― ― V
Voltage(2)
SCID Pin Low Level Detection
VSCID_IL 22–8 ― ― 0.8 V
Voltage(2)
3.3 V Analog Internal Regulator VAVCC 9–8 3.233 3.300 3.366 V
3.3 V Digital Internal Regulator VDVCC 10–8 3.135 3.300 3.465 V
External Transistor Drive
VBASE IBASE = −1 mA 7–8 3.6 ― 4.4 V
Voltage for DVCC Pin
VSEN Pin Input UVP
VSEN(OFF) 13–8 0.43 0.47 0.51 V ✓
Threshold Voltage
VSEN Pin Input UVP Release
VSEN(ON) 13–8 0.52 0.56 0.60 V ✓
Voltage
VSEN Pin AC Input Voltage
VSEN(AC_OFF) 13–8 0.16 0.19 0.22 V ✓
Off-state Detection Voltage
Delay Time of VSEN Pin Input
tVSEN(OFF) 13–8 9.5 10.0 10.5 ms ✓
UVP Detection
Delay Time of VSEN Pin AC
Input Voltage Off-state tVSEN(AC_OFF) 13–8 21.8 23.0 24.2 ms ✓
Detection
PFC Stage
VCC = 17 V,
PFC Drive Current (Source) IGP(SRC) VGP = 0 V
5–4 ― −500 ― mA
VCC = 17 V,
PFC Drive Current (Sink) IGP(SNK) VGP = 17 V
5–4 ― 1 ― A
CS Pin OCP Threshold Voltage
VCS(LO) VIN = 90 VAC 12–8 1.60 1.69 1.78 V ✓
(Low)

(1)
VCC (OFF) = VCC (P.OFF)
(2)
Guaranteed by design.

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MD6752

Parameter Symbol Conditions Pin Min. Typ. Max. Unit Chg.


CS Pin OCP Threshold Voltage
VCS(HI) VIN = 260 VAC 12–8 0.65 0.71 0.77 V ✓
(High)
Number of OVP Operation
NOPP(AC) 5–8 ― 32 ― Times ✓
Times
VREF Pin Threshold Voltage
VREF 11–8 2.009 2.096 2.183 V ✓
for PFC Output Control
Maximum PFC Oscillation
fMAX_PFC 5–8 190 200 210 kHz ✓
Frequency
Minimum PFC On-time tON(MIN)_PFC 5–8 0.28 0.30 0.32 μs ✓

Minimum PFC Off-time tOFF(MIN)_PFC 5–8 0.28 0.30 0.32 μs ✓


Maximum PFC On-time tON(MAX)_PFC 5–8 20.8 21.9 23.0 μs ✓
Maximum PFC Off-time tOFF(MAX)_PFC 5–8 14.2 14.9 15.7 μs ✓
VREF Pin PFC_UVP Start VREF−
VREF(UVD) 11–8 — — V
Voltage 0.08
VERF Pin PFC_UVP
VREF(UVP) 11–8 1.05 1.10 1.15 V ✓
Oscillation Stop Voltage
VREF Pin PFC_UVP Release
VREF(UVP_R) 11–8 0.51 0.55 0.59 V ✓
Voltage
PFC_UVP Recovery Delay
t(UVP_R) ― 778 819 860 ms ✓
Time
VREF Pin PFC_OVP Start VREF+
VREF(OVD) 11–8 — — V
Voltage 0.08
VREF Pin PFC_OVP
VREF(OVP) 11–8 2.14 2.23 2.33 V ✓
Oscillation Stop Voltage
VREF Pin PFC_OVP
Oscillation Stop Release VREF(OVP_R) 11–8 2.09 2.18 2.27 V ✓
Voltage
LLC Stage
Maximum FB Pin Source
IFB(MAX) VFB = 0 V 14–8 −440 −330 −250 µA
Current
High-side Driver Operation
VBUV(ON) 26–27 5.8 6.8 7.8 V
Start Voltage
High-side Driver Operation
VBUV(OFF) 26–27 5.4 6.4 7.4 V
Stop Voltage
VCC = 17 V,
IGL(SRC) VB = 17 V, 23–4
LLC Drive Current (Source) VGL = 17 V,
— –300 — mA
IGH(SRC) 28−8
VGH = 17 V
VCC = 17 V,
IGL(SNK) VB = 17 V, 23–4
LLC Drive Current (Sink) VGL = 0 V,
— 550 — mA
IGH(SNK) 28−8
VGH = 0 V
VREF Pin LLC Operation Start
VREF(LLC_ON) 11–8 1.85 1.93 2.01 V ✓
Voltage
VREF Pin LLC Operation Stop
VREF(LLC_OFF) 11–8 1.26 1.32 1.39 V ✓
Voltage
LLC Maximum Oscillation
23–4
Frequency during Soft Start fMAX_LLC(SS) 385 405 426 kHz ✓
28−8
Operation
Current Mode Operation Start
23–4
LLC Oscillation Frequency fLLC(CM) 190 200 210 kHz ✓
28−8
during Soft Start Operation
Lowest LLC Oscillation 23–4
fMIN_LLC 55.7 58.6 61.5 kHz ✓
Frequency 28−8

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MD6752

Parameter Symbol Conditions Pin Min. Typ. Max. Unit Chg.


Highest LLC Oscillation 23–4
fMAX_LLC 190 200 210 kHz ✓
Frequency 28−8
23–4
Minimum LLC Dead Time td(MIN) 0.44 0.47 0.49 μs ✓
28−8
23–4
Maximum LLC Dead Time td(MAX) 0.53 0.56 0.59 μs ✓
28−8
Current Mode Control
VCM(MIN) 15−8 0.06 0.10 0.15 V ✓
Minimum CM Pin Voltage
Current Mode Control
VCM(MAX) 15−8 1.90 2.00 2.10 V ✓
Maximum CM Pin Voltage
Current Mode Control
Maximum CM Pin Voltage VCM(UV_MIN) 15−8 2.66 2.78 2.91 V ✓
during LLC Undervoltage
OLP Operation Start FB Pin
VFB(OLP) 14−8 2.89 3.00 3.12 V ✓
Voltage
OLP Delay Time 1 tOLP1 15−8 4.7 5.0 5.3 ms ✓

OLP Delay Time 2 tOLP2 15−8 0.1 0.2 0.3 ms ✓

Protection Recovery Time tAR 15−8 2850 3000 3150 ms ✓


Overvoltage Protection (OVP)
VCC Pin OVP Threshold
VCC(OVP) 6–8 18.1 19.0 19.7 V
Voltage
External Shutdown
A0 Pin Operation Stop
VA0 24–8 1.18 1.25 1.32 V ✓
Threshold Voltage
A0 Pin Protection Delay Time tA0 24–8 — 1000 — ms ✓
A0 Pin Offset Voltage (3)
VA0(OFS) VA0 = 0 V 24–8 — 1.65 — V
Digital General-purpose I/O
A2 Pin Offset Voltage(4) VA2(OFS) VA2 = 0 V 3–8 ― 0.6 ― V
GPIO Pin High Level Detection
VIH (5)
2.0 — — V
Voltage
GPIO Pin Low Level Detection
VIL (5)
— — 0.8 V
Voltage
Digital Pull-up Resistor RPUP (5)
20 60 100 kΩ
Analog Pull-up Resistor 14–8
RPUP2 7.9 10.0 12.4 kΩ
(FB, CM) 15–8
VREF = 0 V 11–8
Input Leakage Current IL
VSEN = 0 V
−2 ±1 2 μA
13–8
GPIO Pin High Level Output
VOH4 IOH = −4 mA (5)
2.4 — — V
Voltage
GPIO Pin Low Level Output
VOL4 IOH = 4 mA (5)
— — 0.4 V
Voltage
Clock Operation
Internal IRC Oscillation
fIRC — 11.64 12.00 12.18 MHz
Frequency
Thermal Shutdown (TSD)

(3)
See Figure 2-2.
(4)
See Figure 2-1.
(5)
Refers to voltage between the GND pin and all the following pins: GPIO02, GPIO03, GPIO01, GPIO04.

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MD6752

Parameter Symbol Conditions Pin Min. Typ. Max. Unit Chg.


TSD Operating Temperature (6)
TJ(TSD) — 125 — — °C
Thermal Characteristic
Junction-to-Air Thermal
θJ-A — — — 85 °C/W
Resistor

(6)
Guaranteed by design.

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MD6752

4
4
ANEX0/1/2* Pin Input

3 3

ANEX0* Pin Input


Voltage (V)

Voltage (V)
2 2

1 1

0 0
-2 -1 0 1 2 3 4 -2 -1 0 1 2 3 4
A2 Pin Input Voltage (V) A0 Pin Input Voltage (V)

Figure 2-1. A2 Pin Offset Figure 2-2. A0 Pin Offset

* Indicates voltages inside the IC; see the block diagram in Section 3.

3. Block Diagram

NC 1 26 VB
MIC1: Driver
A2 3 Level Shift
28 VGH
PGND 4
P_GND
VCC
VBUV(ON) /
VGP 5 VBUV(OFF) 27 VS
VCC
P_GND
23 VGL
VCC 6 P_GND
Start/Stop,
BASE 7 OVP, TSD, REG Main Control Logic
Level Shift,
VG_LLC_H
VG_LLC_L

Clamp
VG_PFC

Level
GND
Shift
24 A0
GND 8 A2_2 A2_1 A0_0 AVCC33 DVCC33
GPIO12
GPIO10

GPIO13

ANEX2 ANEX1 ANEX0 AVCC DVCC


DGND
AGND

AVCC 9 AVCC
MIC2: MCU (MD6603)
DVCC 10 DVCC

VREF 11 ANEX10

CS 12 ANEX3
ANEX5 ANEX4
VSEN 13 ANEX9 GPIO21 GPIO20 VCORE GPIO02 GPIO03 GPIO01 GPIO05 GPIO04 SCID

14 15 16 17 18 19 20 21 22
FB CM VCORE GPIO02 GPIO03 GPIO01 VOCM GPIO04 SCID

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MD6752

4. Pin Configuration Definitions


Top View No. Name Description
1 NC No connection (connect to the logic ground)
NC 1 28 VGH
2 — Pin removed
2 27 VS
3 A2 Analog input
A2 3 26 VB
4 PGND Power ground
PGND 4 25
5 VGP PFC gate drive output
VGP 5 24 A0 6 VCC Logic power supply input; VCC_OVP
VCC 6 23 VGL 7 BASE External transistor base voltage output for the DVCC pin
BASE 7 22 SCID 8 GND Ground
GND 8 21 GPIO04 9 AVCC 3.3 V analog power supply
AVCC 9 20 VOCM 10 DVCC 3.3 V digital power supply
DVCC 10 19 GPIO01 PFC constant voltage control signal input; PFC_UVP /
11 VREF
VREF 11 18 GPIO03 PFC_OVP
CS 12 17 GPIO02 12 CS PFC_OCP signal input
VSEN 13 16 VCORE
13 VSEN Input voltage detection signal input
14 FB Power MOSFET control signal input; LLC_OLP
FB 14 15 CM
Current mode detection signal input, LLC overcurrent
15 CM
protection (OCP) detection signal input
16 VCORE Capacitor connection for internal digital circuit supplies
17 GPIO02 General-purpose I/O pin
18 GPIO03 General-purpose I/O pin
19 GPIO01 General-purpose I/O pin
20 VOCM Current mode control signal input
21 GPIO04 General-purpose I/O pin
22 SCID Debugging pin (left open if not used)
23 VGL LLC low-side gate drive output
24 A0 Analog input (External Shutdown Input)
25 — Pin removed
Power supply input for LLC high-side gate drive with UVLO;
26 VB
VB_UVLO signal input
27 VS Floating ground of LLC high-side driver
28 VGH LLC high-side gate drive output

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MD6752

5. Typical Application

C1 L1 C2 L2 D1

VAC L3 D2
L4 D7 D8 L5
D4 D3 DZ1 R7 DZ2
R8
C3
C6 C7

Q1 D5 D6 Q2
R1 R4 C5

C4
R3 R2 R5 R6
D9 C8 C9 D10

D13 R30 R31


R10 Q3
NC VGH D14 R32 C23
1 28
VS
C10 2 27 R33
A2 VB C22
3 26 T1
PGND D51 VOUT+
4 25 R26
C11 VGP A0 D12
R12 5 24 Q4
R17 R11 VCC VGL
6 23 C20 C51 R51
BASE U1 SCID R54
R13 7 22 Debug D11 R27 C21
R18 Q5 C12 GND MD6752 GPIO04 R28 D52 PC1
8 21 R52
AVCC VOCM
R14 9 20
R19 R16 C14 C13 DVCC GPIO01
10 19 C19
R15 VREF GPIO03 C52 R53
11 18 R29
R20 R9 CS GPIO02
C15 12 17
VSEN VCORE
D15 U51
13 16
FB CM R55
14 15 DZ3
C18
C17

C16 C24 VOUT-


R22

R24

C25
R23

R25

R21 PC1
Q6

External power supply CY

Figure 5-1. Typical Application

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MD6752

6. Physical Dimensions
● SOP28

NOTES:
● Dimension is in millimeters.
● Pb-free

7. Marking Diagram

28

MD675 2
Part Number
S KY MD X XX
Lot Number:
X XX X Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N, or D)
1 D is the period of days represented by:
1: the first 10 days of the month (1st to 10th)
2: the second 10 days of the month (11th to 20th)
3: the last 10–11 days of the month (21st to 31st)

Control Number

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MD6752

8. Operational Description releases the protection and restarts to operate.


Connect the pull-down resistor, R22 (about 1 kΩ), to
All the characteristic values given in this section are the logic ground, if not used.
typical values, unless they are specified as minimum or
maximum. Current polarities are defined as follows:
current going into the IC (sinking) is positive current
(+); current coming out of the IC (sourcing) is negative
8.2.2. A2
current (−). For concise descriptions, this section This is the input pin for analog signals. The A2 pin is
employs notation systems that denote the electrical internally connected to the comparator and the AD
characteristics symbols listed in Section 2 and the converter. Connect this pin to the logic ground or a
electronic symbol names of the typical application in capacitor of about 0.01 μF, if not used. For more details,
Section 5. refer to the MD6603 data sheet.

8.1. General Description


The MD6752 digitally controls a PFC circuit and an
8.2.3. GND and PGND
LLC current-resonant circuit. The GND pin is the logic ground pin of the IC; the
The PFC circuit embedded in the IC requires no input PGND pin is the power ground pin where driving
rectifier bridge for its own controlling. The PFC circuit, currents for an external power MOSFET flow through.
driven by continuous conduction mode (CCM) in Varying electric potential of the logic ground can be a
normal operation, is controlled with the frequencies cause of improper operations. Therefore, extreme care
suitable for applied input voltages and loads. By should be taken in designing a PCB so that currents from
monitoring the output voltage of the PFC circuit with the the power ground do not affect these pins. For the notes
VREF pin, the IC controls the VGP pin on-time and on PCB pattern layouts, see Section 10.
provides regulated outputs.
The IC has a built-in high-side driver that drives the
LLC half-bridge circuit. By monitoring the secondary 8.2.4. VGP
output voltage through an optocoupler, which is
connected to the FB pin, the IC controls the oscillation This is the drive output pin for driving the power
frequencies of the VGH and VGL pins to provide MOSFETs (Q1, Q2) in the PFC stage. The pin should be
regulated outputs (Section 8.10). Moreover, software- connected to the gates of Q1 and Q2. Respective drive
supported dead time setting is available for the MD6752 currents are defined as follows: the PFC Drive Current
(Section 8.11). (Source), IGP(SRC) = −500 mA; the PFC Drive Current
Protections in the PFC stage include the overcurrent (Sink), IGP(SNK) = 1 A.
and overload protections (Section 8.7), the overvoltage
protection (Section 8.8), and the undervoltage protection L2 D1
C2
(Section 8.9). Protections in the LLC stage include the
high-side driver undervoltage lockout (Section 8.12), L3 D2 C3
and the overcurrent and overload protections (Section
8.13).
In addition to the protections above, the IC also has L5 L4
the following functions: the soft start function (Section
8.4), the VCC pin overvoltage protection (to prevent Q1
R1 D5 U1
secondary outputs from overvoltage; see Section 8.6),
and the thermal shutdown (Section 8.14). 5
VGP
R3 R2
8.2. Pin Descriptions Q2
R4 D6
8 GND
R6
R5
8.2.1. A0
This pin is used for analog input and external
shutdown input. The A0 pin should be used within the Figure 8-1. VGP Pin and Its Peripheral Circuit
range of absolute maximum ratings (see Section 1).
When the A0 pin voltage, VA0 = 1.25 V or more, and The description hereafter holds up the peripheral
remains in this condition for 1000 ms or longer, the circuit of Q1 as an example (but is also applicable to
oscillation operations of the VGH, VGL, and VGP pins Q2). To increase a rising speed of the gate at power
are stopped. When the Protection Recovery Time, MOSFET turn-off, connect the diode D5 as shown in
tAR = 3000 ms or longer, elapses after that, the IC Figure 8-1. D5, R1, and R2 should be adjusted based on

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the operation performance checked with an actual board, 8.2.7. AVCC


including a loss in the power MOSFET, gate waveform
(e.g., ringing due to pattern layout), and EMI noise. To The AVCC pin is the internal 3.3 V analog power
prevent malfunction caused by steep dv/dt at power supply pin. The capacitor C13 in Figure 8-2 should have
MOSFET turn-off, connect R3, of about 10 kΩ to a capacitance of about 0.47 μF. Do not connect anything
100 kΩ, between the gate and source of the power but C13 to the AVCC pin.
MOSFET with a minimal length of traces.

8.2.8. VREF
8.2.5. VCC As shown in Figure 8-3, the output voltage of the PFC
This is the power supply pin for the built-in control stage, VOUT(PFC), divided by the detection resistors is
MICs, and is connected to an external power supply. applied to the VREF pin. Signals input to the VREF pin
When the VCC pin voltage increases to VCC(ON) or more, are used for the constant voltage control in the PFC
the IC starts operating. When the VCC pin voltage stage, the overvoltage protection (Section 8.8), and the
decreases to VCC(OFF) or less, the IC stops operating. This undervoltage protection (Section 8.9). VOUT(PFC) is
sequence of operations is the VCC pin undervoltage determined by the detection resistors, R12 to R16, and
lockout (VCC_UVLO). In addition to this function, the can be calculated by the equation below:
VCC pin also has the VCC pin overvoltage protection
(VCC_OVP). R REF1
VOUT(PFC) = ( + 1 ) × VREF . (1)
Section 8.3 describes the startup operation of the IC; R REF2
Section 8.6 provides more details on the VCC_OVP. To
prevent malfunction induced by supply ripples or other Where:
factors, connect 0.01 μF to 0.1 μF ceramic capacitors, VREF is the VREF pin threshold voltage (2.10 V),
C11 and C12, between the VCC and PGND pins, and RREF1 is the combined resistance of the resistors R12 to
between the VCC and GND pins, respectively, with a R15, and
minimal length of traces. RREF2 is the resistance of R16 (≈ 10 kΩ to 68 kΩ).

The resistors of RREF1 are set at high resistance such


8.2.6. DVCC and BASE that high voltage is applied on them. Therefore, the
following must be taken into account in actual
The DVCC pin is the internal 3.3 V digital power designing: select resistors designed to stand against
supply pin. As Figure 8-2 illustrates, the DVCC pin electromigration; configure RREF1 with some serial
power is supplied from the external power supply resistors to reduce each applied voltage.
through an external transistor. The BASE pin is R16 should be adjusted based on the operation
connected to the base of this external transistor. To performance checked with an actual board, including a
reduce noises on the DVCC pin, connect the capacitor PFC output, overvoltage protection, and undervoltage
C14 with a capacitance of about 0.47 μF. protection.
To reduce switching noises, connect the capacitor C15
with a capacitance of about 100 pF to 1000 pF, as near
External power as possible to the VREF pin.
supply
U1
6 VIN L2 D1
VCC VOUT(PFC)

R11 C12 D3 L3 D2 C3
C2 R12

7 R13
Q5 BASE D4 Q1
10 R14
DVCC Q2
R17
9
AVCC R15 U1
R18
16 11
C14 VCORE VREF
C13 R19
R16
C17 8 GND C15
R20
13
VSEN
R21 C24 8 GND
Figure 8-2. Power Stage and Its Peripheral Circuit

Figure 8-3. VREF and VSEN Pins and Their


Peripheral Circuit

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8.2.9. CS C3
D14 R32
This pin serves as a drain current detector of the 28
Q3

power MOSFET in the PFC circuit. In the PFC circuit, VGH


R31
which supports high-power applications, current through VS
27 R33

the power MOSFET is usually detected by the current U1 C22 D12


26
transformers (L4, L5) as in Figure 8-4. Then, a detection VB
D11 R27 T1
D51 OUT(+)
C51
signal is input to the CS pin. Current detection signals 23
Q4
VGL R51
transmitted from the CS pin are used for the protections 20 R26
C20 R54
VOCM
against overcurrent and overload conditions. Section 8.7 R28 C21
R52
15 D15
provides detailed descriptions on the setting of constants GND FB
CM D52
PC1 R53
R29 C19
for the CS pin peripheral circuit, the PFC overcurrent 8 14 C52
DZ3
protection, and the PFC overload protection. Q6
U51 R55
C18
OUT(-)

C2 L2 D1 PC1 C16

L3 D2 C3 Figure 8-5. LLC Circuit


D7
L4
R7 U1 8.2.12. CM
DZ1
C6 The CM pin detects the current flowing to the power
L5
D8 R9
12
MOSFET of the LLC stage. The detected signals are
CS used for the current mode control and the LLC
DZ2
R8 R10 C10 overcurrent protection. Section 8.10 explains the settings
Q1 C7 8
GND of peripheral circuit for the CM pin; Section 8.13 gives a
detailed explanation on the LLC overcurrent protection.
Q2

8.2.13. VCORE
Figure 8-4. CS Pin and Its Peripheral Circuit
The VCORE pin is the internal 1.80 V power supply
pin. The capacitor C17 should have a capacitance of
8.2.10. VSEN 0.1 μF. Do not connect anything but C17 to the VCORE
pin.
As shown in Figure 8-3, the input voltage, VIN,
divided by the detection resistors is applied to the VSEN
pin. Signals input to the VSEN pin are used for the 8.2.14. GPIO01 to GPIO04
undervoltage lockout and the input voltage off-state
detection. For more detailed functional descriptions and These pins are the general-purpose I/O pins. For more
the setting of peripheral constants for the VSEN pin, see details, refer to the MD6603 data sheet.
Section 8.5. The GPIO1 pin controls the LLC stage on/off
operation. The capacitor C25 should have a capacitance
of 0.01 μF. When the GPIO1 pin becomes logic high,
8.2.11. FB the LLC stage turns on. When the GPIO1 pin becomes
logic low, the LLC stage turns off.
This pin is used for controlling LLC output voltage to The GPIO04 pin has the AC power supply input off-
be constant. As Figure 8-5 shows, the optocoupler PC1 state detection function, which outputs a signal at AC
and the capacitor C16 should be connected to the FB pin. power supply cutoff (see Section 8.5). GPIO02 to
The FB pin controls the on-times of the high- and low- GPIO04 pins must be all connected to the GND pin if
side power MOSFETs (duty cycle = 50%). not used.
Section 8.10 provides more details on the constant
voltage control.
8.2.15. VOCM
The VOCM pin is connected to the gate of the power
MOSFET (Q6) for small-signal used for current mode
control as shown in Figure 8-5. For more detailed setting
of peripheral circuit for the VOCM pin, see Section 8.10.

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8.2.16. SCID 28 Q3
VGH
This is the debugging pin. For detailed functional 27 T1
descriptions, such as software debugging, and software VS
C22 D12
programming (erasing and writing) to the programs on
the flash memory, refer to the MD6603 data sheet. VB 26 C20
R30
Leave this pin open if not used. U1
6 D13 External
VCC power
supply
23 C21
8.2.17. VGL and VGH VGL
8 C12 Q4
These pins are the drive output pins for driving the GND
power MOSFETs in the LLC stage. The VGL pin acts as Bootstrap circuit
a low-side driver, whereas the VGH pin acts as a high-
side driver. Respective drive currents are defined as
Figure 8-7. Bootstrap Circuit
follows: the LLC Drive Current (Source),
IGL(SRC) = IGH(SRC) = –300 mA; the LLC Drive Current
(Sink), IGL(SNK) = IGH(SNK) = 550 mA. Figure 8-7 is a schematic diagram of the bootstrap
The description hereafter holds up the peripheral circuit that drives the high-side power MOSFET (Q3).
circuit of Q4 as an example (but is also applicable to In the condition where the high-side power MOSFET is
Q3). To increase a falling speed of the gate at power turned off and the low-side power MOSFET (Q4) is
MOSFET turn-off, connect the diode D11 as shown in turned on, the VS pin voltage has almost the same
Figure 8-5. R26, R27, and D11 should be adjusted based potential as the ground. Then, C22 is charged with the
on the operation performance checked with an actual VCC pin. When the voltage between the VB and VS
board, including a loss in the power MOSFET, gate pins (hereafter “VB–VS voltage”) increases to
waveform (e.g., ringing due to pattern layout), and EMI VBUV(ON) = 6.8 V or more, the internal high-side driver
noise. To prevent malfunction caused by steep dv/dt at starts operating. When VB–VS voltage decreases to
power MOSFET turn-off, connect R28, of about 10 kΩ VBUV(OFF) = 6.4 V or less, the internal high-side driver
to 100 kΩ, between the gate and source of the power stops operating (i.e., VB_UVLO). The VB_UVLO
MOSFET with a minimal length of traces. When protects the IC in case both ends of C22 and D12 are
adjusting gate resistances, note that gate waveforms of shorted. The bootstrap circuit components must meet the
the power MOSFETs must be checked whether a proper following:
amount of dead time is ensured based on the reference
waveforms depicted in Figure 8-6. ● D13
D13 should be a fast recovery diode with a short
High-side recovery time and a low reverse current. When the
Gate maximum supply input voltage is specified at 265 VAC,
it is recommended to use a fast recovery diode with
Vth (min.) VRM = 600 V.
Low-side Dead time Dead time ● C12, C22, R30
Gate The values of C12, C22, and R30 are determined by
the following parameters: the total amount of gate
Vth (min.)
charges of the external power MOSFETs, Qg; the
amount of a voltage dip between the VB and VS pins
Figure 8-6. Dead Time Confirmation during operation at the lowest oscillation frequency. C12,
C22, and R30 should be adjusted according to voltages
measured by a high-voltage differential probe so that
VB–VS voltage exceeds VBUV(ON) = 6.8 V. C12 and C22
8.2.18. VB and VS should be film or ceramic capacitors with a low ESR and
The VB pin is the input of the high-side floating a low leakage current. The reference value of C12 is
power supply, whereas the VS pin is the ground of the 0.47μF to 1 μF. The time constants of C22 and R29
high-side floating power supply. The MD6752 should be set within 500 ns. C22 should have a
incorporates the high-side driver undervoltage lockout capacitance of 0.047 μF to 0.1 μF; R30 should have a
(VB_UVLO) between the VB and VS pins (see Section resistance of 2.2 Ω to 10 Ω.
8.12).
● D12
D12 is used for protecting the VS pin from having a
negative potential. D12 should be a Schottky diode with

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a low forward voltage so that VB–VS voltage does not Frequency controlled by
Switching feedback signal
fall below −0.3 V of its absolute maximum rating. Frequency OCP
operation

8.3. Startup Operation


The power supply voltage for control circuit of the IC
is externally applied to the VCC pin that is the power 0
input pin. When the AC power supply is turned on and Soft start Time
Primary period
the VCC pin voltage applied from the external power Winding
Current
supply reaches VCC(ON) = 14.0 V or more, the VGP pin in
the PFC stage starts oscillating and the PFC output OCP
Limitation
voltage rises. When 100 ms or more elapses after the 0
Time
VGP pin in the PFC stage starts oscillating, the VGH
and VGL pins in the LLC stage start oscillating, and the
secondary output voltage rises. When the VCC pin
voltage decreases to VCC(OFF) = 8.3 V or less, the IC Figure 8-9. Soft Start Operation
stops operation by undervoltage lockout (UVLO) circuit.
8.5. AC Power Supply Input Undervoltage
AC Power
Supply Voltage Lockout, AC Power Supply Input Off-
0
t
state Detection Function
The IC incorporates the AC power supply input
VCC Pin undervoltage lockout and the AC power supply input
Voltage
off-state detection function. These functions allow the
VCC(ON)
IC to stop the switching operation of the VGP pin when
VCC(OFF) a low AC line input voltage is detected, thus preventing
0 from excessive input current and overheating.
t
VGP Pin As depicted in Figure 8-10, the VSEN pin monitors
Voltage the AC input voltage. Each protection starts operating
when either of the two conditions persists for its own
0
t fixed delay time: when the AC input voltage falls below
PFC Output
Voltage
its normal-state level and VSEN ≤ VSEN(OFF) of 0.47 V; or
when VSEN stays unvaried. In either condition, the IC
stops the VGP pin switching operation after a lapse of
0
t
tVSEN(OFF) = 10.0 ms (i.e., the AC power supply input
VGH, VGL
100 ms undervoltage lockout), or the GPIO04 pin becomes logic
Pin Voltage low after a lapse of tVSEN(AC_OFF) = 23.0 ms (i.e., the AC
0 power supply input off-state detection function).
t
Signals detected when the AC power supply is in an
off state can also be transmitted to the secondary
Figure 8-8. Operational Waveforms at Startup microcontroller through an optocoupler (see Figure 8-
10). During the function operation, the IC controls the
8.4. Soft Start Function LLC circuit with “AC off mode”.
When all the following conditions are met, the VGP
Figure 8-9 shows operational waveforms of the soft pin resumes switching operation according to output
start operation at startup. The IC has the soft start load and the LLC circuit returns to normal operation: the
function, which reduces stresses on the peripheral AC input voltage is rising, the IC is in operation, and
components. During the soft start operation, output VSEN ≥ VSEN(ON) of 0.56 V.
power increases as the switching frequencies of the The reference resistance of R21, the resistor to be
VGH and VGL pins gradually decrease. After the output connected to the VSEN pin, is about 20 kΩ. R17 to R21
power increases, the IC operates with oscillation should be selected based on the operation performance
frequency control using feedback signal. checked with an actual board. R17 to R20 are set at high
resistance such that high voltage is applied on them.
Therefore, the following must be taken into account in
actual designing: select resistors designed to stand
against electromigration; connect these resistors in series
to reduce each applied voltage.

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MD6752

VIN L2 D1 VOUT(PFC) NOPP(AC)


CS Pin Voltage
1 2 3 4 31 32
D3 L3 C3 PFC_OCP
D2
C2 Threshold Voltage
D4
0 t
Q2 Q1
R17 VGP Pin Non-oscillating (3000 ms)
Voltage
R18

R19 0 t
U1
R20
GPIO04
VSEN Channel9
A/D0 CPU Figure 8-11. PFC_OCP Operational Waveforms
13 21
R21 C24
GND In all AC input voltage specifications, the current
8
transformer should be set so that CS pin voltage stays
within the range of VCS(LO) to VCS(HI). The winding turns
Figure 8-10. VSEN Pin and Its Peripheral Circuit ratio of the current transformer, n, is calculated as
follows:

8.6. VCC Pin Overvoltage Protection ID(PEAK)


n= × R CS . (2)
VOCP
When the voltage between the VCC and GND pins
increases to VCC(OVP) = 19.0 V or more, the VCC pin
overvoltage protection (VCC_OVP) is activated. Then, Where:
the IC stops switching operation. ID(PEAK) is the drain current in the PFC_OCP operation,
After that, when the VCC pin voltage decreases to RCS is the current detection resistance of the current
VCC(P.OFF) = 8.3 V or less, the IC restarts. When the transformer (i.e., R10 in Figure 5-1), and
causes of the overvoltage condition are eliminated, the VOCP is the PFC_OCP threshold voltage (i.e., VCS(HI)).
IC automatically returns to normal operation.
2.0
PFC_OCP Threshold Voltage (V)

8.7. PFC Overcurrent Protection, PFC 1.8


Overload Protection
1.6
The MD6752 has the PFC overcurrent protection
(PFC_OCP). This function monitors the CS pin voltage 1.4
to detect a peak drain current of the power MOSFET on
a pulse-by-pulse basis, and limits the on-time of the 1.2
VGP pin when the CS pin voltage reaches the PFC_OCP 1.0
threshold voltage. The PFC_OCP threshold voltage can
be set by the CS pin, with a range of VCS(LO) to VCS(HI). 0.8
As shown in Figure 8-11, when the number of the
0.6
half-wave cycle of the AC input voltage with the
80 130 180 230 280
PFC_OCP state (i.e., the CS pin voltage exceeds the
PFC_OCP threshold voltage) becomes more than the AC Input Voltage (VAC)
fixed number of times, NOPP(AC) = 32 times, the PFC
overload protection (PFC_OLP) is activated to stop the
oscillation operations of the VGP, VGH, and VGL pins. Figure 8-12. PFC_OCP Threshold Voltage vs. AC
When the Protection Recovery Time, tAR = 3000 ms or Input Voltage
longer, elapses after that, the IC releases the PFC_OLP
operation and restarts to operate. When the causes of the
overcurrent condition are eliminated, the IC .
automatically returns to normal operation.

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8.8. PFC Overvoltage Protection VREF Pin Voltage tUVP_R tUVP_R


VREF
VREF(UVD)
The VREF pin detects an overvoltage condition of the VREF(UVP)
PFC output. Figure 8-13 depicts operational waveforms VREF(UVP_R)
0
of the PFC overvoltage protection (PFC_OVP). When t
the VREF pin voltage increases to VREF(OVP) = 2.23 V or VGP Pin Voltage
more, the PFC_OVP is activated to stop the VGP pin
oscillation and to avoid a further increase in the output
0
voltage. When the VREF pin voltage decreases to t
VREF(OVP_R) = 2.18 V or less along with a lowering in the Drain Current,
output voltage, the VGP pin resumes oscillating. In this ID(PFC)

way, the intermittent operation is repeated while the


overvoltage condition persists. When the causes of the 0
t
overvoltage condition are eliminated, the IC
automatically returns to normal operation. During the Figure 8-14. PFC_UVP Operational Waveforms
PFC_OVP operation, the VGH and VGL pins in the
LLC circuit continue their switching operations.
8.10. LLC Constant Voltage Control
VREF Pin
VREF(OVP)
Figure 8-15 is a schematic diagram of the FB, CM,
Voltage VREF(OVP_R) and VOCM pins and their peripheral circuit. On-time of
VREF the VGH pin is determined by the CM pin and FB pin
0
voltages. On-time of the VGL pin is equal to that of the
t
VGH pin. The on-time of the VGH and VGL pins
VGP Pin
Voltage including dead time is controlled by 50% duty, and the
shorter the on-time, the higher the operating frequencies.
0
The capacitor C18 is connected to the CM pin. When
t the high-side power MOSFET is turned on, the CM pin
Drain Current, voltage, VCM, increases because C18 is charged. The
ID(PFC)
capacitor C16 and the optocoupler PC1 are connected to
the FB pin. The feedback current is sunk from the FB
0
t pin by the optocoupler depending on the load, and then
FB pin voltage, VFB, is determined. The IC compares
Figure 8-13. PFC_OVP Operational Waveforms VCM and VFB with an internal comparator, and operates
the time until VCM reaches VFB as on-time. When VCM ≈
VFB, the IC turns the VOCM pin "H", and then Q6 is
8.9. PFC Undervoltage Protection turned on. Thus, C18 is discharged, and the CM pin
The VREF pin also detects an undervoltage condition voltage becomes the initial value (0 V).
of the PFC output. Figure 8-14 depicts operational In light load operation, VFB decreases as the feedback
waveforms of the PFC undervoltage protection source current increases. The IC reduces the on-times of
(PFC_UVP). When the VREF pin voltage decreases to the VGH and VGL pins, and raises their oscillation
VREF(UVD) = VREF−0.08 V or less, the on-time of the frequencies. Conversely, VFB increases in heavy load
VGP pin is lengthened. Besides, when the VREF pin operation. The IC extends the on-times of the VGH and
voltage still decreases VREF(UVP) = 1.10 V or less, the VGL pins, and lowers their oscillation frequencies. By
PFC_UVP is activated to stop the VGP pin oscillation. regulating oscillation frequencies in this manner, the IC
When the VREF pin voltage decreases even further to can stabilize an output voltage (controlled in an
VREF(UVP_R) = 0.55 V or less after that, the VGP pin inductance area).
resumes oscillating. During the non-oscillating period of In heavy load operation, when VFB rises and the peak
the VGP pin, if the VREF pin voltage does not go below of VCM reaches Current Mode Control Maximum CM
VREF(UVP_R) within t(UVP_R) = 819 ms, the VGP pin Pin Voltage, VCM(MAX) = 2.00 V or more, the LLC
resumes oscillating at the time that t(UVP_R) elapses. In overcurrent protection (LCC_OCP) is activated to limit
this way, the intermittent operation is repeated while the current on pulse-by-pulse basis. Section 8.13 provides
output undervoltage condition persists. When the causes more details on the LLC_OCP.
of the undervoltage condition are eliminated, the IC C18 should have a capacitance of about 1000 pF to
automatically returns to normal operation. 0.01 μF. Care should be taken in adjusting C18 because
During the PFC_UVP operation, the VGH and VGL C18 value depends on the maximum output power.
pins in the LLC circuit continue their switching The secondary error amplifier should be designed so
operations. that collector current passing through the optocoupler
PC1 is higher than 330 µA, i.e., higher than the absolute
maximum source current of the FB pin. In particular, the

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current transfer ratio, CTR, of the optocoupler must take range, from td(MIN) = 0.47 μs to td(MAX) = 0.56 μs, for
its performance decline over time into account in actual which the power supply operates within all the allowable
designing. C16 should have a capacitance of about operating ranges and avoids the zero voltage switching
1000 pF. (ZVS) failure shown in Figure 8-17.
Figure 8-19 depicts how a dead time varies according
C3
to the FB pin voltage. Also, ensure a margin so that
D14 R32 period in which drain current flows through body diode
28
Q3 in Figure 8-18 is longer than the dead time, and actual
VGH
R31 operations must be checked to ensure that power
27 R33
VS MOSFETs operate with the zero current switching
U1 C22 D12 (ZCS) under the following conditions:
26
VB D51 OUT(+)
– When an output power is minimum in a maximum
D11 R27 T1 C51
Q4
23 R51
VGL
R26
C20 R54 input voltage specification
20
– When an output power is maximum in a minimum
VOCM R28 C21
R52
15 D15 PC1
CM
GND FB R29 C19
D52 R53 input voltage specification
8 14 C52
DZ3
U51 R55
C18
Q6 VGL
OUT(-)

PC1 C16
VGH

Figure 8-15. FB Pin and Its Peripheral Circuit High-side Losses increased due
D–S Voltage, to hard switching
VDS(H)
VGL Pin
Voltage

0
t Voltage resonance Voltage resonance
VGH Pin
Voltage

0 Figure 8-17. Waveforms When ZVS Failure Occurs


High-side t
D–S Voltage,
VDS(H)

0 High-side Drain
High-side Current, ID(H)
Drain Current, t
ID(H) Period in which drain
current flows through
0 body diode
t
FB Pin Voltage
VFB Figure 8-18. Point to Be Checked in ZCS
0
t
CM Pin Voltage
VCM VFB 0.60

0
t 0.55
Dead Time (μs)

Figure 8-16. Current Mode Control Operational 0.50


Waveforms

0.45
8.11. LLC Dead Time
A dead time is a period of time when both of the high- 0.40
and low-side power MOSFETs in the LLC stage turn off. 0 50 100 150 200 250
When the dead time is shorter than a voltage resonance
period as in Figure 8-17, the power MOSFETs turn on LLC Oscillation Frequency (kHz)
or off during the voltage resonance period. In such case,
switching loss increases due to hard switching of the Figure 8-19. Dead Time vs. LLC Oscillation
power MOSFETs. Frequency
Be sure to set a dead time so that it falls within the

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8.12. LLC High-side Driver Undervoltage 8.14. Thermal Shutdown


Lockout When the control circuit temperature reaches
The MD6752 incorporates the high-side driver TJ(TSD) = 125 °C, the thermal shutdown (TSD) is
undervoltage lockout (VB_UVLO) between the VB and activated. The IC then stops switching operation. In the
VS pins. condition where VCC ≤ VCC(P.OFF) of 8.3 V and the
When the voltage between the VB and VS pins (i.e., control circuit temperature falls below TJ(TSD), the TSD
“VB–VS voltage”) increases to VBUV(ON) = 6.8 V or circuit is activated again. During the TSD operation, the
more, the internal high-side driver starts operating. IC stops its operation. When the causes of the
When the VB–VS voltage decreases to VBUV(OFF) = 6.4 V overheating condition are eliminated, the IC
or less, the internal high-side driver stops operating. The automatically returns to normal operation.
VB_UVLO protects the IC in case both ends of the
capacitor C22 for bootstrap circuit and the protective
diode D12 are shorted.

8.13. LLC Overcurrent Protection,


LLC Overload Protection
The LLC overcurrent protection (LLC_OCP) detects a
peak drain current of the power MOSFET on a pulse-by-
pulse basis, and limits the output power. The CM pin
detects the current flowing to the power MOSFET. In
heavy load operation, when the FB pin voltage, V FB,
rises, the peak value of CM pin voltage, VCM also rises.
When VCM reaches VCM(MAX) = 2.00 V or more, the
LCC_OCP is activated to increase oscillation frequency
and thus limits the drain current. When the LCC_OCP
condition persists for a period longer than tOLP = 5.0 ms,
the LLC overload protection (LLC_OLP) is activated to
stop the oscillation operations of the VGH, VGL, and
VGP pins. When the Protection Recovery Time,
tAR = 3000 ms or longer, elapses after that, the IC
releases the LLC_OLP operation and restarts to operate.
When the causes of the overload condition are
eliminated, the IC automatically returns to normal
operation.
During the LLC_OCP operation, the maximum output
power, PMAX, depends on C18 capacitance of the CM pin.
The smaller C18 capacitance, the higher the frequency
and the smaller PMAX. C18 should have a capacitance of
about 1000 pF to 0.01 μF.

CM Pin Voltage
VCM(MAX)

0
t
FB Pin Voltage tOLP1 tAR tOLP1
VFB(OLP)
0
t
VGL, VGH
Pin Voltage
0
t

Figure 8-20. Operational Waveforms of LCC_OCP


and LCC_OLP

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MD6752

9. External Components 10. PCB Pattern Layout


The switching power supply circuit includes high
9.1. Resonant Transformer frequency and high voltage current paths that affect the
The resonant power supply uses the leakage IC operation, noise interference, and power dissipation.
inductance of a transformer. Therefore, to reduce Therefore, PCB trace layouts and component placements
influences from eddy current and skin effect, use a play an important role in circuit designing. High-
bundle of fine litz wires as the wire of the transformer. frequency and high-voltage current loops (see Figure 10-
1) should be as small and wide as possible in order to
maintain a low-impedance state. In addition, ground
9.2. Inductor in PFC Stage
traces should be as wide and short as possible so that
Apply proper design margin to temperature rise or radiated EMI levels can be reduced.
magnetic saturation due to copper loss and iron loss.

9.3. Power MOSFET


Use a power MOSFET with a breakdown voltage,
VDSS, providing enough margin to the PFC output
voltage, VOUT(PFC). Choose a proper size of heatsink that
takes switching and on-resistance losses due to power
MOSFETs into account.

9.4. PFC Boost Diode (D1, D2)


Figure 10-1. High-frequency Current Loop
Choose a boost diode having a peak reverse voltage,
VRSM, which provides enough margin to the PFC output
voltage, VOUT(PFC). A fast recovery diode with a short Figure 10-2 is a peripheral circuit example of the IC.
reverse recovery time, trr, is recommended to reduce The following considerations should be taken into
noise and loss due to switching. Choose a proper size of account in designing pattern layouts for your application.
heatsink that takes losses caused by forward voltage, VF,
and recovery current into considerations. 1) Main Circuit Trace Layout
Traces of the PFC and LLC circuits, where switching
9.5. Input Filter currents pass through, should be as wide and looped
small as possible.
Connect the C8, C9, D9, and D10 in addition to the pi
filter (C1, C2, and L1) to the input side. Connect the 2) Logic Ground Trace Layout
film capacitors C8 and C9 (about 600 V / 0.1 μF~ If a large current flows through a logic ground,
1.0 μF) to the input side. Connect the general-purpose electric potential across the logic ground may vary and
rectifier diodes D9 and D10 to the input side. C8, C9, thus cause the IC to malfunction. Ground traces should
D9, and D10 should be selected based on the operation be as wide and short as possible.
performance checked with an actual board. Logic ground traces should be designed as close as
possible to the GND pin, at a single-point ground (or
9.6. Output Capacitor (C51) star ground) that is separated from the main circuit. Do
not connect the PGND pin to these traces. Traces of the
Apply proper design margin to ripple current, ripple
ground (i.e., the capacitors of the GND, PGND, and
voltage, and temperature rise. A low-ESR capacitor is
VCC pins) should be separately connected at a single-
recommended to reduce ripple voltage, in terms of
point ground whose connection is configured to the root
designing switch-mode power supplies.
of the output capacitor C3 in the PFC stage.
9.7. Current-resonant Capacitor (C21) 3) Peripheral Connections to VCC Pin
Because large resonant current flows through C21, it Traces connected to the VCC pin should be looped
should be a capacitor that supports high-current small as possible because the pin supplies power to the
applications with small losses such as a polypropylene IC. Connect the film capacitor C12 (about 0.1 μF to 1.0
film capacitor. High-frequency current flows through μF) between the VCC and GND pins with a minimal
C21; therefore, capacitor-specific frequency length of traces.
characteristics must also be taken into account.

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MD6752

4) Peripheral Connections to VB Pin


The components of the bootstrap circuit connected
between the VCC and VB pins (D13, R30) should be
placed as close as possible to the IC. The capacitor C22
connected between the VB and VS pins should also be
placed with a minimal length of traces.

5) Components for Logic Control System


These components should be placed close to the IC,
and be connected to the corresponding pin of the IC with
a minimal length of traces.

6) Secondary Rectifier Smoothing Circuit


This is the secondary main circuit, in which switching
current flows, should be wide and looped small as
possible.

1) Designed as wide 2) Connected to the root of 3) Looped as small as


and short as possible C3 with dedicated pattern possible
C1 L1 C2 L2 D1

VAC
L3 D2
C3
D4

D3
R12 External power supply
C8 C9 Q1
R13
Q2 4) Looped as small
D9 D10 R14 D13 as possible
R30 Q3
R15 6) Designed as wide
NC VGH
1 28 and short as possible
R10 VS
2 27
A2 VB T1
3 26
PGND C22 D51
4 25
C10 R9 VGP A0
5 24 Q4 C51
R17 C12 VCC VGL C20
6 23
2) Connected to the root of BASE U1 SCID
C21
7 22 Debug
R18 GND MD6752 GPIO04
C3 with dedicated pattern 8 21 D52
AVCC VOCM
R19 C13 9 20
DVCC GPIO01 C19
C14 10 19
VREF GPIO03 R29
R20 C15 11 18
CS GPIO02
5) Placed near the IC with a R16 12 17
VSEN VCORE CY
13 16
minimum length of traces FB CM
D15
C16 14 15 DZ3
C17
C18

C25
R22
R23
R24

R25

R21 PC1
Q6
C24

Figure 10-2. Example Connections to IC and Its Peripheral Circuits

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MD6752

Important Notes
● All data, illustrations, graphs, tables and any other information included in this document (the “Information”) as to Sanken’s
products listed herein (the “Sanken Products”) are current as of the date this document is issued. The Information is subject to any
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your name and seal, on the specification documents of the Sanken Products and return them to Sanken, prior to the use of the
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Applications or in manner not in compliance with the instructions set forth herein.
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such uses in advance and proceed therewith at your own responsibility.
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DSGN-CEZ-16003

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