Transition Guideline

Rev1.2 06/26/2009
Physical Design Group, Vikas Amrelia

Definitions:
• Transition time = slope. It is the time it takes a signal to switch from logic low to high (or
vice versa). Usually measured from the linear portion of the waveform or certain % of vdd
(such as 30% to 70% of vdd in 65nm process library or 20% to 80% of vdd in 90nm
library).
• Max Transition: The maximum transition (max_tran) that a cell pin can have or a design
can have overall. It can be listed by default in the library (.lib) or defined globally in the
APR tool or timing tool.

Transition time
degrades over
vdd wires

% vdd

Transition
time
% vdd

How Transition Impacts Design

There are three key areas that a transition can impact:

1. Increased power consumption
2. Hot Electron Effect (decreased reliability)
3. Decreased attainable frequency
4. Accuracy of .lib model
5. Make design more or less Si-prone.

1. Increased Power Consumption:

Momentary shorts between power and ground occur due to an imperfect signal transition.
This is known as crowbar current. In any given static CMOS cell, both p-mos and n-mos
transistors can conduct simultaneously for a period, providing this temporary short. This generally
occurs with slow transition inputs.

Cells with a weak / slow transition input are most susceptible to a crowbar current effect.
Cells with a strong / fast transition input are least susceptible to a crowbar current effect.
Figure 1: Example power consumption waveforms

~170 uAmp Crowbar

51ps slope

Peak ~300uAmp Crowbar

for long Time

806ps slope

2. Hot Electron Effect:

In general terms, the hot electron effect shifts the threshold voltage of a transistor until the
device is ineffective. The effect can be a side effect of the crowbar current as defined above.

Cells with a smaller load and slower input transition are least susceptible to this effect.
Cells with a larger load and faster input transition are most susceptible to this effect.

APR engineer do not need to fix hot electron effect explicitly since library characterization
already account for this effect.

3. Decreased Attainable Frequency:

Frequency can be directly impacted by slow transitions. If a critical setup-timing path contains
a slow transition, fixing that slope can lead to a critical path solution. Slow transition impacts SI
delta delay which impacts both setup SI and hold SI negatively.

The APR tool must be aware of maximum transition limits in order to maintain generally
consistent slopes on all nets. This eliminates slope as a factor in frequency improvement. Slow
nets should be fixed by the tool if a “max transition limit” is set.
4. Accuracy of .lib model

Cell delay and output transition time is represented in library files as lookup-tables. It is
assumed that cell delay is based on input transition time and output load. Library team will run
various Spice simulations at different slew rates and different output capacitance values and
accumulate delay and transition time values. These values are then placed in four lookup-tables
that are indexed by input transition time and output load. The four tables for each cell are: rise cell
delay, fall cell delay, rise output transition, and fall output transition. Values for cell delay and
transition time are then simply looked up using the input transition time and output capacitance
numbers.
Staying within the characterization range is very important. If transition violation falls
outside this range then timing analysis tools will extrapolate its impact on timing which may not be
accurate.

5. Make design more or less Si-prone

A net with strong transition can serve as aggressor while weak transition can serve as
victim. This will have direct impact on setup and hold.
Transitions in a LIB file

Lib files define a max transition limit based on characterization data. The APR tool should
consider this limit along with net capacitance. There should be a different maximum transition
limit for slow, fast, and typical corners as well for different threshold voltage.

Note that in 150/90nm Marvell library there is no max transition set, but 65nm onwards it
does.

Example: 65G/LP Marvell Library Transition Limits

Marvell Marvell
(65g, s110, rev2.1) (65lp, s110, rev2.2)

Slow:0.9v, 125c: 459ps 1187ps

Typical:1.0v, 110c 316ps 517ps

Fast:1.1v, 0c 236ps 443ps

Example: Marvell S110 Library (65nm) look up table (slow corner)

lu_table_template ( delay_template_7x7 ) {
variable_1 : total_output_net_capacitance ;
variable_2 : input_net_transition ;
____________________________________________________________________________________
timing ( ) {
related_pin : "A" ;
timing_sense : positive_unate ;
cell_rise ( delay_template_7x7 ) {
index_1 ( "0, 0.0015, 0.003, 0.006, 0.012, 0.024, 0.048" ) ;
index_2 ( "0.004, 0.0256, 0.036, 0.0632, 0.12, 0.2312, 0.4592" ) ;
values ( \
"0.051583, 0.056857, 0.059216, 0.065389, 0.077954, 0.096784, 0.121616", \
"0.064653, 0.069769, 0.072157, 0.078384, 0.090705, 0.110526, 0.137512", \
"0.075223, 0.080371, 0.082734, 0.088908, 0.101212, 0.121365, 0.149431", \
"0.094299, 0.099414, 0.101806, 0.107944, 0.120217, 0.140498, 0.169681", \
"0.130617, 0.135639, 0.138025, 0.144195, 0.156456, 0.176723, 0.20635", \
"0.202063, 0.207071, 0.209261, 0.215305, 0.227743, 0.247908, 0.277449", \
"0.343159, 0.347725, 0.349487, 0.355549, 0.368328, 0.388451, 0.417641") ;

Example: 55G/LP Marvell Library Transition Limits

Marvell Marvell
PVT
(55g, s110, rev2.2) (55lp,s110, rev2.2)

Slow:0.9v, 125c: 370ps 1187ps

Typical:1.0v, 110c 265ps 710ps

Fast:1.1v, 0c 186ps 443ps

Example: 40G/LP Marvell Library Transition Limits

Marvell Marvell
PVT (40g, m12szd_m1std, (40lp, m12szd_ls,
rev2.2) rev2.1)

Slow:0.81v, 125c: 570ps 506ps

Typical:0.9v, 110c 369ps 302ps (25c)

Fast:0.99v, 0c 244ps 192ps

Suggested Transition Guidelines

Normally in design there are four different types of nets that we are concern about transition.

1. Clock nets
2. Critical timing path nets
3. Nets in normal functional path.
4. Static signal.

Clock nets and critical timing path nets:

Transition violation on clock nets and critical timing path nets is normally fixed by APR
tool automatically. These nets may have sharp transition time in order to meet performance
requirement.

Clock and critical timing path nets transition must be fixed. Engineers should write P&R
and PT checks for them, where the other two can be fixed selectively.

Clock transition should be fixed with respect to clock transition limit which is usually
tighter requirement than signal nets. As a rule of thumb, designer can set clock max transition
limit ½ of standard cell max transition limit defined in LIB file. Engineer need to make a call on
trade off between power and performance when choosing aggressive slew limit for clock nets.
Also clock latency and skew will get impacted by chosen slew limit. Project needs to make call
based on these impacts to choose clock transition limit.

For nets in normal functional path:

The max transition number can be set by a number of factors. The most important factor
is to make sure the transitions in the design are within the characterized range of the library. If
some net transitions are greater than the library characterized range, then the resulting calculated
cell delays could become less accurate.

If transition violations can not be fixed for max transition defined in LIB file, than P&R
engineer and FE teams needs to work together for decision on waiver.

Consider timing margin and how many times the net switches to decide on waiver. For
example efuse net might be switching logical value only once and it may not require fixing
transition violation on this net.
Static signal nets:

It is design dependent. Scan test mode signals, efuse nets, net out of analog pads etc.
can be waived if transition violation can not be fixed since it does not impact performance of the
chip. If it is easy to fix transition violation than fix it.

Exceptions:

Projects may set a more aggressive max transition limit if they have done simulations that
show a need for a shorter slopes (such as from deep sub-micron effects like signal electro-
migration or transistor hot-electrons that get worse with longer slopes).

For most projects, if avaliable, the library default max transition can be sufficient.
If a project has data that mandates a shorter max transition (or maybe the library doesn’t
have a default to begin with), then it is important that this number not be too aggressive.
Sharper max_trans can lead to larger cells, more buffers, more area, more power.
To set a global max_transition, can use these example commands:
o Magma: force limit slew $m 500p
o PrimeTime/DC/ICC: set_max_transition 0.5 [current_design]

Summary:

1. Transition violations on clock nets and critical paths nets should be fixed based on max
transition limit defined in standard cells library. Engineers must write P&R and PT checks
for them, where the other two can be fixed selectively.

2. SI based transition violations will not require to be fixed if project decides not to do SI
based setup timing analysis. SI based setup timing analysis is recommended but not
required as mentioned in document “90nm and 65nm Timing Signoff Guidelines” at:
http://nano/cad/pnr/pdd/home/doc/Guidelines_for_Physical_Design_Group/90nm_and_6
5nm_Timing_Signoff_Guidelines.pdf.

3. APR engineer should set max transition limit in design (ideally max transition limit defined
in library). APR tool should address most of transition violation and fix it.

4. Any transition violations on non timing critical nets or static signals need to be handled
case by case basis. If it is easy to fix these violations without impacting schedule, than
APR engineers should fix it. If it can not be fixed easily or schedule does not permit the
fixes, work with project for waiver.

5. In the case of low frequency designs, some slow slopes may be alright and project team
can waive this case by case basis.