CHAPTER 2

Basic Computer Organization and Design

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Chapter 2 content

2-1 Instruction Codes

2-2 Computer Registers
2-3 Computer instructions
2-4 Timing and Control
2-5 Instruction Cycle
2-6 Memory Reference instructions
2-7 Input-Output and Interrupt
2-8 Complete Computer Description
2-9 Design of Basic Computer
2-10 Design of Accumulator Logic
• Design of Accumulator Logic
• Design of ALU Logic

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Chapter 2 content

2-1 Instruction Codes

2-2 Computer Registers
2-3 Computer instructions
2-4 Timing and Control
2-5 Instruction Cycle and Register Reference Instructions
• Instruction Cycle
• Register Reference Instructions
2-6 Memory Reference instructions
2-7 Input-Output and Interrupt
2-8 Complete Computer Description
2-9 Design of Basic Computer
2-10 Design of Accumulator Logic

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5-1 Instruction Codes

The Basic Computer

Every different processor type has its own design:

▪ different registers
▪ different buses
▪ different microoperations
▪ different machine instructions,
▪ etc.

:‫كل نوع مختلف من المعالجات له تصميمه الخاص‬

‫سجالت مختلفة‬ ▪

‫ناقالت (للبيانات و العناوين) مختلفة‬ ▪

‫عمليات دقيقة مختلفة‬ ▪

‫تعليمات مختلفة‬ ▪

.‫إلخ‬ ▪

Modern processor is a very complex device It contains:

▪ Many registers
▪ Multiple arithmetic units, for both integer and floating-point calculations
▪ The ability to pipeline several consecutive instructions to speed execution etc.

:‫المعالج الحديث جهاز معقد جدا ويحتوي على‬

‫العديد من السجالت‬ ▪

‫ لكل من حسابات األعداد الصحيحة والكسور‬، ‫وحدات حسابية متعددة‬ ▪

.‫القدرة على توجيه عدة تعليمات متتالية لتسريع التنفيذ وما إلى ذلك‬ ▪

However, to understand how processors work, we will start with a simplified processor model.
This is similar to what real processors were like ~25 years ago.

.‫ سنبدأ بنموذج معالج مبسط‬، ‫ لفهم كيفية عمل المعالجات‬، ‫علي الرغم من ذلك‬

.‫ عا ًما تقريبًا‬25 ‫هذا مشابه لما كانت عليه المعالجات الحقيقية منذ‬

M. Morris Mano introduces a simple processor model he calls the Basic Computer

‫قدم لنا العالم موريس مانو نموذج معالج بسيط و سماه الكمبيوتر األساسي‬

We will use this to introduce processor organization and the relationship

of the RTL model to the higher-level computer processor.

.‫ بمعالج الكمبيوتر‬RTL ‫سوف نستخدم هذاالنموذج المبسط لفهم تركيب المعالج وعالقة نموذج‬

The Basic Computer

The Basic Computer has two components: :‫يتكون الكومبيوتر من‬

▪ processor ‫المعالج‬
▪ memory‫الذاكرة‬

The memory has 4096 words in it.

▪ 𝟒𝟎𝟗𝟔 = 𝟐𝟏𝟐 , so, it takes 12 bits to select a word in memory.
▪ Each word is 16 bits long.

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By Eng. Emad Mahdy

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 The Instruction Format

Program: sequence of (machine) instructions

(Machine) Instruction: group of bits that tell the computer to perform a specific operation (a sequence of micro-operation)

▪ The instructions of a program, along with any needed data are stored in memory.
▪ The CPU reads the next instruction from memory and place it in an Instruction Register (IR)
▪ Control circuitry in control unit then translates the instruction into the sequence of microoperations necessary to implement it.

The Instruction Format

A computer instruction is often divided into two parts:

▪ An opcode (Operation Code) that specifies the operation for that instruction.
▪ An address that specifies the registers and/or locations in memory to use for that operation.
In the Basic Computer, since the memory contains 𝟒𝟎𝟗𝟔 = 𝟐𝟏𝟐 words, we need 12 bits to specify which memory address this instruction will use.

In the Basic Computer, bit 15 of the instruction specifies the addressing mode:
0: direct addressing
1: indirect addressing
Since the memory words, and hence the instructions, are 16-bits long, that leaves 3 bits for the instruction’s opcode.

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 Addressing Modes

Addressing
Mode

Direct Indirect
address address

Direct address Indirect address

Direct address: the address in memory of the data to use (the address Indirect address: the address in memory of the address in memory
of the operand) of the data to use

Effective Address (EA) The address, that can be directly used without modification to access an operand for a computation-type instruction, or as the target address
for a branch-type instruction.

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 5-2 Computer Registers

Register Description

Program Counter (PC) ▪ Program Counter (PC) that holds the memory address of the next instruction to get.
▪ Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits.

Address Register (AR) ▪ In a direct or indirect addressing, the processor needs to keep track of what locations in memory it is addressing:
▪ The Address Register (AR) is used for this.
▪ The AR is a 12-bit register in the Basic Computer

Instruction Register (IR) Instruction Register (IR) holds instruction code

Data Register (DR) ▪ When an operand is found, using either direct or indirect addressing, it is placed in the Data Register (DR).
▪ The processor then uses this value as data for its operation.

Accumulator (AC) The Basic Computer has a single general-purpose register – the Accumulator (AC)

The significance of a general-purpose register is that it can be referred to in instructions.

▪ e.g., load AC with the contents of a specific memory location; store the contents of AC into a specified
memory location.

Temporary Register (TR) ▪ Often a processor will need a scratch register to store intermediate results or other temporary data.
▪ in the Basic Computer this is the Temporary Register (TR)

▪ The Basic Computer uses a very simple model of input/output (I/O) operations.
I/O registers (INPR- OUTR) ▪ Input devices are considered to send 8 bits of character data to the processor.
▪ The processor can send 8 bits of character data to output devices.

▪ The Input Register (INPR) holds an 8-bit character gotten from an input device.

▪ The Output Register (OUTR) holds an 8-bit character to be send to an output device.

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 Common Bus System

The basic computer has

- 8 registers
- memory unit
- control unit
- ALU
- Bus System

The registers in the Basic Computer are connected using a bus and this gives savings in circuitry over complete connections between registers.
.‫ باستخدام ناقل موحد وهذا يوفر في الدوائر و التوصيالت بين السجالت‬basic computer ‫يتم توصيل السجالت في ال‬

‫رسمة الكتاب‬ ‫رسمة المحاضرة‬

▪ Three control lines, 𝐒𝟐 , 𝐒𝟏 , and 𝐒𝟎 control which register the bus selects as its input.

▪ Either one of the registers will have its load signal activated, or the memory will have its read signal activated will determine where the data from the bus gets loaded.

▪ The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4-bit positions.

▪ When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on the bus.

▪ Five registers have three control inputs:

• LD (load)
• INR (increment)
• CLR (clear)

▪ the result of an addition is transferred to AC and the end carry-out of the addition is transferred to flip-flop E (extended AC bit).

▪ The input data and output data of the memory are connected to the common bus, but the memory address is connected to AR . Therefore, AR must
always be used to specify a memory address

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 5-3 Computer instructions

Basic Computer Instruction Format

Register-Reference Instructions Memory-Reference Instructions (I/O)Input-Output Instructions

Opcode = 𝟏𝟏𝟏 Opcode = 𝟎𝟎𝟎 → 𝟏𝟏𝟎 Opcode = 𝟏𝟏𝟏

𝐈 = 𝟎 𝐈 = 𝟎→𝟏 𝐈 = 𝟏

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 5-4 Timing and Control
• Control unit (CU) of a processor translates from machine instructions to the control signals for the microoperations that implement them.

• Control units are implemented in one of two ways:

Hardwired Control Microprogrammed Control

Hardwired Control: CU is made up of sequential and combinational circuits to Microprogrammed Control: A control memory on the processor contains
generate the control signals microprograms that activate the necessary control signals.

Note: We will consider a hardwired implementation of the control unit for the Basic Computer

▪ Bit 15 of the instruction is transferred to a flip-flop designated by the symbol I.

▪ The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder.
▪ The eight outputs of the decoder are designated by the symbols D0 through D7•
▪ The subscripted decimal number is equivalent to the binary value of the corresponding operation code.
▪ Bits 0 through 11 are applied to the control logic gates.

Timing Signals

▪ The outputs of the counter are decoded into 16 timing signals T0 through T15•
▪ The sequence counter SC can be incremented or cleared synchronously
▪ Most of the time, the counter is incremented to provide the sequence of timing signals out of the 4 x 16 decoder.
▪ Once in a while, the counter is cleared to 0, causing the next active timing signal to be T0.

▪ As an example
o consider the case where SC is incremented to provide timing signals T0, T1 T2, T3, and T4 in sequence.
o At time T4, SC is cleared to 0 if decoder output D3 is active.
o This is expressed symbolically by the statement

𝑫𝟑𝑻𝟒: 𝑺𝑪 ← 𝟎

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 5-5 Instruction Cycle

‫استخراج التعليمة من الذاكرة‬

T 0: AR  PC
Fetch T 1: IR  M [AR] , PC  PC + 1

‫معرفة نوع التعليمة‬

T 2: I  IR(15) , D0, . . . ,D7  Decode IR(12-14), AR  IR(0-11)
Decode
‫تنفيذ التعليمة‬
̅̅̅̅
𝑫𝟕 𝑰 𝑻𝟑 : 𝑨𝑹 ← 𝑴[𝑨𝑹]
̅̅̅̅ 𝑰̅ 𝑻𝟑 : 𝑨𝑹
𝑫𝟕 ← 𝑵𝒐𝒕𝒉𝒊𝒏𝒈
Execute 𝑫𝟕 𝑰̅ 𝑻𝟑 : 𝑨𝑹 ← 𝑬𝒙𝒆𝒄𝒖𝒕𝒆 𝒂 𝒓𝒆𝒈𝒊𝒔𝒕𝒆𝒓 − 𝒓𝒆𝒇𝒆𝒓𝒆𝒏𝒄𝒆 𝒊𝒏𝒔𝒕𝒓𝒖𝒄𝒕𝒊𝒐𝒏.
𝑫𝟕 𝑰 𝑻𝟑 : 𝑨𝑹 ← 𝑬𝒙𝒆𝒄𝒖𝒕𝒆 𝒂𝒏 𝒊𝒏𝒑𝒖𝒕 − 𝒐𝒖𝒕𝒑𝒖𝒕 𝒊𝒏𝒔𝒕𝒓𝒖𝒄𝒕𝒊𝒐𝒏.

𝐃𝟕 𝐈 𝐓𝟑
̅̅̅̅
𝑫𝟕 ̅𝑰 𝑻𝟑 : 𝟎 𝟎 𝟏 𝐍𝐨𝐭𝐡𝐢𝐧𝐠
̅̅̅̅
𝑫𝟕 𝑰 𝑻𝟑 : 𝟎 𝟏 𝟏 𝐀𝐑 ← 𝐌[𝐀𝐑]
𝑫𝟕 𝑰̅ 𝑻𝟑 : 𝟏 𝟎 𝟏 Execute a register-reference instruction.
𝑫𝟕 𝑰 𝑻𝟑 : 𝟏 𝟏 𝟏 Execute an input-output instruction.

• Initially, the program counter PC is loaded with the address of the first instruction in the program.
• The sequence counter SC is cleared to 0, providing a decoded timing signal To

Register-Reference Instructions Memory-Reference Instructions Input-Output Instructions

𝐎𝐏 − 𝐜𝐨𝐝𝐞 = 𝟏𝟏𝟏 𝐎𝐏 − 𝐜𝐨𝐝𝐞 = 𝟎𝟎𝟎 → 𝟏𝟏𝟎 𝐎𝐏 − 𝐜𝐨𝐝𝐞 = 𝟏𝟏𝟏
𝐈 = 𝟎 𝐈 = 𝟎→𝟏 𝐈 = 𝟏

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Register Reference Instructions

Register Reference Instructions

r: SC  0 Clear SC
CLA rB11: AC  0 Clear AC
CLE rB10: E0 Clear E
CMA rB9: AC  AC’ Complement AC
CME rB8: E  E’ Complement E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0) Circulate right
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15) Circulate left
INC rB5: AC  AC + 1 Increment AC (AC=AC+1)
SPA rB4: if (AC(15) = 0) then (PC  PC+1) Skip next instruction if AC > 0 (positive)
SNA rB3: if (AC(15) = 1) then (PC  PC+1) Skip next instruction if AC < 0 (negative)
SZA rB2: if (AC = 0) then (PC  PC+1) Skip next instruction if AC=0
SZE rB1: if (E = 0) then (PC  PC+1) Skip next instruction if E=0
HLT rB0: S  0 (S is a start-stop flip-flop) Halt computer (stops the sequence
counter from counting)

𝐫 = 𝐃𝟕 𝐈 ′ 𝐓𝟑 Register Reference Instructions

𝐁𝐢 = 𝐈𝐑(𝐢) bit in IR(0-11) that specifies the operation), i=0,1,3,…11
𝐁𝐢 → 𝐛𝐢𝐭 𝐢 𝐢𝐧 𝐈𝐑 𝐑𝐞𝐠𝐢𝐬𝐭𝐞𝐫

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 5-6 Memory Reference instructions

AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

Symbol Operation Symbolic Description RTL

Decoder
AND AND to AC D0 AC  AC  M[AR]

ADD ADD to AC D1 AC  AC + M[AR], E  Cout

LDA Load to AC D2 AC  M[AR]

STA Store AC D3 M[AR]  AC

BUN Branch D4 PC  AR
Unconditionally
BSA Branch and Save D5 M[AR]  PC, PC  AR + 1
Return Address
ISZ Increment and D6 M[AR]  M[AR] + 1,
Skip-if-Zero if M[AR] + 1 = 0
then PC  PC+1

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By Eng. Emad Mahdy

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 Flowchart For Memory Reference Instructions

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5-7 Input-Output and Interrupt

The output register INPR works as follows.

• Initially, the input flag FGI = 0.
• When a key is struck in the keyboard, an 8-bit alphanumeric code is shifted into INPR and the input flag FGI is set to 1.
• As long as the flag is set, the information in INPR cannot be changed by striking another key.
• The computer checks the flag bit; if it is 1, the information from INPR is transferred in parallel into AC and FGI is cleared to 0.
• Once the flag is cleared, new information can be shifted into INPR by striking another key.
The output register OUTR works similarly but the direction of information flow is reversed.
• Initially, the output flag FGO=1.
• The computer checks the flag bit; if it is 1, the information from AC is transferred in parallel to OUTR and FGO is cleared to 0.
• The output device accepts the coded information, prints the corresponding character, and when the operation is completed, it sets FGO to 1 .
• The computer does not load a new character into OUTR when FGO is 0 because this condition indicates that the output device is in the process of
printing the character.

❖ The terminal sends and receives serial information.

❖ The serial info. from the keyboard is shifted into INPR
❖ The serial info. for the printer is stored in the OUTR
❖ INPR and OUTR communicate with the terminal serially and with the AC in parallel.
❖ The flags are needed to synchronize the timing difference between I/O device and the computer.

INPR Input register - 8 bits

OUTR Output register - 8 bits
FGI Input flag - 1 bit
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

𝐩 = 𝐃 𝟕𝐈𝐓𝟑
𝐁𝐢 = 𝐈𝐑(𝐢), 𝐢 = 𝟔, … , 𝟏𝟏

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By Eng. Emad Mahdy

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 5-8 Complete Computer Description

(Flowchart of operations):

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 Complete Computer Description (Microoperations)

Complete Computer Description (Microoperations)

Control function

Memory-Reference

Register-Reference

Input-Output Reference

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 5-9 Design of Basic Computer

❖ Hardware Components of BC (Basic Computer)

▪ A memory unit: 4096 x 16.

▪ Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
▪ Flip-Flops (Status): I, S, E, R, IEN, FGI, and FGO
▪ Decoders: a 3x8 Opcode decoder - a 4x16 timing decoder
▪ Common bus: 16 bits
▪ Control logic gates:
▪ Adder and Logic circuit: Connected to AC

❖ Control Logic Gates

▪ Input Controls of the nine registers (CLR, INC, LD)

▪ Read and Write Controls of memory.
▪ Set, Clear, or Complement Controls of the flip-flops.
▪ S2, S1, S0 Controls to select a register for the bus.
▪ AC, and Adder and Logic circuit

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 Control of registers and memory
❖ Address Register; AR

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 5-10 Design of Accumulator Logic

❖ All the statements that change the content of AC

Control of ac register
❖ Gate structures for controlling the LD, INR, and CLR of AC

ALU (adder and logic circuit)

❖ One stage of Adder and Logic circuit

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