Dept.

of ECE, AJIET, Mangaluru BEC302

Programmable Logic Devices (PLDs)

Programmable Logic Devices PLDsPLDs are the integrated circuits. They contain an array of
AND gates & another array of OR gates. There are three kinds of PLDs based on the type of
arrayss, which has programmable feature.
• Programmable Read Only Memory
• Programmable Array Logic
• Programmable Logic Array

The process of entering the information into these devices is known as programming. Basically,
users can program these devices or ICs electrically in order to implement the Boolean functions
based on the requirement. Here, the term programming refers to hardware programming but not
software programming.

In order to show the internal logic diagram for such technologies in a concise form, it is necessary
to have special symbols for array logic. Figure shows the conventional and array logic symbols for
a multiple input AND and a multiple input OR gate.

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Dept. of ECE, AJIET, Mangaluru BEC302

Programmable Logic Devices (PLDs)

PLD’s are Standard logic devices that can be programmed to implement any
combinational logic circuit. Programmable refers to a hardware process used to specify
the logic that a PLD implements.
There are various types of PLD devices based on which array is programmable
The Device names and the type of array are listed in the table below.

Types of PLDs

DEVICE AND array OR array

PROM Fixed Programmable

PLA Programmable e
Programmable
PAL Programmable Fixed e
Programmable Logic Arrays (PLAs)
ee
Similar concept as in PROM, except that a PLA does not necessarily generate all possible
minterms (ie. the decoder is not used). More precisely, in PLAs both the AND and OR arrays can
be programmed (in PROM, the AND array is fixed – the decoder – and only the OR array can be
programmed).

PLA Example

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Dept. of ECE, AJIET, Mangaluru BEC302

f(a,b,c) = a’b’ + abc

g(a,b,c) = a’b’c’ + ab + bc
h(a,b,c) = c
PLAs can be more compact implementations than ROMs, since they can benefit from minimizing the
number of products required to implement a function.

Example 2

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Dept. of ECE, AJIET, Mangaluru BEC302

Programmable Array Logic (PAL)

• OR plane (array) is fixed, AND plane can be programmed

• A PAL is less Less flexible than PLA
• Number of product terms available per function (OR outputs) is limited
Example 1:

• X =AB + AC’
Y= AB’ + BC’

• Example 2

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Dept. of ECE, AJIET, Mangaluru BEC302

Three Fundamental Types of PLDs:

The three fundamental types of PLDs differ in the placement of programmable

connections in the AND-OR arrays. Figure shows the locations of the programmable
connections for the three types.

• The PROM (Programmable Read Only Memory) has a fixed AND array (constructed as a
decoder) and programmable connections for the output OR gates array. The PROM
implements Boolean functions in sum-of-min terms form.

The PAL (Programmable Array Logic) device has a programmable AND array and fixed
connections for the OR array.

The PLA (Programmable Logic Array) has programmable connections for both AND and
OR arrays. So it is the most flexible type of PLD.

The ROM (Read Only Memory) or PROM (Programmable Read Only

Memory):

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Dept. of ECE, AJIET, Mangaluru BEC302

The input lines to the AND array are hard-wired and the output lines to the OR array are
programmable.

Each AND gate generates one of the possible AD products (.e., i minterms).

The PLA (Programmable Logic Array):

In PLAs, instead of using a decoder as in PROMs, a number (k) of AND gates is used
where k<2n, (n is the number of inputs).

Each of the AND gates can be programmed to generate a product term of the input
variables and does not generate all the minterms as in the ROM.
The AND and OR gates inside the PLA are initially fabricated with the links (fuses)
among them.

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Dept. of ECE, AJIET, Mangaluru BEC302

Question bank
1. What is magnitude comparator? Design a two bit digital comparator by writing TT,
relevant expression and logic diagram.
2. Implement the following functions using 3:8 decoder(IC-74138)
i. f(a, b, c, d) = πM(2, 4, 5, 7, 9, 10, 13, 14)
ii. ii) f(a, b, c, d) = ∑m(1, 3, 5, 8, 12, 14, 15)
3. Explain Carry look ahead adder with neat diagram and relevant expressions.
4. Implement f(a, b, c, d) = ∑m(0, 1, 5, 6, 10, 12, 14, 15) using
i. 8:1 MUX with a, b, c as select lines.
ii. 4:1 MUX with a, b as select lines.
5. Implement the following function using 74138 Decoder
i. f1(a, b, c) = πM(2, 3, 4, 5, 7)
ii. f2(a, b, c) = ∑m(1, 3, 5)
6. Implement f(a, b, c ,d) = ∑m(0, 1, 5, 6, 7, 10, 15) using 8:1 MUX with a, b, c as select lines
7. Design a 4 to 16 decoder by cascading 2 to 4 decoders.
8. Design an 8:1 MUX using only 2:1 Multiplexers.
9. Design a full adder by constructing the truth table and simplify the output equations.
10. Design one-bit comparator circuit, represent truth table, k-maps and logic diagram.
11. Implement 4-bit parallel adder/subtractor using 4-full adders blocks. Explain its operation,
if Cin = 0 the circuit should act as adder and if Cin = 1 the circuit act as subtractor.
12. Implement the function using 8:1 MUX,
F(a, b, c, d) = ∑m(0, 1, 3, 4, 7, 10, 11, 14, 15)
13. Construct an 16:1 MUX using 4:1 and 2:1 multiplexers and hence analyze using truth table

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