Unit-1 Notes
Unit-1 Notes
denotes a transfer of the content of register R1 into register R2. It designates a replacement
of the content of R2 by the content of R l . By definition, the content of the source register R1
does not change after the transfer.
Normally, we want the transfer to occur only under a predetermined control condition. This
can be shown by means of an if-then statement.
• The control condition is terminated with a colon. It symbolizes the requirement that the
transfer operation be executed by the hardware only if P = 1 .
• Every statement written in a register transfer notation implies a hardware construction for
implementing the transfer.
Basic Symbols for Register Transfers:
Bus and Memory Transfers
• Bus is a path(a group of wires), over which information is transferred from
any of several source to destination.
• A more efficient scheme for transferring information between registers in a
multiple-register configuration is a common bus system.
• Control signals determine which register is selected by the bus during each
particular register transfer.
• One way of constructing a common bus system is with multiplexers.
• The construction of a bus system for four registers:
- Each register has four bits, numbered 0 through 3.
- The bus consists of four, 4 x 1 multiplexers each having four data inputs, 0
through 3, and
- two selection inputs, S1 and S0•
• The two selection lines S1 and S0 are connected to the selection inputs of all four
multiplexers. The selection lines choose the four bits of one register and transfer them
into the four-line common bus.
• Function table for bus:
• Note: The size of each multiplexer must be k x 1 since it multiplexes k data lines.
• For example, a common bus for eight registers of 16 bits each requires 16
multiplexers, one for each line in the bus.
• Each multiplexer must have eight data input lines and three selection lines to multiplex
one significant bit in the eight registers.
Example
• A digital computer has a common bus system for 16 registers of 32
bits each. The bus is constructed with multiplexers.
a. How many selection inputs are there in each multiplexer?
b. What size of multiplexers are needed?
c. How many multiplexers are there in the bus?
• Consider a memory unit that receives the address from a register, called the address
register, symbolized by AR . The data are transferred to another register, called the data
register, symbolized by DR . The read operation can be stated as follows:
This causes a transfer of information into DR from the memory word M selected by the address in AR.
• The addition and subtraction operations can be combined into one common circuit by
including an exclusive-OR gate with each full-adder.
• A 4-bit adder-subtractor circuit:
• The mode input M controls the operation. When M = 0 the circuit is an adder and when M
= 1 the circuit becomes a subtractor.
• Each exclusive-OR gate receives input M and one of the inputs of B. When M = 0, we have
B 0 = B. The full-adders receive the value of B, the input carry is 0, and the circuit
performs A plus B .
• When M = 1, we have B 1 = B' and C0 = 1. The B inputs are all complemented and a 1
is added through the input carry. The circuit performs the operation A plus the 2's
complement of B.
• For unsigned numbers, this gives A - B if A >= B or the 2's complement of (B - A) if
A < B.
Binary lncrementer
The increment micro-operation adds one to a number in a register. For example, if a 4-bit
register has a binary value 0110, it will go to 0111 after it is incremented
..
• where A is the 4-bit binary number at the X inputs and Y is the 4-bit binary number at the
Y inputs of the binary adder. Cin is the input carry, which can be equal to 0 or 1.
• Note that the symbol + in the equation above denotes an arithmetic plus.
• By controlling the value of Y with the two selection inputs S1and S0 and making Cin equal
to 0 or 1, it is possible to generate the eight arithmetic micro-operations
• It has four full-adder circuits that constitute the 4-bit adder and four multiplexers for
choosing different operations.
• There are two 4-bit inputs A and B and a 4-bit output D.
• The four inputs from A go directly to the X inputs of the binary adder.
• Each of the four inputs from B are connected to the data inputs of the multiplexers.
The multiplexers data inputs also receive the complement of B.
• The other two data inputs are connected to logic-0 and logic-1 . Logic-0 i s a fixed
voltage value (0 volts for TTL integrated circuits) and the logic-1 signal can be
generated through an inverter whose input is 0.
• The four multiplexers are controlled by two selection inputs, S1 and S 0.
• The input carry Cin goes to the carry input of the FA in the least significant
position. The other carries are connected from one stage to the next.
Arithmetic Circuit Function Table
Logic Micro-operations
• Logic micro-operations specify binary operations for strings of bits stored in registers.
• These operations consider each bit of the register separately and treat them as binary
variables.
• For example, the exclusive-OR micro-operation with the contents of two registers R 1
and R2 is symbolized by the statement:
There are 16 different logic operations that can be performed with two binary variables.
Hardware Implementation
• It consists of four gates and a multiplexer. Each of the four logic operations is generated
through a gate that performs the required logic.
• The outputs of the gates are applied to the data inputs of the multiplexer.
• The two selection inputs S1 and S0 choose one of the data inputs of the multiplexer and
direct its value to the output.
Some Applications
From the truth table we note that the bits of A after the operation are obtained from the logic-
OR operation of bits in B and previous values of A . Therefore, the OR micro-operation can
be used to selectively set bits of a register.
2.selective-complement
3. selective-clear
• The selective-clear operation clears to 0 the bits in A
only where there are corresponding 1's in B. For
example:
• One can deduce that the Boolean operation
performed on the individual bits is AB ' . The
corresponding logic micro-operation is:
4. mask operation
• The mask operation is similar to the selective-clear
operation except that the bits of A are cleared only
where there are corresponding 0' s in B.
• The mask operation is an AND micro operation as
seen from the following numerical example:
5. clear operation
• The clear operation compares the words in A and B
and produces an all 0' s result if the two numbers are
equal.
• This operation is achieved by an exclusive-OR micro-
operation as shown by the following example:
6. insert operation
• The insert operation inserts a new value into a group of
bits. This is done by first masking the bits and then OR-ing
them with the required value.
• For example, suppose that an A register contains eight bits,
0110 1010. To replace the four leftmost bits by the value
1001 we first mask the four unwanted bits:
• are two micro-operations that specify a 1-bit shift to the left of the content of register R 1
and a 1-bit shift to the right of the content of register R2.
• The register symbol must be the same on both sides of the arrow.
• The bit transferred to the end position through the serial input is assumed to be 0 during a
logical shift.
Logical Shift Left
1 0 1 1 0 0 1
Serial i/p = 0
0 1 0 1 1 0 0
circular shift
• The circular shift (also known as a rotate operation) circulates the bits of the register
around the two ends without loss of information.
• This is accomplished by connecting the serial output of the shift register to its serial input.
• We will use the symbols cil and cir for the circular shift left and right, respectively
.
• An arithmetic shift is a micro-operation that shifts a signed binary number to the left or
right.
• An arithmetic shift-left multiplies a signed binary number by 2. An arithmetic shift-right
divides the number by 2.
• Arithmetic shifts must leave the sign bit unchanged because the sign of the number
remains the same when it is multiplied or divided by 2.
• The leftmost bit in a register holds the sign bit, and the remaining bits hold the number.
• The sign bit is 0 for positive and 1 for negative. Negative numbers are in 2's complement
form.
• The arithmetic shift-left inserts a 0 into R0 and shifts all other bits to the left. The
initial bit of R n-1 is lost and replaced by the bit from R n-2 •
• A sign reversal occurs if the bit in R n-1 changes in value after the shift.
• This happens if the multiplication by 2 causes an overflow. An overflow occurs after an
arithmetic shift left if initially, before the shift, R n-1 is not equal to R n- 2•
• An overflow flip-flop Vs can be used to detect an arithmetic shift-left overflow.
If Vs = 0, there is no overflow, but if Vs = I, there is an overflow and a sign reversal after the
shift. Vs must be transferred into the overflow flip-flop with the same clock pulse that shifts the
register.
Left Arithmetic Shift
1 0 1 1 0 0 1
Serial I/p=0
0 1 1 0 0 1 0
Sign bit
1 0 1 1 0 0 1
1 1 0 1 1 0 0
Hardware Implementation
• In a processor unit with many registers it is more efficient to implement the shift operation
with a combinational circuit.
• In this way the content of a register that has to be shifted is first placed onto a common
bus whose output is connected to the combinational shifter, and the shifted number is then
loaded back into the register.
• This requires only one clock pulse for loading the shifted value into the register.