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Formal Verification

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39 views

Formal Verification

Uploaded by

ankit
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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INTERVIEW PREPARATION

SV | UVM EXPERIENCE ROLE

Interview Preparation
Formal Verification Engineer
Basic to Advanced Q/A
INTERVIEW PREPARATION
SV | UVM EXPERIENCE ROLE

Question 1 :
Can you explain what formal verification is and its importance in the VLSI design
process?
Answer :
Formal verification uses mathematical techniques to prove the correctness of
hardware designs against specifications. It is essential because it provides
exhaustive proof, covering all input combinations and edge cases, which
simulation alone cannot achieve. This ensures designs are error-free, especially in
critical systems like automotive, aerospace, and medical applications.

Question 2 :
What are the differences between simulation-based verification and formal
verification?
Answer :
Simulation-Based Verification: Tests specific scenarios using stimulus-driven
methods. It is not exhaustive.
Formal Verification: Proves correctness for all scenarios by checking against
properties and constraints mathematically. It is exhaustive but
computationally expensive.
Both methods are complementary in ensuring robust design validation.

Question 3 :
What are the types of properties verified in formal verification?
Answer :
Safety Properties: Ensure something bad doesn’t happen (e.g., no two
masters access the bus simultaneously).
Liveness Properties: Ensure something good eventually happens (e.g., every
request gets a response).
INTERVIEW PREPARATION
SV | UVM EXPERIENCE ROLE

Functional Properties: Define how the design should behave under specific
conditions.

Question 4 :
What is the role of SVA (SystemVerilog Assertions) in formal verification?
Answer :
SVA defines properties in the design, such as temporal relationships between
signals. It is used for:
Specifying expected behavior.
Debugging violations.
Reusing properties across simulation and formal verification tools.

Question 5 :
How do you identify and resolve over-constraining or under-constraining issues in
formal verification?
Answer :
Over-Constraining: Leads to a false sense of correctness. Check constraints
for overly restrictive conditions that eliminate valid input scenarios.
Under-Constraining: Leads to false failures. Ensure all realistic operating
conditions are captured.
Tools like counterexample analysis and coverage metrics help in identifying
such issues.

Question 6 :
How do you handle “unreachable state” issues in formal tools?
Answer :
Analyze the counterexamples provided by the tool.
Debug and refine assumptions or constraints.
Use coverage tools to understand which parts of the design are unreachable.
INTERVIEW PREPARATION
SV | UVM EXPERIENCE ROLE

Question 7 :
How do you verify a complex bus protocol like AXI using formal meth
Answer :
Define properties such as valid handshakes, transaction ordering, and
response correctness using SVA.
Use abstraction techniques to simplify scenarios.
Debug failures by analyzing counterexamples and refining assertions.

Question 8 :
Describe a challenging formal verification problem you solved and how you
approached
Answer :
Example: Verifying deadlock-freedom in a network-on-chip.
Decomposed the design into smaller components.
Wrote liveness properties for individual blocks.
Used induction-based proof methods for scalability.
Optimized tool runtime with abstraction models.

Question 9 :
A property fails in formal verification. How would you debug and fix it?
Answer :
Analyze the counterexample to understand why the property failed.
Check the assumptions and constraints for errors or gaps.
Refactor the property or constraint if needed.
Validate fixes by rerunning the verification and reviewing coverage metrics.
INTERVIEW PREPARATION
SV | UVM EXPERIENCE ROLE

Question 10 :
Write an SVA property to verify that a signal req is always followed by ack within
3 clock cycles.
Answer :

Question 11 :
How would you check for mutual exclusivity between two signals signal_a and
signal_b?
Answer :

Question 12 :
Implement an assertion to verify a protocol requirement: If valid is high, then ready
must be high in the next cycle.
Answer :
INTERVIEW PREPARATION
SV | UVM EXPERIENCE ROLE

Question 13 :
Write an assertion to detect a deadlock where a req signal is asserted but a grant
signal is never received.
Answer :

Question 14 :
How would you create an abstract model for a FIFO to verify its functionality?
Answer :
INTERVIEW PREPARATION
SV | UVM EXPERIENCE ROLE

Question 15 :
How do you write assertions for equivalence checking between two designs?
Answer :
Compare outputs of RTL (golden) and synthesized design (implementation):

Question 16 :
Write an SVA to ensure no two masters in a bus protocol access the same slave at
the same time.
Answer :

Question 17 :
Write an SVA to ensure no two masters in a bus protocol access the same slave at
the same time.
Answer :
INTERVIEW PREPARATION
SV | UVM EXPERIENCE ROLE

Question 18 :
How do you verify that all states in a finite state machine (FSM) are reachable?
Answer :
Use a cover property for each state.

Question 19 :
Verify the AXI protocol property: AWVALID must remain high until AWREADY is
asserted.
Answer :

Question 20 :
Write a property to check that a burst transaction is completed before the next
begins in AXI.
Answer :

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