International Journal of Pure and Applied Mathematics

Volume 119 No. 16 2018, 4357-4363

ISSN: 1314-3395 (on-line version)
url: http://www.acadpubl.eu/hub/
Special Issue
http://www.acadpubl.eu/hub/

Design and Analysis of Low Power Braun Multiplier

Architecture
1
Prakash.S.P , 2 Valarmathi.R.S , 3 M.Abdhullah, 4 S.Kirubakaran
1
AP(Sr.G) Department of ECE Bannari Amman Inst. of Technology ,Sathyamangalam,
Tamilnadu, India.
2
Sr Professor & Dean Academics, Department of ECE Bannari Amman Inst. of Technology ,Sathyamangalam,
Tamilnadu, India.
3
AP(Sr.G), Department of ECE , Department of ECE Bannari Amman Inst. of Technology ,Sathyamangalam,
Tamilnadu, India.
4
AP(Sr.G), Department of ECE Bannari Amman Inst. of Technology ,Sathyamangalam,
Tamilnadu, India.
1
[email protected],2 [email protected],3 [email protected]
4
[email protected]

Abstract — In recent years, power dissipation is one of the low power electronics. High power systems often may
biggest challenges in VLS I design. Multipliers are the main lead to damage several circuit damages. Low power
sources of power dissipation in DS P blocks. Power
optimization has to be implemented on all components of
the processor. In this paper, the design and power leads to smaller power supplies and less expensive
comparison of the low power unsigned array multipliers batteries.
using different types of adder units are analyzed. The
fundamental units to design a multiplier are adders. The
proposed multiplier is designed by using different types of The mu lt iplier circu it is a core component of most of
full adder and half adder units. The design of full adder the present day digital signal proces sors. Therefore, the
and half adder for low power is obtained and the low demand for mu ltip lier-performance improvement is
power units are implemented on the proposed multiplier increasing. Multipliers are a major source of power
and the results are analyzed for better performance. The dissipation. Reducing the power d issipation of
designs are done using TANNER S EDIT tool and are
simulated using TS PICE. The experimental tanner S PICE
mu ltip liers is key to satisfying the overall power budget
results show that the transistor count and the power of various digital circuits and systems.
required are significantly reduced in the proposed design In this paper, power reduction fo r unsigned multip liers
over the existing design. is explained and power comparisons of BRAUN
mu ltip liers are obtained. For power reduction the AND
gates are replaced with NOR gates. The half adder units
Key terms: BRAUN multiplier, unsigned multiplication
are also modified in the proposed design for the
algorithm, full swing 16T full adder, S ERF full adder, 12T
XOR.
excellent reduction in both the power and transistor
count. This paper is organized as follows: In section 2
the unsigned mult iplication algorith m is given. Section 3
INT RODUCT ION deals with the existing/ conventional array mult iplier
architecture .In section 4 the designs of different adders
are discussed. Section 5 the proposed multiplier design
Very Large Scale Integrated (VLSI) circu it technology
is described. Section 6 experimental results and
is the rapid growing technology for a wide range of conclusion are discussed, which validate the proposed
innovative devices and systems that have changed the
method.
world today. In the past, the major concerns of the VLSI
designer were area, performance, cost and reliability. UNSIGNED M ULT IPLICATION A LGORITHM
Power was mostly of only secondary importance. Now
adays, however, this trend has changed a lot, power is
Ut ilizing AND gates and full adders, mu ltip lication can
given primary importance than area and speed. The be imp lemented on the processor in the same way as it is
explosive growth in laptop and portable systems and in
done by hand: mu ltip ly each digit o f the mult iplier by
cellular networks has intensified the research efforts in
the mu ltip licand, thereby generating part ial products and

n 1
X X i 2i
i 0

4357
International Journal of Pure and Applied Mathematics Special Issue

then sum up the respective partial products in order to

generate the final result. Assume that X and Y are t wo n-
bit unsigned numbers, where X is the mult iplicand and
Y is the multiplier. They can be expressed as follows:

(1)
n 1
Y Yj 2 j (2)
j 0

The product of X and Y is P and it can be written in

the following form:
n 1 n 1
P X iY j 2 ( i j)

i 0 j 0
(3)
Each of the partial product terms Pn = Xi Yj is called
the summand. All the partial products then get added up
to generate the final product [7].

1. EXIST ING A RCHIT ECTURE

Array mu lt ipliers are high speed parallel mu ltipliers.

Unsigned array mu ltip liers are also known as Braun
mu ltip liers or Carry Save Array Multipliers [7][8].Th is
mu ltip lier is restricted to performing mu ltiplication of
two unsigned numbers. It consists of an array of AND
gates and adders arranged in an iterat ive structure that
does not require logic registers. This is also known as
the non-additive mu ltiplier since it does not add an
additional operand to the result of the mu ltiplication.
Figure 1. Conventional unsigned array multiplier
Architecture of a n*n bit multip lier requires n(n-1) and
n 2 AND gates.
The half adders used in the existing mu ltiplier is the
28transistor conventional CMOS adder. The design of
Each of the Xi Yj product bits is generated in parallel
conventional XOR gate of 22T and the conventional
with the AND gates. Each partial product can be added half adder of 28T, that are used in the existing array
to the previous sum of partial products by using a row of multiplier are given in figure 2 and figure 3 respectively.
adders. There is no horizontal propagation of carry. The
INV AND
braun mu ltiplier perfo rms well for unsigned operands
that are less than 16 bits.The conventional unsigned
array multiplier architecture is given in figure 1. OR

INV
AND

Figure 2. XOR gate (22T )

4358
International Journal of Pure and Applied Mathematics Special Issue

XOR (22T) A Novel 14T full adder[5] is the next full adder us ed
for the analysis and is better than the conventional 14T
[7] in the figure 6.

AND

Figure 3. Conventional half adder(28T )

DESIGN OF FULL A DDERS

The existing and p roposed array mu lt iplier will be

designed and power analyzed for d ifferent full adders
like CM OS normal full adder, 16 t ransistor full adder, 14
Figure 6. New 14T full adder
transistor full adder and SERF 10 transistor full adder
and from the comparison the power optimized
Static energy recovery full adder [6] is the fourth one
multiplier will be found out.
which is having 10T and it is having low power than the
conventional 10T full adder[7] is shown in the figure 7.
Four d ifferent fu ll adders are used for analysis. The
first one is the normal CM OS fu ll adder[8] in figure 4
which is having 62 transistors.

HALF ADDER

OR

HALF ADDER

Figure 4. CMOS full adder (62 T )

Figure 7. SERF full adder
The second full adder is the 16T fu ll adder [4] which
is having full swing and is having low power PROPOSED A RCHIT ECTURE
consumption than the transmission function adder
[2][3] is shown in figure 5. The process of array mu lt iplication wh ich fo llows the
unsigned algorithm, is the AND operation of
mu ltip licand and mu ltip lier bits and its followed
INV
addition. The AND gates in the conventional mult iplier
INV are rep laced with NOR gates in the proposed mult iplier
[1], according to the DeMorgan’s Law:

A.B = (A’+B’)’ (4)

Fro m (4) its clear that the inputs have to be

INV complemented. AND gates have 6 transistors but NOR
INV gates have 4 transistors. For a 4*4 mult iplier 8 inverters
are in itially required, 16 AND gates are rep laced with 16
NOR gates, thus in total when co mpared to conventional
Figure 5. Full swing 16T full adder 16 transistors are saved in existing mult iplier. The
proposed design of unsigned array mu ltip lier is given in
figure 8.

4359
International Journal of Pure and Applied Mathematics Special Issue

Figure 9. 12T XOR

RESULT S A ND DISCUSSION

The designs are done in TANNER SEDIT 12.0 tool

and the simulat ions are done and the power results are
obtained in the TANNER TSPICE 12.0.The power
comparisons of different units in the existing design and
proposed designs are shown in figure 10 to figure 13 and
the mu ltip lier power co mparison is given in figure 14. A
table 1 showing transistor count is also obtained for
Figure 8. Proposed unsigned array multiplier
existing and proposed array multipliers.

The half adders used in the proposed design are with

12transistor XOR gate. In the proposed multip lier again
10 transistors are saved by this modification in one half Power Comparison
adder unit alone. The 22T XOR gate of the half adder of
the existing mu ltip lier is rep laced with 12T XOR gate in 0.3 0.2496
the half adder of the proposed multip lier. The 12T
power (mw)

0.25
XOR gate is g iven in figure9. Half adder in the 0.2
proposed design is with 18T and it is having good power 0.15
0.1 0.0731
reduction than 28T conventional half adder. The
proposed and existing array mu ltip liers are analy zed for 0.05
good power results with different full adder units. 0

INV INV AND NOR

Figure 10 . Power comparison of AND(6T ) gate and NOR(4T ) gate

4360
International Journal of Pure and Applied Mathematics Special Issue

Power Comparison 30
Power Comparison
1.041 26.54
1.2

22.84
power (mw)

1 25
0.8
0.6 0.4664
0.4 20
0.2

power (mw)
0

13.76

13.15

12.79

12.19
15

11.14

10.13
XOR-22T XOR-12T 10
Figure 11. Power comparison of 22T XOR and 12T XOR gates
5

Power Comparison 0
existingAM(with CMOS fa)
1.5 1.16 proposedAM (with CMOS fa)
power (mw)

existingAM(with 16t fa)

1 0.701 proposedAM (with 16t fa)
0.5 existing AM(with 14t fa)
proposedAM (with 14t fa)
0 existing AM (with SERF fa)
proposed AM (with SERF fa)
Figure 14. Power comparison of different unsigned array multipliers
Half adder(22TXOR) half adder(12TXOR) (AM).

Figure 12. Power comparison of 22T XOR half adder and 12T XOR
half adder
T ABLE 1
T RANSIST OR COUNT OF DIFFERENT ARRAY MULT IPLIERS

Power Comparison Array multiplier(AM) No.of transistor

count
4.5
3.94 Existing AM (with CMOS fa) 704
4 Proposed AM(with CMOS fa) 648
3.5 Existing AM (with 16T fa) 336
3 Proposed AM(with 16T fa) 280
power (mw)

2.5 Existing AM (with 14T fa) 320

2 Proposed AM(with 14T fa) 264

1.41
1.5 Existing AM (with SERF fa) 288

1 Proposed AM(with SERF fa) 232

0.5 0.338
0.129
0 CONCLUSION

The existing and proposed array multip liers are

CMOS full adder (62t) 16T full adder
designed using TANNER sedit tool and the power
results are analysed with different adder units using
Tspice. It is therefore found that the proposed array
14T full adder SERF 10T full adder
mu ltip liers have transistor count and power range less
than that of existing mu ltip liers. Proposed Multipliers
Figure 13. Power comparison of different full adders with the CMOS fu ll adder have 8% reduction in
transistor count and about 13.9% power reuction than
the existing mult iplier with CMOS fu ll adder.

4361
International Journal of Pure and Applied Mathematics Special Issue

Multipliers with 16T fu ll adder have 16% transistor

count reduction and 4.4% power reduction in the
proposed than the existing.Transistor count reduction
and power reduction are 17.5% and 4.6% respectively
for the proposed mult iplier with 14T full adder than the
existing multip lier with 14T full adder.Finally the
proposed mult ipliers with SERF have 19.4% reduction
in transistor count and 9% power reduction than the
existing multip lier.Therefore it is found that the
proposed multiplier with SERF have better results than
the other multipliers.

REFERENCES

[1] Ronak Bajaj, Saransh Chhabra, Sreehari Veeramachaneni and

M.B.Srinivas, ― A Novel Low Power Array Multiplier
Architecture,‖ ISCIT , pp. 119 -123, 2009.

[2] Nan Zhuang and Haomin Wu, ―A new design of the CMOS full
adder,‖ IEEE Journal of Solid State Circuits, Vol. 27, No.5,
pp.840-844, May 1992.

[3] Ahmed M . Shams , Magdy A . Bayoumi and T arek K .

Darwish , ―Performance Analysis of low – power 1-Bit CMOS
Full Adder Cells,‖ IEEE T ransactions on VLSI Systems,
vol.10 , No. 1 , pp. 20- 29, February ,2002.

[4] M.H. Ghadiry, M.Miryahyaei and M.Nadisnejani, ― A New Full

Swing Full Adder Based on a New Logic Approach,‖ World
Applied Sciences Journal 11 (7), pp. 808-812, 2010.

[5] E. Abu-Shama and M. Bayoumi, ― A New Cell for Low Power

Adders,‖ IEEE Int. Symp. on Circuits and Systems, pp.49-52.
[doi:10.1109/iscas. 1996. 541898], 1996.

[6] E.John, L.K. John and R. Shalem, ― A novel low power

energy recovery full adder cell, ‖ Proc. of GLSVLSI, pp.380-
383,1999.

[7] K.Roy and S.C. Prasad, Low Power CMOS VLSI Circuit Design,
Wiley, 2000.

[8] Neil Weste and Kamran Eshranghian, Principles of CMOS VLSI

Design, Addison Wiley, 2000.

4362
4363
4364