Unit 2: Introduction to VHDL

Digital Electronics

• Bibliography: “Digital Design: Principles and Practices”, J.F. Wakerly. Prentice‐Hall, 4th ed., Chap. 5
• “Sistemas Electrónicos Digitales”, E. Mandado. Marcombo, 10ª Ed., Cap. 5 y 7.
Rev. 2021‐09‐21

1
 Index
2.1. Hardware Description Languages (HDL)
2.1.1. Introduction to HDLs
2.1.2. Synthesis of HDLs
2.1.3. Characteristics of HDLs
2.2. Very‐high‐speed integrate circuit HDL (VHDL)
2.2.1. Top‐Down Design Methodology
Digital Electronics

2.2.2. VHDL Model

2.2.3. Entity Declaration
2.2.4. Identifiers
2.2.5. Objects and Data Types
2.2.6. Architecture Definition
2.2.6.1. Dataflow Model
2.2.6.2. Behavioral Model
2.2.6.3. Structure Model
2.2.8. Libraries
2.2.9. Packages
2.2.10. Test Bench
2.2.11. Attributes
2.2.12. Reserved Words

Topic 2: Introduction to VHDL 2

 2.1 HDLs
• The Hardware Description Languages (HDL) are an alternative to classical design
methodologies
• They allow to describe the behavior and the structure of the circuits
• The HDL are formal languages, and can be understood by designers
• They allow designers to work on higher levels of abstraction than the logical level
(algorithm, register transfer logic)
Digital Electronics

• Used for documentation, modeling, synthesis and simulation

HDL
Schematic
Capture

Topic 2: Introduction to VHDL 3

 2.1.1. Introduction to HDLs
Digital Electronics

Procedure to check the functionality of the

Simulation description

Procedure to convert one behavioral

Synthesis description from one level of abstraction to
another lower structural level

Topic 2: Introduction to VHDL 4

 2.1.2 HDL Synthesis
• The synthesis is the process of translating one behavioral description to a
logical description, for a target technology with specific restrictions.

RT Synthesis
Digital Electronics

VHDL
Code Optimized Circuit
XOR MUX
FF
AND NOT
Optimization
Generic Logical Model Mapped Logical Circuit

Restrictions
Manufacturer
Library TEC Technology Mapping Tmax

Topic 2: Introduction to VHDL 5

 2.1.3 Characteristics of HDLs
• Can describe
– the behavior (what does it do?)
• Describe the hardware to be
– the structure (which components it
– simulated has?)
– modeled
• Must known
– specified
–
Digital Electronics

the language elements

– documented
– the time treatment
– create the circuit
– the data types
– ...
– the control instructions
• It is not a programming – the execution
language
• Must have
– concurrent execution
– wide use (standard)
– signal modeling
– variety of tools
– libraries
• The most employed are Verilog and
– hierarchy
VHDL

Topic 2: Introduction to VHDL 6

 2.2. VHDL Language
• VHDL = VHSIC Hardware Description Language (ultimately Design
Language), where VHSIC stands for Very High Speed Integrated Circuit.
• Was a project of the Department of Defense (DoD) of the USA to have a
common documentation and design format in the VHSIC program.
Digital Electronics

• Between 1983 and 1984, Texas Instruments and Intermetrics developed the
first version, that was introduced to IEEE.
• On December 1984 it is accepted by the IEEE Standards Board, and its first
version was published in 1987 (VHDL‐87).
• In 1993 a second version was published, with some changes (VHDL‐93)
• In 2002 a third version was released (VHDL‐2002), a few years later VHDL‐
2008 and so forth.
• It is important to know with which version of the software tools are we
going to work. The language has not changed its basics since 1993, but
more resources have been added for experienced designers.

Topic 2: Introduction to VHDL 7

 2.2.1. Top‐Down Design Methodology

Specification
Specification
Document

System
Level
Digital Electronics

Simulation Architecture Design entity COMP is

.... Design
VHDL Description end COMP;

Descending
architecture
begin

Simulation Logical Design

Logic Gates
Schematics
Physical
Design
Verification Physical Design

Hardware

Topic 2: Introduction to VHDL 8

 2.2.2. VHDL Model (I)

Describes the interface with other circuits and the common

entity
characteristics of all possible variants of a component

Describes how the device operates, its functionality or its

Digital Electronics

architecture
internal structure. It is related with an entity

configuration Picks the components to be used from the design library

Optional

Contains a set of declarations of types and subprograms

package
common to different design units

Define the package body that have been declared in the

package body
associated package

Topic 2: Introduction to VHDL 9

 2.2.2. VHDL Model (II)

entity

M1
Digital Electronics

M3
architecture M2
A1 A2 A3

configuration
Optional

function SUM (A,B: bit) return bit

constant N : integer = 16;
package ...

function SUM (A,B: bit_vector) return bit_vector

begin
package body return CONV_BIT_VECTOR (A + B); ...

Topic 2: Introduction to VHDL 10

 2.2.3. Entity Definition (I)
• Describe the interface with the exterior, describes its inputs and outputs
• Entity declaration pattern:

Outputs
Inputs
entity <entity_name> is Entity
port (<port_name>: <mode> <type>;
Digital Electronics

….
);
end <entity_name>;

There are for modes

• in: input to the entity.
• out: output of the entity, can not be read from inside the entity.
• buffer: output of the entity, can be read from inside the entity.
• inout: input / output of the entity.

Topic 2: Introduction to VHDL 11

 2.2.3. Entity Definition (II)

• Example: entrada1
entrada2
Digital Electronics

salida
entrada3

Topic 2: Introduction to VHDL 12

 2.2.4. Identifiers
• Names or tags used to refer to constants, signals, entities and processes

• Contains letters, digits and underscores

• Can not be the reserved words!

Digital Electronics

• Examples and rules:

Incorrect Correct
The first character must be a letter 4Suma Suma4
The second character can not be an underscore S_4bits S4_bits
Two underscore together are not allowed Resta__4 Resta_4_bits
No other symbols are allowed Resta_4# Resta_4_num

Topic 2: Introduction to VHDL 13

 2.2.5. Objects and Data Types (I)
Objects Data Types

integer
Objects Types
Digital Electronics

boolean
signal Numerical
bit

Enumerated character, string

variable
std_logic

constant
Compound array

Topic 2: Introduction to VHDL 14

 2.2.5. Objects and Data Types (II)
• The input / output ports must be signals
signals • Are in concurrent or sequential circuits
• Visible to the whole architecture
signal S1: std_logic; • Information about what value and when they show this value
• Assigned with <= combination of symbols
Digital Electronics

• Exists only inside of processes and subprograms (sequential

environments)
variables
• Are visible only inside of the process or subprogram where it has
been declared
variable V1 : bit;
• Take the given value immediately
• Assigned with := combination of symbols

constants • Declared inside of concurrent or sequential environments

• Are visible only where declared
constant C1: integer :=100; • Take value immediately

Topic 2: Introduction to VHDL 15

 2.2.5. Objects and Data Types (III)
• Enumerated Type: defined in ascending order

type <name> is (<string1>, <string2>, ...);

• Examples:
Digital Electronics

type op_alu is (addition, subtraction, multiplication);

type std_logic is ( ʽUʼ, ʽXʼ, ʽ0ʼ, ʽ1ʼ, ʽZʼ, ʽWʼ, ʽLʼ, ʽHʼ, ʽ‐ʼ );

Topic 2: Introduction to VHDL 16

 2.2.5. Objects and Data Types (IV)
Multi Valued Logic (MVL)
• To make the simulation more efficient and to provide the highest level of information
about the behavior of a model it is necessary to increase possible values of the logic
states
• IEEE introduced in 1993 the package 1164. It defines 9 possible logical states
• STD_LOGIC: defined type in the package std_logic_1164 of the IEEE library
Digital Electronics

type std_logic is (
‘U’, -- uninitialized
‘X’, -- forcing unknown
‘0’, -- forcing zero
‘1’, -- forcing one
‘Z’, -- high impedance
‘W’, -- weak unknow
‘L’, -- weak zero
‘H’, -- weak one
‘-’ -- don´t care
);

Topic 2: Introduction to VHDL 17

 2.2.5. Objects and Data Types (V)
Concept of logic strength: capacity to deliver current from a node.
• 'U' ‐> nodes not initialized, that means that these nodes have not evolved since the beginning
of the simulation.
• '‐' ‐> This means that the synthesis tools can generate a ‘0’ or a ‘1’ indifferently, whatever is
simpler to implement

T1 p T2 p VC='0' →T2p OFF/ T2n OFF → VOUT = 'Z' high impedance

Digital Electronics

VC='1' →T2p ON / T2n ON =>

VIN='0'→T1p ON/ T1n OFF → VOUT = '1' strong
VIN=‘1'→T1p OFF/ T1n ON → VOUT = '0' strong
T1 n T2 n

'X' → colisión de '0' y '1'

if T is OFF → Vo1= 'H'

Analogously 'W' → collision of 'L' and 'H'
Vo2= 'L'

Topic 2: Introduction to VHDL 18

 2.2.5. Objects and Data Types (VI)
• Arrays: contain many elements of the same type

type name_array is array (start to end) of typo_elements;

type name_array is array (start downto end) of typo_elements;

• The std_logic_vector type is defined in the package

Digital Electronics

ieee.std_logic_1164.

type std_logic_vector is
array (integer range <>) of std_logic;

• Examples
signal datos1: std_logic_vector (7 downto 0);
signal datos2: std_logic_vector (0 to 15);

Topic 2: Introduction to VHDL 19

 2.2.5. Objects and Data Types (VII)

• The VHDL allows to define subtypes: a type with certain restriction

• It is usefull for some data with limited ranges

Digital Electronics

• Format:
subtype <name_subtype> is <type_base> range <limits_range>

• Example
subtype DIGITO is integer range 0 to 9;

Topic 2: Introduction to VHDL 20

 2.2.5. Objects and Data Types (VIII)
• Operators:

Relational Logical
= /= and or nand nor
< <= > => xor not
Digital Electronics

Arithmetics Others
** abs & (concatenation)
* / mod rem + ‐ (sign change)
+ ‐

SALIDA <= not ENTRADA1;

SAL_BUS(2 downto 0) <= ENTRADA1 & ENTRADA2 & ENTRADA3;

SAL_SUMA <= ENT_A(7 downto 0) + ENT_B(7 downto 0);

Topic 2: Introduction to VHDL 21

 2.2.6. Architecture Definitions (I)

• Defines the functionality of the entity.

• One architecture belongs to an specific entity, however one entity can have
many architectures associated.
Digital Electronics

• Declaration:

architecture <nombre_arquitectura> of <nombre_entidad> is

<declarations> ‐‐ declarations of signals, components, …
begin
<sentences> ‐‐ body of the architecture
end <nombre_arquitectura>;

Topic 2: Introduction to VHDL 22

 2.2.6. Architecture Definitions (II)

Architecture Entity
ESTRUCTURAL
Data Flow
Concurrent
Digital Electronics

Components
Assignations
Signals

PORTS
Styles of assignations

Variables
Behavioral
Sequence:
Process and
subprograms

Topic 2: Introduction to VHDL 23

 2.2.6. Architecture Definitions (III)

Concurrent Sequential

• The concurrent
• The sequential sentences
sentences are executed
are executed one after
Digital Electronics

simultaneously (in another (in order).

parallel).
... function F(X) is
begin
A <= B and C; if X = ‘0’ then
B <= ‘1’ when D = ‘0’ return ‘1’;
else ‘0’; else
D <= F(E) or G; Sequential code return ‘0’;
end if;
...
end function;
Concurrent code

• They allow to describe

• They describe the
algorithms easily (like a C
behavior of the
code)
hardware

Topic 2: Introduction to VHDL 24

 2.2.6.1. Data Flow Model (I)
• Describes the functionality of an entity without describing its structure‐
• The functionality is described by means of the information flow (Data Flow),
written in concurrent sentences.
• Example:
Digital Electronics

Topic 2: Introduction to VHDL 25

 2.2.6.1. Data Flow Model (II)

• The concurrent sentences are executed when an event occurs on the

rightmost part of the sentences (like in hardware)

• The order of the sentences has no effect on the simulation nor on the
Digital Electronics

synthesis of the designed circuit.

• Two sentences

• WITH ‐ SELECT

• WHEN ‐ ELSE

Topic 2: Introduction to VHDL 26

 2.2.6.1. Data Flow Model (III)

WITH – SELECT
All possible cases of the SEL signal
with <EXPRESION> select must be described
<S_D> <= <EXP1> when <CASO1>,
<EXP2> when <CASO2> | <CASO3>, <S_D> can be an output or one internal
<EXPn> when others; signal (neve an input)
Digital Electronics

• Example: XOR gate The outputs of the entity

can not be in <EXPRESION>
nor in <EXP1>... <EXPn>

Topic 2: Introduction to VHDL 27

 2.2.6.1. Data Flow Model (IV)

WHEN ‐ ELSE

<S_D> <= <EXP1> when <CONDICION1> else

<EXP2> when <CONDICION2> else <S_D> could be an aoutput or
<EXPn>; an internal signal (never an input)
Digital Electronics

The outputs of the entity can not

be used in <CONDICIONx> nor in
• Example <EXP1>... <EXPn>

entrada1

entrada2

salida
entrada3

Topic 2: Introduction to VHDL 28

 2.2.6.2. Behavioral Model (I)

• The functionality is expressed sequentially in a similar way to high‐level

programming languages (like C or Pascal.)

• The behavior description start with a process word.

Digital Electronics

• The sentences inside a process are executed sequentially.

• All the process of an architecture are executed concurrently.

• All process are repeated indefinitely, unless they are suspended.

Topic 2: Introduction to VHDL 29

 2.2.6.2. Behavioral Model (II)
• A process is a concurrent sentence that groups sequentially executed
sentences

<ETIQ>: process[(<LISTA_SEÑALES>)]
<DECLARACIONES>
Digital Electronics

begin
Sequential
<SENTENCIAS_SECUENCIALES> Sentences
end process <ETIQ>;
Signal assignation and
variable control flow
if...then...else...
case...is...when...=>...
while...loop...
Declarative part for...loop...
loop...
Execution control
declaration of variables,
constants sensitivity list
wait on...for...until...

Topic 2: Introduction to VHDL 30

 2.2.6.2. Behavioral Model (III)

• The processes have sentences that architecture COMP of UN_EJEMPLO is

begin
are executed sequentially P1: process(A, C)
begin
• The processes are executed in a if A = ‘1’ then
Digital Electronics

concurrent way among them B <= C;

else
B <= not C;
end if;
end process P1;
• A process starts to be run when an
event occurs in its sensitivity list or P2: process
begin
the conditions of the wait clause wait on A, C;
are valid if A = ‘1’ then
D <= C;
else
D <= not C;
• They must have a sensibility list or end if;
end process P2;
a wait clause end COMP;

Topic 2: Introduction to VHDL 31

 2.2.6.2. Behavioral Model (IV)

WAIT clause

P1: process P1: process P1: process

begin begin begin
wait on A, B; wait for 50 ns; wait until ST = ‘1’;
X <= A; X <= A; X <= A;
Y <= B; Y <= B; Y <= B;
Digital Electronics

end process P1; end process P1; end process P1;

Wait until A or B change Wait for 50 ns Wait until ST=‘1’

wait on <SIGNAL_LIST>; wait for <TIME>; wait until <COND>;

P1: process(A, B)
begin If the wait clause is used, all the control paths must
X <= A; have a wait
Y <= B;
end process P1;

Topic 2: Introduction to VHDL 32

 2.2.6.2. Behavioral Model (V)

IF sentence if <BOOLEAN_EXPR> then

<SEQUENTIAL_SENTENCES>
[elsif <BOOLEAN_EXPR> then
<SEQUENTIAL_SENTENCES>]
[else
<SEQUENTIAL_SENTENCES>]
• Example
Digital Electronics

end if;

entrada1

entrada2

salida
entrada3

Topic 2: Introduction to VHDL 33

 2.2.6.2. Behavioral Model (VI)
CASE sentence
case <EXPR> is
• Example when <OPCION_1> =>
<SEQUENTIAL_SENTENCES>
when <OPCION_2> =>
<SEQUENTIAL_SENTENCES>
Digital Electronics

...
when others =>
<SEQUENTIAL_SENTENCES>]
end case;

All posible conditions must be

described
entrada1

entrada2

salida
entrada3

Topic 2: Introduction to VHDL 34

 2.2.6.2. Behavioral Model (VII)

LOOP sentence
for <INDEX> in <RANGE> loop
• Example <SEQUENTIAL_SENTENCES>
end loop;
Digital Electronics

while <BOOLEAN_EXPR> loop

<SEQUENTIAL_SENTENCES>
end loop;

<ETIQ>: loop
<SEQUENTIAL_SENTENCES>
[exit <ETIQ> when <BOOLEAN_EXPR>]
[next <ETIQ> when <BOOLEAN_EXPR>]
end loop <ETIQ>;

Example of VHDL that can be simulated but not synthetized

Topic 2: Introduction to VHDL 35

 2.2.6.3. Structural Description (I)

• The structural description describes the exact interconnection between

signals and entities in a circuit.

• This description is closer to a traditional electronic circuit schematic.

Digital Electronics

• When a previously defined entity is going to be used, it must be

declared with the component sentence.

• When a component is used in an architecture it is called instantiation

(close to what is done in object oriented programming languages)

Topic 2: Introduction to VHDL 36

 2.2.6.3 Structural Description (II)

architecture <N_ARCH> of <N_ENT> is

declarative zone

component <N_COMP>
Digital Electronics

port(<N_PORT>: <MODE> <TYPE>); Components declarations

end component;

signal <N_SIGN> : <TYPE>; Signals declarations

begin
sentences zone

<C_REF>: <N_COMP>
Instantiation and
port map(<PORT_LIST>);
components
interconnections
end <N_ARCH>;

Topic 2: Introduction to VHDL 37

 2.2.6.3 Structural Description (III)
Digital Electronics • Example

Topic 2: Introduction to VHDL 38

 2.2.6.3 Structural Description (IV)
• It is possible to mix different description methods on a single design
• Example

entity sumador is
port(a,b,c: in bit; sum,cout:out bit);
end sumador;

architecture mix_descr of sumador is

Digital Electronics

component XOR2
port(p1,p2: in bit; pz:out bit);
end component;
signal s1: bit;
begin

x1: XOR2 port map (a,b,S1);

process(a,b,c)
variable t1,t2,t3: bit;
begin
t1:= a and b;
t2:= a and c;
t3:= b and c;
cout <= t1 or t2 or t3;
end process;

sum <= S1 xor c;

end mix_descr;

Topic 2: Introduction to VHDL 39

 2.2.8. Libraries

• The libraries have information about design units, including entities and
architectures.

• Fore each project, a library named work is created.

Digital Electronics

• To use already available common modules, general libraries are used. To

select a library, the sentence is

library IEEE;

library work; ‐‐ not needed, it is implicit included

Topic 2: Introduction to VHDL 40

 2.2.9. Packages (I)
• A package contains definitions of objects that can be used in many designs. For
instance, definition of components, functions, types and constants.

• To use a package
Digital Electronics

use ieee.std_logic_1164.all

library package use all

use ieee.std_logic_1164.std_ulogic

library package use std_ulogic type

Topic 2: Introduction to VHDL 41

 2.2.9. Packages (II)
• Standard package: contains types, functions and attributtes
commonly employed in digital designs
type boolean is (false, true);
type bit is (‘0’, ‘1’);
type character is ....;
Digital Electronics

type integer is range impl_defined;

type real is range impl_defined;
type time is range impl_defined
units
fs;
ps = ...
end units;
subtype natural is
integer range 0 to integer’high;
subtype positive is
integer range 1 to integer’high;
type string is
array (positive range<>) of character;
type bit_vector is
array (positive range<>) of bit;

Topic 2: Introduction to VHDL 42

 2.2.10. Test Bench
• A Test Bench defines the inputs signals that should be applied
to simulate a HDL design. The circuit or system to be simulated
is called Unit Under Test (UUT.)
Digital Electronics

TestBench Inputs UUT Outputs

Topic 2: Introduction to VHDL 43

 2.2.11. Attributes

attribute type description

‘event boolean returns true if there has been a change in the signal
‘range range gives the range of the vector
‘reverse_range range gives the inverted range
Digital Electronics

‘length integer gives the length of the vector

‘high Integer returns the upper limit value of the vector
‘low integer returns the lower limit value of the vector

signal A: bit_vector(7 downto 0);

...
A’range --> returns 7 downto 0
A’reverse_range --> returns 0 to 7
A’length --> returns 8
A’high --> returns 7
A’low --> returns 0

Topic 2: Introduction to VHDL 44

 2.2.12. Reserved Words

ABS ELSE NAND SELECT

ACCESS ELSIF NEW SEVERITY
S
AFTER E END
N
NEXT SIGNAL
ALIAS ENTITY NOR SUBTYPE
ALL EXIT NOT
A AND NULL
THEN
FILE TO
T
Digital Electronics

ARCHITECTURE F FOR OF TRANSPORT

ARRAY FUNCTION ON TYPE
ASSERT OPEN
ATTRIBUTE
GENERATE O OR
UNITS
G GENERIC
OTHERS
U UNTIL
BEGIN GUARDED USE
BLOCK OUT
VARIABLE
B BODY IF PACKAGE V
BUFFER IN
I INOUT P
PORT
WAIT
BUS PROCEDURE
IS WHEN
CASE PROCESS W WHILE
COMPONENT LABEL RANGE
C WITH
LIBRARY
CONFIGURATION L RECORD
CONSTANT LINKAGE REGISTER X XOR
LOOP R REM
DISCONNECT
D DOWNTO MAP REPORT
M MOD RETURN

Topic 2: Introduction to VHDL 45

 Final Remarks

• To design using VHDL it is more important do know all

the concepts related with digital electronics rather than
the VHDL language structures
Digital Electronics

• The design tools provide templates to work with the

most common circuits.

• Understand VHDL is fundamental to design complex

digital systems.

Topic 2: Introduction to VHDL 46