CHAPTER NO-1: 8086

Features of 8086:-
1) It has a 20-bit address bus, hence it can access maximum 220 bytes of main memory .i.e. 1MB. The addre
range of main memory is from 00000H to FFFFFH.
2) It has a 16-bit data bus and it has a 16-bit ALU, hence it is called as a 16-bit microprocessor.
3) It supports 2-stage pipelining.
The process of fetching next instruction while executing the current instruction is known as pipelining.
4) It supports Memory Banking i.e. In 8086, the main memory chip is divided in to two banks in order to fe
bits of data in one cycle. The banks are termed as Lower or Even bank and Higher or Odd bank.
5) It has two operating one modes.
i. Minimum mode.
ii. Maximum mode.
In Minimum mode, there is only one processor in the system. (Uniprocessor).
In Maximum mode, there are processors other than 8086 in the system such as 8087, etc. (Multiproces

6) It supports Memory Segmentation.

Segmentation means dividing the memory in to logical components.
In 8086, the memory is divided in to 4 segments and they are as follows:
i. Code Segment.
ii. Stack Segment.
iii. Data Segment.
iv. Extra Segment.
7) It has 256 interrupts.
8) It has a 16-bit IO address, hence it can access 216 IO ports ( ≈ 64k ports).

1
Microprocessor Notes
Memory Banking in 8086:-
In 8086, the size of data bus is 16 bits but we know one memory location can store only one byte of data (i.e. 8
So to make optimum use of data bus there is a need to fetch data from two memory locations but an address b
cannot carry two addresses (or address of two memory locations) simultaneously. So to solve above problem th
memory chip is divided in to two banks in such a way that the two consecutive memory locations lie in differen
banks. Hence each bank contains alternate locations. Therefore one bank contains all the even or lower addres
is called as Even bank or Lower bank and the other bank contains all the odd or higher addresses and is called a
bank or Higher bank.

Now by dividing the main memory chip in to two banks we can fetch 16-bit data in one cycle in following way:-

1. Address bus carries the address of the location present in Even or Lower bank from which data needs to
fetched.
2. Both the banks are enabled.
Even or Lower bank is enabled when A0 line is low i.e. A0 =0.
And Odd or Higher bank is enabled when 𝐵𝐻𝐸 line is low i.e. 𝐵𝐻𝐸 =0.
3. Since both the banks are enabled therefore one byte of data is fetched from the Even or Lower bank an
more byte of data is fetched from Odd or Higher bank in one cycle thereby 16-bit of data is fetched in o
cycle.

Using memory banking concept we can fetch byte 16-bit of data in one cycle thereby we are able to make
optimal use of 16-bit data bus.

Banks are enabled in following way:-

𝐵𝐻𝐸 A0 Operations
0 0 R/W 16-bit operation from both the banks.
1 0 R/W 8-bit operation from Lower or Even bank.
0 1 R/W 8-bit operation from Higher or Odd bank.
1 1 No operation.

2
Microprocessor Notes
 Diagram:-

1MB

512 KB
512 KB

Odd/Higher bank Even/Lower bank

3
Microprocessor Notes
Architecture of 8086:-

Architecture of 8086 is divided in to two parts and they are as follows:-

1) Bus interface unit (BIU).

2) Execution unit (EU).

Bus interface unit consists of the following components:-

4
Microprocessor Notes
 1) ES :-
It is a 16-bit segment register which stores the segment or base address of the extra segment.

2) CS :-
It is a 16-bit segment register which stores the segment or base address of the code segment.
3) DS :-
It is a 16-bit segment register which stores the segment or base address of the data segment.
4) SS :-
It is a 16-bit segment register which stores the segment or base address of the extra segment.
5) Instruction Pointer(IP) :-
It is a 16-bit offset register which stores an offset address of the next instruction which is to be fetched f
code segment.
6) Address Generation Circuit :-
In 8086 Address Generation Circuit calculates 20-bit physical address using offset and segment addresse
the following formula:-
Physical Address (PA) = Segment Address * 10H + Offset Address.
7) 6-Byte Pre-Fetch Queue :-
It is a 6-byte FIFO RAM used to implement pipelining.
The process of fetching the next instruction while executing the current instruction is known as pipelinin
BIU fetches the next six instruction bytes from the code segment and stores in the queue.
Execution Unit removes the instruction bytes from the queue and executes them.
Since the size of data bus in 8086 is 16-bit bus therefore queue is refilled when atleast two bytes of the
are empty.
Pipelining increases the efficiency of the microprocessor.
Pipelining fails when a branch occurs, as the pre-fetched instructions are no longer useful.
Hence as soon as microprocessor detects a branch instruction.It clears or discards the instructions prese
stored in the queue and new instructions are fetched from the new location and stored in the queue an
pipelining continues.

Execution Unit consists of the following components:-

1) General Purpose Registers :-

Those registers which are available to the programmers for their own use are termed as general pur
registers.
In 8086 there are 4 16-bit general purpose registers and they are AX, BX, CX and DX.
These 4 16-bit general purpose registers can also be operated as 8 8-bit general purpose registers an
are AH,AL,BH,BL,CH,CL,DH and DL.
2) Stack Pointer(SP) :-
It is a 16-bit special purpose register which is used to store the offset address of the stack top symbo

3) Base Pointer(BP) :-

5
Microprocessor Notes
 It is a 16-bit special purpose register which is used to store the offset address of any random location
stack segment.
4) Source Index(SI) :-
It is a 16-bit special purpose register which is used to store the offset address of a location in a data
segment.
5) Destination Index(DI) :-
It is a 16-bit special purpose register which is used to store the offset address of a location in an extr
segment.
6) ALU :-
In 8086 there is a 16-bit ALU which is used to perform arithmetic and logic operations.
7) Operand Register :-
It is 16-bit special purpose register which is used to store the data temporarily.
8) Control System :-
Inside control system there are instruction register and instruction decoder.
EU fetches the instruction from the queue and stores in the instruction register then the instruction
decoder decodes the instruction and sends the information to the control circuit for execution.
9) Flag Register :-
8086 has a 16-bit flag register.
It has 6 status flags and 3 control flags.
Status flags are those flags which are affected or updated due to ALU operations are known as Statu
Control flags are those flags which are used by the programmer to control certain operations.

Diagram :-

Status Flags :-

1) Carry Flag(CY) :-
It is set whenever there is a carry generated out of the MSB of the result.
2) Parity Flag(PF) :-
It is set when there is even parity (.i.e. even number of one’s) in the result.

3) Auxiliary Carry Flag(AC) :-

It is set whenever there is a carry generation from lower nibble to higher nibble.
4) Zero Flag(ZF) :-
6
Microprocessor Notes
 It is set whenever the result of an operation is equal to zero.
5) Sign Flag(SF) :-
It is set whenever the MSB of a result is 1.
6) Over Flow Flag(OF) :-
It is set whenever overflow is occurred (i.e. if result of a signed operation is large enough to fit in the
number of bits available to represent it then this situation is termed as an overflow).

Control Flags :-

1) Direction Flag(DF) :-
When this flag is set (i.e. DF=1) the microprocessor enters the auto-decrement mode.
2) Interrupt Enable Flag(IF) :-
When this flag is set (i.e. IF=1) the masked interrupts are enabled.
3) Trap Flag(TF) :-
When this flag is set (i.e. TF=1) the microprocessor enters the single stepping mode.

7
Microprocessor Notes
 MEMORY SEGMENTATION IN 8086:-
Diagram:-

Memory segmentation refers to dividing the main memory in to logical components.

8086 has a 20-bit address bus therefore it can access maximum 220 bytes of main memory i.e. 1MB.
In 8086 we divide the main memory in to four components i.e. segments and they are as follows:-
1) Code Segment.
2) Stack Segment.
8
Microprocessor Notes
 3) Data Segment.
4) Extra Segment.
In 8086 the maximum size of a segment can be 64KB and minimum size of a segment can be 16 bytes.
In 8086 a programmer can define multiple segments of a particular type but it can access maximum 4 segment
time.
In 8086 there are 4 16-bit registers such as CS,SS,DS and ES to hold the base address of the segments and it also
16-bit offset registers to hold the offset address for each of the segments.

Code Segment :-
This segment is used to store programs and instructions.
CS is a 16-bit segment register which stores the Segment or base address for the code segment.
IP is a 16-bit offset register which stores the offset address of the next instruction which is to be fetched from th
code segment.

Stack Segment :-
This segment is used to store the data in a particular manner i.e. in LIFO manner.
SS is a 16-bit segment register which stores the segment or base address for the stack segment.
SP is a 16-bit offset register which stores the offset address of the stack top symbol.
BP is a 16-bit offset register which stores the offset address of any random location in stack segment.

Data Segment :-
This segment is used to store the data.
Ds is a 16-bit segment register which stores the segment or base address for the data segment.
SI(Source Index) is a 16-bit offset register which stores the offset address of a location in the data segment.

Extra Segment :-
This segment is used store the data.
ES is a 16-bit segment register which stores the segment or base address for the extra segment.
DI(Destination Index) is a 16-bit offset register which stores the offset address of a location in the extra segmen

Address Calculation:-
8086 calculates 20-bit physical address using segment address and offset address using the following formula:-
Physical Address = Segment Address * 10H + Offset Address.

Advantages of Segmentation :-
Using segmentation we can access 1MB of main memory using 16-bit address.

Disadvantages of Segmentation :-
Due to segmentation, at a time we can access only 4 * 64KB of main memory i.e. 256KB instead of 1MB.

9
Microprocessor Notes
Pin Diagram of 8086:-

CLK:-
10
Microprocessor Notes
In 8086 clock is provided to microprocessor by 8284 clock generator.
8086 has a 33% duty cycle so to provide 6MHZ clock we will need to connect 18MHZ external clock frequency.
RESET:-
In 8086 the microprocessor is reset or formatted through reset pin.
8086 is reset by connecting an external 8284 clock generator.
When microprocessor is reset, it clears the flag register, the instruction queue, registers such as DS,ES,SS and IP
sets the bits of CS register.
Therefore the reset vector address of 8086 is FFFF0H (i.e. after microprocessor is reset CS= FFFFH and IP= 0000H
therefore Physical or reset address = CS*10H+offset address i.e. FFFFH*10H+0000H=FFFF0H).
READY:-
This pin is used to synchronize the microprocessor with the slower peripheral devices.
Devices inform the microprocessor whether they are ready or not through this pin.
The microprocessor checks this pin during T3 state of machine cycle and if suppose a device is not ready it send
this pin thereby indicating to microprocessor that it is not ready.
Then the microprocessors insert wait states between T3 and T4 states and will come out of the wait state only w
the device is ready for further computation I.e. when it sees 1 on the ready pin.
̅̅̅̅̅̅̅
𝐓𝐄𝐒𝐓 :-
This pin is dedicated or reserved for 8087 co-processor.
The microprocessor checks this pin only when it encounters wait instruction.
If the 8087 co-processor is busy it makes this pin high indicating to microprocessor that it is busy.
Then microprocessor enters the wait state and come out of the wait state only after this pin is made low by the
co-processor i.e. when 8087 is free or ready for further computations.

̅̅̅̅̅ :-
𝑴𝑵/𝑴𝑿

This pin is a multiplexed pin and it is used to indicate the operating mode in which the microprocessor is operat
working in (i.e. minimum mode or maximum mode).
If this pin is high then the microprocessor is operating in minimum mode.
If this pin is low then the microprocessor is operating in maximum mode.

NMI:-

NMI is a non-maskable, edge triggered, high priority interrupt pin.

On receiving an interrupt on NMI line, the microprocessor executes INT2 i.e. control is shifted to location 2*4=0
in the IVT, to get the value of CS and IP register to locate the ISR and service or execute it.

INTR:-

This is a maskable, level triggered, low priority interrupt pin.

On receiving an interrupt on INTR line, the microprocessor issues 2 ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 Pulses.

11
Microprocessor Notes
 ̅̅̅̅̅̅̅ Pulse, PIC calculates vector number N and on the second 𝐼𝑁𝑇𝐴
On the first 𝐼𝑁𝑇𝐴 ̅̅̅̅̅̅̅ Pulse, PIC sends the vector nu
N to the microprocessor through the data bus.
Now the microprocessor will multiply N*4 and go to the IVT to obtain the ISR address (I.e. CS & IP).
RD:-
When this pin is low it indicates the microprocessor is performing read operation either from memory or IO.
VCC and GND:-
These pins are used to provide power supply to the microprocessor.
AD15-AD0:-
In 8086 there is a multiplexed address and data bus.
When ALE pin is high it indicates that the multiplexed bus contains address in it and when the ALE pin is low it
indicates that the multiplexed bus contains data in it.
A16/S3-A19/S6:-
A16-A19 lines carries the address during T1 of every machine cycle and from T2 onwards status signals S3-S6 ar
active.
S3 and S4 signals are used to indicate the memory segment which is currently used.
S5 gives the status of the Interrupt Enable Flag.
S6 goes low when 8086 controls the System bus.
S3 S4 Segment Selected
0 0 Extra segment
0 1 Stack segment
1 0 Code/No segment
1 1 Data segment

̅̅̅̅̅̅̅/𝑺𝟕 :-
𝑩𝑯𝑬
̅̅̅̅̅̅ during the T1 machine cycle.
It carries 𝐵𝐻𝐸
̅̅̅̅̅̅
𝐵𝐻𝐸 line is used to enable the higher bank.
From T2 machine cycle onwards it carries S7 signal which is reserved for further development.

MIN/MAX MODE SIGNALS:-

̅̅̅̅̅̅̅̅̅̅̅̅̅:-
HOLD….𝑹𝑸𝟎/𝑮𝑻𝟎
In minimum mode this line carries Hold signal.
Hold signal is used to perform direct memory access(DMA).
In 8086 DMAC issues the Hold signal to request the microprocessor to become the bus master of the System bu
In maximum mode this line carries ̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑅𝑄0/𝐺𝑇0 signal.
The external bus master sends an active low pulse to the microprocessor to request for the access of System bu
In response 8086 completes the current bus cycle and releases the System bus and sends an active low grant pu
the same line to the external bus controller.
8086 gets back the System bus only after external bus master sends an active low release pulse on the same lin
̅̅̅̅̅̅̅̅̅̅̅̅̅ :-
HLDA….𝑹𝑸𝟏/𝑮𝑻𝟏
In minimum mode this line carriers HLDA signal.

12
Microprocessor Notes
This signal is issued by the microprocessor in response to DMAC’S HOLD signal i.e. when the microprocessor is a
to releases the System bus it acknowledges the Dmac with the help of this signal.
In maximum mode this line carriers ̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑅𝑄1/𝐺𝑇1.
̅̅̅̅̅ ̅̅̅̅̅̅̅̅
𝑾𝑹 … . 𝑳𝑶𝑪𝑲 :-
In minimum mode this line carriers 𝑊𝑅̅̅̅̅̅ Signal.
̅̅̅̅̅
When 𝑊𝑅 signal is low it indicates that the microprocessor is performing a write operation.
In maximum mode this line functions as ̅̅̅̅̅̅̅̅
𝐿𝑂𝐶𝐾 output line.
When this signal is low the external bus master cannot take the control of the System bus.
This signal is activated when the microprocessor executes an instruction with Lock prefix.
𝑫𝑬𝑵 … ̅̅̅̅
̅̅̅̅̅̅̅ 𝑺𝟎 :-
In minimum mode this line carriers ̅̅̅̅̅̅
𝐷𝐸𝑁 signal.
When this signal is low the data trans-receivers are enabled.
In maximum mode this line carriers ̅̅̅𝑆0.
̅ ̅̅̅̅
DT/𝑹 … . 𝑺𝟏 :-
In minimum mode this line carriers 𝐷𝑇/𝑅̅ signal.
When this signal is high the data is being transmitted and when this is low the data is being received.
In maximum mode this line carriers ̅̅̅𝑆1 signal.

̅̅̅̅̅̅ 𝐷𝑇/𝑅̅ Action

𝐷𝐸𝑁
1 X Transreceiver is disabled
0 0 Receives data
0 1 Transmits data
̅̅̅̅ ̅̅̅̅
𝑴/𝑰𝑶 …𝑺𝟐 :-
In minimum mode this line carriers 𝑀/𝐼𝑂 ̅̅̅ signal.
When this signal is high it indicates a memory operation is being performed and when this signal is low it indica
IO operation is being performed.
In maximum mode this line carriers 𝑆2 ̅̅̅ signal.

̅̅̅
𝑆0 ̅̅̅
𝑆1 ̅̅̅
𝑆2 Machine Cycle
0 0 0 INTA Cycle
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Inactive

̅̅̅ 𝑅𝐷
𝑀/𝐼𝑂 ̅̅̅̅ 𝑊𝑅
̅̅̅̅̅ Operations

13
Microprocessor Notes
 0 0 1 I/O Read
0 1 0 I/0 Write
1 0 1 Memory Read
1 1 0 Memory Write

ALE…𝑸𝑺𝟎̅̅̅̅̅̅ :-
In minimum mode this line carriers ALE signal.
When ALE signal is high then it is concluded that the multiplexed bus carriers the address in it and when ALE sig
low then it is concluded that the multiplexed bus carriers data in it.
In maximum mode this line carriers ̅̅̅̅̅ 𝑄𝑆0 signal.
̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅
𝑰𝑵𝑻𝑨 … 𝑸𝑺𝟏 :-
In minimum mode this line carriers ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 signal.
̅̅̅̅̅̅̅ signal, PIC calculates the vector number N.
On first pulse of 𝐼𝑁𝑇𝐴
On second pulse of ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 signal, PIC sends the vector number N to the microprocessor through the data bus.
In maximum mode this line carriers ̅̅̅̅̅ 𝑄𝑆1 signal.

̅̅̅̅̅ ̅̅̅̅̅
𝑄𝑆0 𝑄𝑆1 Queue Operation
0 0 NOP
0 1 Opcode fetched from the queue
1 0 Queue is cleared
1 1 Fetch remaining bytes from the queue

14
Microprocessor Notes
Interrupts in 8086:-

 Interrupt can be described as a special condition that arises during the execution of the program.
 There are two types of interrupts and they are maskable interrupts and non-maskable interrupts.
 In 8086 there are total 256 interrupts.
 In 8086 interrupts can be generated in three ways and they are as follows:-
1. Internally generated interrupts:-
In this type, the microprocessor is interrupted due to some special conditions that arises during
execution of certain instructions in the program.
Eg. An error in division automatically causes the INT 0 interrupt.

2. Software Interrupts:-
In this type an interrupt is invoked by writing a software instruction INT n where “n” can be any
from 0 to 255.
Eg. INT 03H is a software interrupt for breakpoint.

3. Hardware Interrupts:-
In this type, the interrupts occurs as a signal on the hardware pins of the microprocessor.
In 8086 there two hardware pins and they are NMI and INTR.

 The microprocessor services an interrupt by executing a subroutine called as ISR (Interrupt Service Rou
 The address of the ISR is stored in a table called as IVT (Interrupt Vector Table)

Interrupt Vector Table (IVT):-

 An IVT contains the ISR addresses for the 256 interrupts.
 Each ISR address is stored as CS and IP.
 Therefore to store each ISR’s address 4 bytes are required ( 2 bytes to store CS and 2 bytes to store IP
 Therefore in 8086 the size of IVT is 1KB ( because to store each ISR address it requires 4 bytes and the
such 256 interrupts in 8086 i.e. 4 * 256 = 1KB).

15
Microprocessor Notes
  The first 1KB of the memory is reserved for the IVT (i.e. addresses from 00000H to 003FFH are reserv
IVT).
 Whenever an interrupt INT N occurs, the microprocessor performs N * 4 to get the address of the ISR
values of IP and CS) from the IVT and hence executes the ISR.

Interrupt Vector Table

Interrupt Vector Table can be classified mainly in to three parts and they are as follows:-
1) Dedicated Interrupts:-
In 8086, Dedicated Interrupts are further classified in to five and they are as follows:-
I. INT 0 (Divide Error):-
This interrupt occurs whenever there is a division error i.e. when the result of a division is too lar
be stored.
This condition normally occurs whenever the dividend is large and divisor is comparatively too sm
it is zero.
Its ISR address is stored at location 0 * 4=00000H in the IVT.
16
Microprocessor Notes
 II. INT 1 (Single Step):-
Whenever the trap flag is set (i.e. TF=1), the microprocessor enters in single stepping mode i.e. it
after executing every instruction.
Its ISR address is stored at location 1 *=00004H in the IVT.
Single stepping is used in debugging and its ISR displays the contents of all the registers.

III. INT 2 (NMI):-

Whenever an interrupt occurs on the NMI line, the microprocessor goes to fetch the ISR address
is stored at location 2 * 4=00008H in the IVT and executes the ISR.

iv. INT 3 (Breakpoint):-

This interrupt is used to create Breakpoints in the program.
It can be done by simply writing INT 03H and INT instruction.
Breakpoints are generally used in large programs where using single stepping is inefficient.
Its ISR displays the contents of all the registers.
Its ISR address is stored at a location 3 * 4=0000CH in the IVT.

v. INT 4 ( Overflow Interrupt):-

Whenever the overflow flag is set (i.e. OF=1), the microprocessor executes INTO instruction.
It is used to detect overflow error in signed arithmetic operations.
Its ISR address is stored at location 4 *4 =00010H in the IVT.

2) Reserved Interrupts:-
Interrupts INT 5 to INT 31 are reserved in 8086 for the further development and these interrupts are no
available to the user.

3) User Defined Interrupts:-

Interrupts INT 32 to INT 255 are user defined, software interrupts.
The ISRs for these interrupts are written by the users to service the user defined conditions.
These interrupts are invoked by writing the instruction INT N.
To execute the ISR of the user defined interrupts, the microprocessor fetches the ISR address which is st
the location N *4 in the IVT.

17
Microprocessor Notes
ADDRESSING MODES OF 8086:-

In 8086 addressing modes is mainly classified in to five types and they are as follows:-
1. Immediate Addressing Mode:-
In this type of an addressing mode operands are directly specified in the instruction itself.
In this type operands can be easily identified.
In this type the length of the instructions are longer.
Eg :- 1) MOV BL, 23H.
2) MOV CX, 2332H.

2. Register Addressing Mode :-

In this type of an addressing mode the operands are specified using registers.
In this type operands cannot be easily indentified.
In this type the length of the instructions are shorter as compared to immediate addressing mod
Eg: 1) MOV BL,CL.
2) MOV BX,CX.

3. Direct Addressing Mode:-

In this type of an addressing mode the address of the operand is directly specified in the instruc
itself.
Here only offset address is specified, the segment being indicated by the instruction.
Eg: 1) MOV BX, [1234H].

4. Indirect Addressing Mode:-

i. Register Indirect Addressing Mode:-
In this type of an addressing mode the addresses are specified using registers.
In this type any of the two base registers BP,BX or any of the two index registers SI,DI to
provide the offset address for the data byte.
BX indicates Data Segment and BP indicates stack segment.
Eg: 1)MOV DL,[BX].
2)MOV [BP], DL.

18
Microprocessor Notes
 ii. Register Relative Addressing Mode:-
In this type of an addressing mode the address of the operands are specified using one o
base registers and a 8-bit or a 16-bit displacement.
Eg. 1)MOV DL,[BX+8].
2)MOV 12H[BP], CL.

iii. Base Indexed Addressing Mode:-

In this type of an addressing mode the address of the operand is specified using a base re
and an index register.
Eg. 1)MOV DL,[BX+SI].
2)MOV [BP+DI], DL.

iv. Base Relative Plus Index Addressing Mode:-

In this type of an addressing mode the address of the operand is specified using a base re
and an index register and a 8-bit or a 16-bit displacement.
Eg.1)MOV DL,[BX+SI+8].
2)MOV [BP+SI+12],DL.

5. Implied Addressing Mode:-

In this type of an addressing mode the address of the operands are already implied i.e. there is n
need to specify the operands.
Eg. 1)CMC.
2)STD.

19
Microprocessor Notes
8282-8 bit (octal) latch:-

1. In 8086, the address bus is multiplexed with the data bus and the status signals.
2. When ALE is high it indicates the multiplexed bus contains the address.
3. 8282 is used to latch the address from the multiplexed bus.
4. Therefore ALE signal is connected to the STB(strobe) of 8282.
5. When STB signal of 8282 is high, the input is latched and transferred to the output. Hence addre
latched.

20
Microprocessor Notes
 6. When STB signal of 8282 is low, the input is discarded so the data is not latched and the previou
latched address remains at the output.
7. The size of an address bus in 8086 is 20 bits and ̅̅̅̅̅̅
𝐵𝐻𝐸 signal is latched, so in all 21 bits are latche
8282 is a 8 bit octal latch so 3 latches are required.

8286- 8 bit Data Trans-receiver:-

1. 8286 is a 8-bit data trans receiver.

21
Microprocessor Notes
 2. It allows 8086 to either transmit the data or to receive the data through it (i.e. it acts as a bi-directi
buffer).
3. In 8086 the size of data bus is 16- bits, hence 2 8-bit trans receivers are required.
4. In minimum mode 𝑂𝐸 ̅̅̅̅ of 8286 is connected with 𝐷𝐸𝑁
̅̅̅̅̅̅ of 8086 and in maximum mode 𝑂𝐸 ̅̅̅̅ of 8286
connected with DEN of 8288.
5. T of 8286 is connected with 𝐷𝑇/𝑅̅ of 8086.
If T=1 then data is transmitted.
If T=0 then data is being received.
6. 8286 is enabled when ̅̅̅̅ 𝑂𝐸 is low.
7. 8286’s main function is to prevent the address and allow the data to be transferred on the data bu
8. During the 1st T-state the bus contains address I.e. bus does not contains data, therefore 𝐷𝐸𝑁 ̅̅̅̅̅̅ of 80
̅̅̅̅
high hence the 𝑂𝐸 of 8286 is high therefore the trans receiver is disabled. Thereafter when bus con
𝐷𝐸𝑁 of 8086 is low hence the ̅̅̅̅
data then ̅̅̅̅̅̅ 𝑂𝐸 of 8286 is low and the trans receiver is enabled and th
only allows data to flow.

8284 – Clock Generator:-

BLOCK DIAGRAM:-

22
Microprocessor Notes
8284 interfaced with 8086:-

1. 8284 is a clock generator and it provides clock to 8086.

2. Besides providing clock it also synchronizes Ready and Reset signal where Ready signal indicates that
interface is ready for data and Reset signal is used to initialize the system.
3. 8086 has a 33% duty cycle i.e. output clock frequency=1/3rd of the input clock frequency.
4. In two ways frequency can be provided to 8284 and they are as follows:-
i. Through X1,X2.
An oscillator can be connected across X1,X2 to provide clock signal at constant frequency.
ii. Through EFI pin.
A pulse generator circuit can be connected to EFI pin to provide an external frequency signal.
5. Clock selection is done using 𝐹/𝐶 pin, if 𝐹/𝐶 = 1 then input clock is provided through EFI pin and if 𝐹
then input clock is provided through X1,X2 pins.

23
Microprocessor Notes
8086 Minimum Mode:-

24
Microprocessor Notes
 1) When 8086 is operating in minimum mode it indicates that there is only one processor (8086) in the sys
it is an uniprocessor system.
2) When 𝑀𝑁/𝑀𝑋 ̅̅̅̅̅=1, then 8086 operates in minimum mode.
3) In minimum mode, 8284 clock generator is connected to the microprocessor to provide CLK, RESET and
Signals.
4) In minimum mode, 8282 8-bit latch is connected to the microprocessor to latch the address from the
multiplexed bus.
5) In 8086, the size of address bus is 20-bit therefore three such 8-bit latches are required.
6) The ALE of 8086 is connected to the STB of 8282.
7) In minimum mode, the microprocessor either transmits or receives data through 8-bit trans-receiver.
8) In 8086, the size of data bus is 16-bit therefore such two trans-receivers are required.
9) 𝐷𝑇/𝑅̅ pin of 8086 is connected to T pin of 8286 and 𝐷𝐸𝑁 ̅̅̅̅ of 8286.
̅̅̅̅̅̅ pin of 8086 is connected to 𝑂𝐸

̅̅̅̅̅̅
𝐷𝐸𝑁 𝐷𝑇/𝑅̅ ACTIONS
1 X Trans-receiver is disabled.
0 0 Receive data.
25
Microprocessor Notes
 0 1 Transmit data.

̅̅̅, ̅̅̅̅
10) M/IO 𝑅𝐷, ̅̅̅̅̅
𝑊𝑅 signals are decoded using 3:8 decoder like IC 74138.
11) In minimum mode, HOLD and HLDA signals are used to perform direct memory access.
12) when microprocessor is interrupted on the INTR line, it issues ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 signal.

TIMING DIAGRAMS:-
26
Microprocessor Notes
 27
Microprocessor Notes
 8086 Maximum Mode:-

1) In Maximum Mode, there are more than one processors present in the system .i.e. other co-process
connected to the 8086 microprocessor.
2) When 𝑀𝑁/𝑀𝑋 ̅̅̅̅̅ pin of 8086 =0, than the 8086 microprocessor enters in the maximum mode.
3) In maximum mode, the clock generator 8284 is connected to the microprocessor to provide CLK, REA
and RESET signals to the 8086 microprocessor.
4) In maximum mode, the address is latched from the address bus using the 8282 8-bit latch.
5) ALE is connected to the STB of 8282 and this ALE is provided by the 8288 bus controller.
6) Since the size of address bus of 8086 is of 20 bits and 8282 is a 8-bit latch, therefore three such latch
required.
7) In maximum mode, the data is transferred or received through the multiplexed bus using 8286 8-bit
receiver.
8) DT/𝑅̅ is connected to the T pin of 8286 and this DT/𝑅̅ is provided by 8288 bus controller.
28
Microprocessor Notes
 ̅̅̅̅ pin of 8286 and this DEN is provided by 8288 bus controller.
9) DEN is connected to the 𝑂𝐸

DEN 𝐷𝑇/𝑅̅ ACTIONS

0 X Trans-receiver is disabled.
1 0 Receive data.
1 1 Transmit data.

10) Size of the data bus in 8086 is 16-bits and 8286 is a 8 bit trans-receiver, therefore such two trans-rec
are required.
11) 8288 decodes ̅̅̅ ̅̅̅,𝑆0
𝑆2,𝑆1 ̅̅̅ signals to generate the control signals for all the operations as follows:-
̅̅̅ 𝑆1
𝑆2 ̅̅̅ 𝑆0
̅̅̅ Processor State 8288 Active Output
0 0 0 Interrupt Acknowledge ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴
0 0 1 Read I/O port ̅̅̅̅̅̅̅
𝐼𝑂𝑅𝐶
0 1 0 Write I/O port ̅̅̅̅̅̅̅̅̅
𝐼𝑂𝑊𝐶 𝑎𝑛𝑑 𝐴𝐼𝑂𝑊𝐶 ̅̅̅̅̅̅̅̅̅̅
0 1 1 Halt None
1 0 0 Instruction Fetch ̅̅̅̅̅̅̅̅̅
𝑀𝑅𝐷𝐶
1 0 1 Memory Read ̅̅̅̅̅̅̅̅̅
𝑀𝑅𝐷𝐶
1 1 0 Memory Write 𝑀𝑊𝑇𝐶 𝑎𝑛𝑑 ̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅ 𝐴𝑀𝑊𝑇𝐶
1 1 1 Inactive None

̅̅̅̅ /𝐺𝑇
12) Bus request is done using 𝑅𝑄 ̅̅̅̅ lines interfaced with 8086.
RQ0/GT0 has higher priority than RQ1/GT1.
13) ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 is given by 8288 Bus controller in response to an interrupt on the INTR line of 8086.

29
Microprocessor Notes
 TIMING DIAGRAMS:-

30
Microprocessor Notes
 Instruction Set of 8086:-

31
Microprocessor Notes
Data Transfer Instructions:

1. MOV Destination , Source

Moves a byte/word from source to the destination specified in the instruction.

Source Register , Memory location , Immediate number

Destination Register or memory location

Eg: MOV CX,0037H which means CX0037H

MOV BL,[4000H] which means BL  DS:[4000H]

2. PUSH Src

Push the source (word) into the stack and decrement the stack pointer by two.

Src Register , Memory location

Eg PUSH CX ; SS[SP-1] CH , SS[SP-2]CL

; SPSP-2

PUSH DS ; DSSS[SP,SP+1]

; SPSP-2

3. POP Destination

POP a word from stack into given destination and increment stack pointer by 2.

Destination must be word(16 bit)

Destination Register (except CS), Memory location

Eg POP CX ;CH SS[SP],CLSS:[SP+1]

SP SP+2

POP DX ; DS SS:[SP,SP+1]

; SPSP+2
32
Microprocessor Notes
4. PUSHF

Push the value into flag register and decrement stack pointer by 2.

Eg PUSHF ;SS[SP-1]FlagH ,SS[SP-2]FlagL , SP SP -2

5. POPF

POP a word from the stack into the Flag register

Eg POPF ;FlagH SS:[SP],FlagL  SS:[SP+1], SP SP +2

6. XCHG Destination , Source

Exchange a byte/word between the source and destination specified in the instruction

Source Register , Memory location

Destination  Register , Memory location

Eg XCHG CX,BX ; CXBX

7.XLAT

Move Into AL, the contents of the memory location in Data Segment, whose effective address formed by the
BX and AL.

EG : XLAT ,ALDS:[BX+AL] ;

i.e if DS 1000H; BX =0200H; AL = 03H

10000 … DS * 16 ;

+ 0200 ... BX

+ 03 ….AL

33
Microprocessor Notes
 = 10203H AL[10203H];

8) LAHF

Loads AH with lower byte of the Flag Register.

9) SAHF

Stores the content of AN into the lower byte of the Flag Register.

10)LEA register,source

Loads effective address (offset address) of the source into the given register.

eg LEA BX, Total ; BX  offset address of Total in Data Segment.

11 )LDS destination register, source

Loads the destination register and DS register with offset address and segment address specified by the source.

Eg: LDS BX, Total ; BX  {DS: [Total], DS: [Total + 1])},

; DS{ DS: [Total + 2], DS: [Total + 3] }

12) LES destination register, source

Loads the destination register and ES register with the offset address and the segment address indirectly spec
the source

Eg: LES BX, Total ; BX  {DS: [Total], DS: [Total + 1]}

; ES  (DS: [Total + 2], DS: [Total + 3])

13)IN destination register, source port

Loads the destination register with the contents of the I/O port specified by the source.

Source: 8-bit address of I/O Port [Direct addressing] Or: DX register [Indirect addressing]

Destination: AL/ AH for 8-bit Port (NOT necessarily 8-bit port address),

34
Microprocessor Notes
AX for a 16-bit Port

Eg: IN AL, 8OH ;AL[80H]I/O as I/O Port 80H in an 8-bit port

IN AX, 8OH ; AX[80H]I/O as I/O Port 80H in an 16-bit port

IN AL, DX ; AL [DX]I/O as I/O Port pointed by DX in an 8 bit port

IN AX, DX ; AX [DX]I/O as I/O Port pointed by DX in an 16 bit port

14)OUT destination port, source register

Loads the destination I/O port with the contents of the source register.

Eg OUT 80H, Al ;[80H] I/O  AL as I/O Port 80H in an 8-bit port

OUT 80H, AX ; [80H]I/O AX as I/O Port 80H in an 16-bit port

OUT DX, AL ; [DX] I/O AL as I/O Port pointed by DX in an 8 bit port

OUT DX, AX ; [DX] I/O AX as I/O Port pointed by DX in an 16 bit port

Arithmetic Instructions :-

1) ADD/ADC destination, source

Adds the source to the destination and stores the result back in the destination.

Source: Register, Memory Location, Immediate Number

Destination: Register

Both, source and destination have to be of the same size.

ADC also adds the carry into the result.

Eg: ADD AL, 25H ; AL  AL + 25H

ADD BL,.CL ; BL BL + CL ;

ADC BX, CX ; BX  BX + CX + Carry Flag

35
Microprocessor Notes
2) SUB/SBB destination, source

It is similar to ADD/ADC except that it does subtraction.

3) INC destination

Adds "1" to the specified destination. Destination: Register, Memory Location

Note: Carry Flag is NOT affected.

Eg:.INC AX ;AX AX +1

INC BL ; BL  BL + 1 ;

INC BYTE PTR [BX] Increment the byte pointed by BX in the Data Segment ; i.e. DS:[BX]  DS;[BX + 1]

INC WORD PTR [BX] Increment word pointed by BX in the Data Segment ;-{DS[BX], DS:[BX+1]};  {D
DS[BX+1]}+1

4) DEC destination

It is similar to INC. Here also Carry Flag is NOT affected

5) MUL source (unsigned 8/16-bit register)

If the source is 8-bit, it is multiplied with AL and the result is stored in AX (AH-higher byte, AL-

lower byte)

If the source is 16-bit, it is multiplied with AX and the result is AX-lower byte)

Source: Register, Memory Location

MUL affects AF, PF, SF and ZF.

Eg:MUL BL ; AX  AL x BL

MUL BX ; DX-AX AX x BX

MUL BYTE PTR [BX] ;AX  AL x DS:[ BX]

36
Microprocessor Notes
6) IMUL source(signed 8/16-bit register)

Same as MUL except that the source is a SIGNED number.

7) DIV source(unsigned 8/16-bit register - divisor)

This instruction is used for UNSIGNED division.

Divides a WORD by a BYTE, OR a DOUBLE WORD by a WORD.

If the divisor is 8-bit then the dividend is in AX register.

After division, the quotient is in AL and the Remainder in AH.

If the divisor is 16-bit then the dividend is in DX-AX registers.

After division, the quotient is in AX and the Remainder in DX.

Source: Register, Memory Location

ALL flags are undefined after DIV instruction.

Eg: DIV BL . ; AX ÷ BL AL  Quotient; AH Remainder

DIV BX ; (DX,AX) ÷BX :- AX  Quotient; DX Remainder

Please note If is too large to fit in AL AX for 16-bit divisor), then 8086 does a type 0 interrupt (divide error)

8) IDIV source (signed 8/16-bit register - divisor)

Same as DIV except that it is used for SIGNED division.

9) NEG destination

This instruction forms the 2's complement of the destination, and stores it back in the destination.

Destination: Register, Memory Location

ALL condition flags are updated.

37
Microprocessor Notes
Eg: Assume AL= 0011 0101 = 35 H then NEG AL AL1100 1011 = CBH. i.e. AL  2's Complement (AL)

1O) CMP destination, source

This instruction compares the source with the destination.

The source and the destination must be of the same size.

Comparison is done by internally SUBTRACTING the SOURCE form DESTINATION.

The result of this subtraction is NOT stored anywhere, instead the Flag bits are affected.

Spurce: Register, Memory Location, Immediate Value

Destination: Register, Memory Location - ALL condition flags are updated.

Eg: CMP BL, 55H ; BL compared with 55H i.e. BL - 55H. ;

11) CBW [Convert signed BYTE to signed WORD]

This instruction copies sign of the byte in AL into all the bits of AH

All is then called sign extension of AL.

No Flags affected.

Eg: Assume AX = XXXX XXXX 1001 0001

Then CBW gives AX = 1111 1111 1001 0001

12) CWD [Convert signed WORD to signed DOUBLE WORD]

This instruction copies sign of the WORD in AX into all the bits of DX. DX is then called sign extension of AX.

No Flags affected.

Eg: Assume AX = 1000 0000 1001 0001

DX = XXXX XXXX XXXX XXXX

Then CWD gives AX = 1000 0000 1001 0001

DX = 1111 1111 1111 1111

Note: Both CBW and CWD are used for Signed Numbers.
38
Microprocessor Notes
Decimal Adjust Instructions

13) DAA [Decimal Adjust for Addition]

It makes the result in packed BCD form after BCD addition is performed. It works ONLY on AL register.

All Flags are updated; OF becomes undefined after this instruction.

For AL register ONLY If D3 — Do > 9 OR Auxiliary Carry Flag is set => ADD 06H to AL.

If D7- D4 > 9 OR Carry Flag is set => ADD 60H to AL.

Assume AL = 14H CL = 28H Then ADD AL, CL gives AL = 3CH

Now DAA gives AL = 42 (06 is added to AL as C > 9) If you notice, (14)10 + (28)10 = (42)10

14) DAS [Decimal Adjust for Subtraction]

It makes the result in packed BCD form after BCD tubtraction is performed. It works ONLY on AL register.

. All Flags are updated; OF becomes undefined after this instruction.

for AL register ONLY If D3 — Do > 9 OR Auxiliary Carry Flag is set => Subtract 06H from AL.

If D7 — D4 > 9 OR Carry Flag is set => Subtract 60H from AL.

Assume AL = 86H CL = 5711 Then SUB AL, CL gives AL = 2FH

Now DAS gives AL = 29 (06 is subtracted from AL as F > 9) If you notice, (86)10 - (57) 10 = (29) 10

ASCII Adjust Instructions (for the AX register ONLY)

15) AAA [ASCII Adjust for Addition]

It makes the result in unpacked BCD form. In ASCII Codes, 0 ... 9 are represented as 30 39. When we add ASCII
we need to mask the higher byte (Eg: 3 of 39).

This can be avoided if we use AAA instruction after the addition is performed.

AAA updates the AF and the CF; But OF, PF, SF, ZF are undefined after the instruction.

Eq: Assume AL = 0011 0100 ... ASCII 4.

39
Microprocessor Notes
 CL = 0011 1000 ... ASCII 8.

Then ADD AL, CL gives AL = 01101100 i.e. AL = 6CH ... it is the Incorrect temporary Result

16) AAS [ASCII Adjust for Subtraction]

It makes the result in unpacked BCD form. In ASCII Codes, 0 ... 9 are represented as 30 ... 39. When we subtra
Codes, we need to mask the higher byte (Eg: 3 of 39). This can be avoided if we use AAS instruction af
subtraction is performed. AAS updates the AF and the CF; But OF, PF, SF, ZF are undefined after the instruct
Assume AL = 0011 1001 ... ASCII 9. CL = 0011 0101 ... ASCII 5. Then SUB AL, CL gives AL = 0000 0100 i.e. AL = 04
AAS gives AL = 0000 0100 ... Unpacked BCD for 4. Carry = 0 ... this indicates that the answer is 04.
17) AAM [BCD Adjust After Multiplication]
Before we multiply two ASCII digits, we mask their upper 4 bits. Thus we have two unpacked BCD operands. A
two unpacked BCD operands are multiplied, the AAM instruction converts this result intc unpacked BCD form
AX register. AAS updates PF, SF ZF; But OF, AP, CF are undefined after the instruction. Eq: Assume AL = 0000
unpacked BCD 9. CL = 0000 0101 ... unpacked BCD 5. Then MUL CL gives AX = 0000 0000 0010 1101 = 002D
AAM gives AX = 0000 0100 0000 0101 = 0405H. This is 45 in the unpacked BCD form.
18)AAD [Binary Adjust before Division]
This instruction converts the unpacked BCD digits in AH and Al into a Packed BCD in AL. AAD updates PF, SF ZF;
AF, CF are undefined after the instruction. Eg: Assume CL = 07H. AH = 04. AL = 03. AX = 0403H ... unpacked
(43)i0 Then AAD gives AX = 002BH i.e. (43)i0 Now DIV CL gives (divide AX by unpacked BCD in CL) AL = Quotient
unpacked BCD AH = Remainder = 01 unpacked BCD
Logical Instructions Bit Manipulation instructions
1) NOT destination
This instruction forms the l's complement of the destination, and stores it back in the destination. Dest
Register, Memory Location. No Flags affected. Eg: Assume AL= 0011 0101 NOT AL ; AL  1100 1010 ... i
l's Complement (AL)
2) AND destination, source

This instruction logically ANDs the source with the destination and stores the result in the destination. Sou
destination have to be of the same size. Source: Register, Memory Location, Immediate Value Destination: R
Memory Location PF, SF, ZF affected; CF, OF -0; AF becomes undefined. Eg: AND BL, CL ; BL BL AND CL

3) OR destination ,source

This instruction logically Ors the source with the destination and stores the result in the destination. Sour
destination have to be of the same size. Source: Register, Memory. Location, Immediate Value.

Destination: Register, Memory Location

PF, SF, ZF affected; CF, OF 4- 0; AF becomes undefined

40
Microprocessor Notes
Eg: OR BL, CL. ; BL BL OR CL destination.

4) XOR destination , source:

Source and destination have to be of the same size. Source: Register, Memory Location, Immediate Value Dest
Register, Memory Location PF, SF, ZF affected; CF, OF . Eg: XOR BL, CL ; BL  BL XOR CL

5) TEST destination, source

This instruction logically ANDs the source with the destination BUT the RESULT is NOT STORED ANYWHERE. O
FLAG bits are AFFECTED.
Source: Register, Memory Location, Immediate Value
Destination: Register, Memory Location
PF, SF, ZF affected; CF, OF E 0; AF becomes undefined.
Eg: TEST BL, CL; BL AND CL; result not stored; Flags affected.
Note: Don't forget this instruction because it will be used later in multiprocessor systems!

Shift Instructions
1) SAL/SHL destination, count
LEFT-Shifts the bits of destination. MSB shifted into the CARRY. LSB gets a 0.
Bits are shifted 'count' number of times.
If count = 1, it is directly specified in the instruction.
If count > 1, it has to be given using CL Register.
Destination: Register, Memory Location.
for this Eg: SAL BL, 1 ; Left-Shift BL bits, once. Assume: Before Operation: BL = 0011 0011 and CF = 1 .
2) SHR destination, count
RIGHT-Shifts the bits of destination. MSB gets a 0 (. Sign is lost). LSB shifted into the CARRY.
Bits are shifted 'count' number of times. If count is 1, it is directly specified in the instruction. If count > 1, it ha
given using CL register. Eg: SHR BL, 1 ; Right-Shift BL bits, once. Assume:
Before Operation: BL = 0011 0011 and CF = 0
After Operation: BL = 00011 1001 and CF = 1
010I0I1i11010I1
3) SAR destination, count
RIGHT-Shifts the bits of destination. MSB placed in MSB itself Sign is preserved). LSB shifted into the CARRY.
Bits are shifted 'count' number of times. If count is 1, it is directly specified in the instruction. If count > 1 it ha
given using CL register. Destination: Register, Memory Location
Eg: SAR BL, 1 ; Right-Shift BL bits, once.
Assume: Before Operation: BL = 0011 0011 and CF = 0
After Operation: BL = 0001 1001 and CF = 1.
Rotate Instructions
1) ROL destination, count
LEFT-Shifts the bits of destination.
MSB shifted into the CARRY.
41
Microprocessor Notes
MSB also goes to LSB. Bits are shifted 'count' number of times.
If count > 1, it has to be loaded in the CL register, and CL gives the count in the instruction.
If count = 1, it is directly specified in the instruction.
Destination: Register, Memory Location
Eg: ROL BL, 1 ; Left-Shift BL bits once.
More examples: MOV CL, 05H ; Load number of shifts in CL register.
ROL BL, CL ; Left-Shift BL bits CL (5) number of times.

2) ROR destination, count

RIGHT-Shifts the bits of destination. LSB shifted into the CARRY. LSB also goes to MSB. Bits are shifted 'count'
of times. If count = 1, it is directly specified in the instruction. If count > 1, it has to be loaded in the CL register,
gives the count in the instruction. Eg: ROR BL, 1

3) RCL destination, count

LEFT-Shifts the bits of destination. MSB shifted into the Carry Flag (CF). CF goes to LSB. Bits are shifted 'count' n
of times. If count = 1, it is directly specified in the instruction. If count > 1, it has to be loaded in the CL register,
is specified as the count in the instruction. Destination: Register, Memory Location
Eg: RCL BL, 1
4) RCR destination, count
RIGHT-Shifts the bits of destination. LSB shifted into the CF. CF goes to Msg. Bits are shifted 'count' number o
If count = 1, it is directly specified in the instruction. If count > 1, it has to be loaded in the CL register, an
specified as the count in t instruction.
Destination: Register, Memory Location Eg: RCR BL, 1
More examples: MOV CL, O5H ; Load number of shifts in CL register.
RCR BL, CL ; Right-Shift BL bits CL (5) number of times.

Program Execution and transfer Instructions These instructions cause a branch in the program sequence. Ther
main types of branching:
i. Near branch ii. Far Branch
This is an Intra-Segment Branch i.e. the branch is to a new location within the current segment
i. Near Branch only.
Thus, only the value of IP needs to be changed. If the Near Branch is in the range of —128 to 127, then it is cal
Short Branch.
ii. Far Branch .
This is an Inter-Segment Branch i.e. the branch is to a new location in a different segment. Thus, the values of
IP need to be changed.
JMP (Unconditional Jump) INTRA-Segment (NEAR) JUMP The Jump address is specified in two ways: 1)
Segment Direct Jump The new Branch location is specified directly in the instruction . The new address is calcul
adding the 8 or16-bit displacement to the IP. The CS does not change. A +ve displacement means that the
ahead (forward) in the program. A -ve displacement means that the Jump is behind (backward) in the progra
also called as Relative Jump. Eg: JMP Prey ; IP offset address of "Prev'. JMP Next ; IP  offset address of "Nex

42
Microprocessor Notes
2) INTRA-Segment Indirect Jump The New Branch address is specified indirectly through a register or a m
location (in DS only). The value in the IP is replaced with the new value. The CS does not change.
Eg: JMP WORD PTR [BX] ; IP  {DS[BX], DS: [BX+I]}
3)INTER-Segment (FAR) JUMP The Jump address is specified in two ways: 3) INTER-Segment Direct Jump T
Branch location is specified directly in the instruction Both CS and IP get new values, as this is an inter-segmen
Eg: Assume NextSeg is a label pointing to an instruction in a different segment. JMP NextSeg ; CS and IP get th
from the label NextSeg.
4) INTER-Segment Indirect Jump g The new Branch location is specified indirectly through a register or a lo
memory Both CS and IP get new values, as this is an inter-segment jump.
Eg:JMP DWORD PTR [BX] ; IP  (DS[BX], DS:[BX+1]}
; CS  {DS[BX+2], DS[BX+3]}

Eg: CALL subAdd ; {SS[SP-1], SS[SP-2]} IP, SP (-SP - 2, ; IP  New Offset Address of subAdd.
INTER-Segment (FAR) CALL
The new subroutine called is in another segment (hence inter-segment). Here CS and IP both get new valu
CALL address can be specified directly OR through Registers or Memory Location The following sequence is ex
for a Far CALL: I.PUSH CS into the Stack. ii. Decrement SP by 2. iii. PUSH IP into the Stack. - iv. Decrement SP
Load CS with new segment address. - vi. Load IP with new offset address. vii. Control transferred to a subroutin
new segment. Eg: CALL subAdd ; {SS:[SP-1J, SS:[SP-23) F CS, SP F SP - 2, (SS:[SP-1], SSISP-2D E- CS, SP F SP -2, ; C
Segment Address of subAdd, ; IP F New Offset Address of subAdd.
There is NO PROVISION for Conditional CALL.
RET -- Return instruction - RET instruction causes the control to return to the main program from the subroutin
- Intrasegment-RET Eg: RET
RET n ; IP SS:[SP], SS:(SP+1]
; SP  SP + 2
;IP  SS:[SP], SS:[SP+1] ;
;SP SP + 2 + n
Intersegment-RET Eg: RET
RET n ; IP SS:[SP], SS:[SP+I.]
; CS  SS:[SP+2], SS:[SP+3]
; SP  SP + 4
;IP  SS:[SP], SS:[SP+1]
; CS  SS:[SP+2], SS:{SP+3]
; SP  SP + 4 + n
Iteration Control Instructions
These instructions cause a series of instructions to be executed repeatedly. for number of iterations is loade
register. If CX is decremented by 1, after every iteration. Iterations occur until CX = 0. The maximum dif
between the address of the instruction and the address of the Jump can be 127.
4) LOOP Label

43
Microprocessor Notes
jump to specified label if CX not equal to 0; and decrement CX.
Eg: MOV CX, 40H
BACK: MOV AL, BL
ADD AL, BL
MOV BL, AL
LOOP BACK ; Do CX CX - 1.
; Go to BACK if CX not equal to 0.
LOOPE/LOOPZ Label (Loop on Equal / Loop on Zero)
Same as above except that looping occurs ONLY if Zero Flag is set (i.e. ZF = 1)
Eg: MOV CX, 40H
BACK: MOV AL, BL
ADD AL, BL
MOV BL,AL
LOOPZ BACK ; Do CX f- CX - 1.
; Go to BACK if Do not equal to 0 and ZF = 1.
• LOOPNE/LOOPNZ Label (Loop on NOT Equal / Loop on NO Zero)
Same as above except that looping occurs ONLY if Zero Flag is reset (i.e. ZF = 0)
Eg: MOV CX, 40H
BACK: MOV AL, BL ADD AL, BL
MOV BL, AL
LOOPZ BACK ; Do CX CX - 1.
; Go to BACK if CX not equal to 0 and ZF = 0.
Type 6) Processor Control Machine Control Instructions (these are instructions that directly operate on Flag Reg
For Carry Flag
1) STC
This instruction sets the Carry Flag. No Other Flags are affected.
2) CLC
This instruction clears the Carry Flag. No Other Flags are affected.
3) CMC
This instruction Complements the Carry Flag. No Other Flags are affected.
For Direction Flag
4) STD
This instruction sets the Direction Flag. No Other Flags are affected.
5) CLD
This instruction clears the Direction Flag. No Other Flags are affected.
For Interrupt Enable Flag
6) STI
This instruction sets the Interrupt Enable Flag. No Other Flags are affected.
7) CLI
This instruction clears the Interrupt Enable Flag. No Other Flags are affected.

44
Microprocessor Notes
7) External Hardware Synchronization Instructions
1) ESC
This is an 8086 instruction-prefix used to indicate that the current instruction is for the 8087 NDP. We
homogeneous program for the two processors 8086 and 8087. Instructions are fetched by 8086 In to its queu
duplicates the instruction queue of 8086 and monitors this queue. When an instruction with ESC prefix (bina
11011) is encountered, 8087 is activated, and hence it executes the instruction. 8086 treats the instruction a
ESC has to be written before each 8087 instruction. 2) WAIT
This instruction is used to synchronize 8086 with the 8087 Co-Processor via the TEST input pin of 8086. Wh
8087 is busy it puts a "1" on its BUSY o/p line connected to the TEST i/p of the
The WAIT instruction makes the µP check the TEST pin. If the µP checks the TEST pin and finds a "1" on i
understands that 8087 is busy and so it enters wait state. Here it does no processing. It can come out of this id
in 2 ways:
i. TEST input is made low i.e. 8087 is no longer busy. This takes 8086 completely out of the IDLE state.
ii. Valid Interrupt on INTR or NMI In this case 8086 exits wait state, executes the ISR for the interrupt, and t
enters th4 WAIT state. (This is because the address of the WAIT instruction is what was pushed into the stack
executing the ISR.)
Thus if we write a WAIT instruction before every 8087 instruction, we can ensure that 8087 i ready for execu
own instruction whenever it arrives. WAIT can also be written before an 8086 instruction that requires the res
previous 8087 operation.

3) LOCK
This is an 8086 instruction prefix. It prevents any external bus master from taking control of the system bus
executor of the instruction, which has a LOCK prefix. It causes 8086 to activate the LOCK signal so that no ot
master takes control of the system bus.
4) NOP
There is no operation performed while executing this instruction. 8086 requires 3 T-States for this instructi
mainly used to insert time delays, and can also be used while debugging.
5) HLT
This instruction causes 8086 to stop fetching any more instructions. - 8086 enters Halt state. 8086 can come
this halt state only if there is a valid hardware interrupt (NMI or INTR) or by reset.
8) Interrupt Control Instructions
1) INT Type
This can be a number between 0 ...255 This instruction causes an interrupt of the given type.
The following action takes place:
i. PUSH Flag Register onto the Stack. SP decremented by 2.
ii. IF and TF are cleared. No other flags are affected.
iii. PUSH CS onto the Stack. SP decremented by 2
iv. PUSH IP onto the Stack. SP decremented by 2. In all SP decremented by 6.
v. New value of IP taken from location type x 4.
Eg: INT 1 ;IP  { [00004] and [00005]) ( a s 1 x 4 = 00004H)
vi. New value of CS taken from location (type x4)+2

45
Microprocessor Notes
 Eg: INT 1 ; CS  ([00006] and [00007])
Execution of ISR begins from the address formed by new values of CS and IP.
2) INTO (Interrupt on Overflow)
This instruction causes an interrupt of type 4, ONLY if Overflow Flag (OF) is set. The above sequence is follow
the control is transferred to the location pointed by 0001011.
Eg: INTO ; If OF = 1 then execute INT 4. Please Note:- This is INTO (0 for Overflow) and NOT INT 0 (i.e. Type 0 =
Divide Interrupt).
3) IRET (Return from ISR)
This instruction causes the 8086 to return to the main program from an ISR.
The following action takes place:
i. POP IP from the Stack.
SP incremented by 2.
ii. POP CS from the Stack.
SP incremented by 2.
iii. POP Flag Register from the Stack.
SP incremented by 2.
In all SP incremented by 6.
Execution of the Main Program continues from the address formed values of CS and IP restored from the stack.

String Instructions of 8086

A String is a series of bytes stored sequentially in the memory. String Instructions operate on such "String
Source String is at a location pointed by SI in the Data Segment. The Destination String is at a location pointed
the Extra Segment. The Count for String operations is always given by CX. Since CX is a 16-bit register we can t
max 64 KB using a string instruction. SI and/or DI are incremented/decremented after each operation dependin
the direction flag "DF" in the flag register. If DF = 0, it is auto increment. This is done by CLD instruction. If DF =
auto decrement. This is done by STD instruction.
1) MOVS: MOVSB/MOVSW (Move String)
It is used to transfer a word/byte from data segment to extra segment. The offset of the so
data segment is in SI. The offset of the destination in extra segment is in DI. SI and DI are incremented / decrem
depending upon the direction Flag
Eg: MOVSB ; ES:[DI]  DS:[SI] ... byte transfer
; SI  SI ± 1 ... depending upon DF ;
;DI  DI ± 1 ... depending upon DF
2) LODS: LODSB/LODSW (Load String)
It is used to Load AL (of AX) register with a byte (or word) from data segment. The offset of the source
segment is in SI. SI is incremented / decremented depending upon the direction flag (DF).
Eg: LODSB; AL  DS:[SI] ... byte transfer
; SI  SI ± 1 ... depending upon DF
LODSW; AL  DS: [SI]; AH  DS:[SI + 1] ; SI  S. ± 2

46
Microprocessor Notes
 3) STOS: STOSB/STOSW (Store String)
It is used to Store AL (or AX) into a byte (or word) in the extra segment. The offset of the source in extra seg
in DI. DI is incremented / decremented depending upon the direction flag (DF).
Eg: STOSB; ES:[DI]  AL ... byte transfer
; DI  DI ± 1 ... depending upon DF
STOSW; ES: [DI]  AL; ES:[DI+1]  AH ... word transfer
; DI  DI ± 2 ... depending upon DF
4) CMPS: CPMSB/CMPSW (Compare String)
It is used to compare a byte (or word) in the data segment with a byte (or word) in the extra segment. Th
of the byte (or word) in data segment is in SI. The offset of the byte (or word) in extra segment is in DI. SI and
incremented / decremented depending upon the direction flag. Comparison is done by subtracting the byte (o
from extra segment from the byte (or word) from Data segment. The Flag bits are affected, but the result is not
anywhere.
Eg :CMPSB; Compare DS:[SI] with ES:[ DI] ... byte operation ;
SI  SI ± 1 ... depending upon DF ;
DI  DI ± 1 depending upon DF
CMPSW ; Compare {DS:[SI]. DS[SI+1]}- ; with {ES:[DI] ES:[DI+1]} ;
SI  SI ±2 ... depending upon DF ;
DI  DI ± 2 ... depending upon DF
5) SCAS: SCASB/SCASW (Scan String) It is used to compare the contents of AL (or AX) with a byte (or word
extra segment. The offset of the byte (or word) in extra segment is in DI. DI is incremented / decrem
depending upon the direction flag (DF). Comparison is done by subtracting a byte (or word) from
segment from AL (or AX). The Flag bits are affected, but the result is not stored anywhere.
Eg: SCASB; Compare AL with ES:[DI] … byte operation
DI  DI ± 1 ... depending upon OF
SCASW; Compare {AX} with {ES:[DI], ES: [DI+1]} DI DI ± 1 ... depending on DF
REP (Repeat prefix used for string instructions)
This is instruction prefix, which can be used in string instructions.
It used with string instructions only. I
It causes the instruction to be repeated CX number of times.
After each execution, the SI and DI registers are incremented/decremented based on the DF (Direction Flag
Flag register and CX is decremented. i.e. DF = 1; SI, DI decrements. .Thus, it is important that before we use
instruction prefix the following steps must be came out: CX must be initialized to the Count value.
decrementing is required, DF must be set - using STD instruction else cleared using CLD instruction.
- EG: MOV CX, 0023H
CLD
REP MOVSB
The above section of a program will cause the following string operation ES:[ DI]  DS:[SI], SI  SI + 1, DI  DI
 CX - 1 to be executed 23H times (as CX = 23H) in auto incrementing mode (as DF is cleared).
6) REPZ/REPE (Repeat on Zero/Equal)

47
Microprocessor Notes
It is a conditional repeat instruction prefix. It behaves the same as a REP instruction provided the - Zero Flag is
ZF = 1),It is used with CMPS instruction.

7) REPNZ/REPNE (Repeat on No Zero/Not Equal)

- It is a conditional repeat instruction prefix. It behaves the same as a REP instruction provided the Zero Flag
(i.e. ZF = 0),It is used with SCAS instruction.

Assembler directives of 8086:-

Assembly language has 2 types of statements:

1. Executable: Instructions that are translated into Machine Code by the assembler. 2. Ass
Directives: Statements that direct the assembler to do some special task. No M/C language code is produced fo
statements. Their main task is to inform the assembler about the start/end of a segment, procedure or prog
reserve appropriate space for data storage etc. Some of the assembler directives are listed below
1. DB (Define Byte) ; Used to define a Byte type variable. ; Assembler reserves 1 Byte of memory for the va
named SUM and initialize it to 0.
Eg: SUM DB 0
2. DW (Define Word) ; Used to define a Word type variable (2 Bytes).
3. DD (Double Word) ; Used to define a Double Word type variable (4 Bytes).
4. DQ (Quad Word) ; Used to define a Quad Word type variable (8 Bytes).
5. DT (Ten Bytes) ; Used to define 10 Bytes to a variable (10 Bytes).
6. DUP(); Copies the contents of the bracket followed by this keyword into the memory location specified be
Stores LIST as a series of 10 bytes initialized to Zero.
Eg: LIST DB 10 DUP (0)
7. SEGMENT ; Used to indicate the beginning of a segment.
8. ENDS ; Used to indicate the end of a SEGMENT.
9. ASSUME Eg:Assume CS:Code; Associates a logical segment with a processor segment. ; Makes the segment
the actual Code Segment. ;
10.PROC ; Used to indicate the beginning of a procedure.
11.ENDP ; Used to indicate the end of a procedure.
12.END ; Used to indicate the end of a program.

48
Microprocessor Notes
 PROGRAMS:-
Refer class notes.

49
Microprocessor Notes
 Interfacing:-
Refer class notes.

50
Microprocessor Notes
 8259- PIC
ARCHITECTURE OF 8259:-

1) PIC 8259 is a programmable interrupt controller.

2) A single 8259 can provide 8 interrupts and 8259 in cascaded configuration with 1 Master and 8
can provide up to 64 interrupts.
51
Microprocessor Notes
 3) It is necessary to initialize the 8259 with the help of ICW’S to decide several properties such as
numbers, priority, masking, triggering etc.
4)In a cascaded configuration, each 8259 has to be individually initialized, master as well as each s
5)The architecture of 8259 mainly consists of the following:-
i. Interrupt Request Register (IRR):-
An IRR is a 8-bit register, one bit is reserved for each interrupt lines and in 8259 there are 8 in
lines named as IR0 to IR7.
Whenever an interrupt request occurs on any of these lines, the corresponding bit is set in th
ii. In-Service Register (InSR):-
An InSR is a 8-bit register which is used to store the level of the interrupt request which is cur
being serviced.
iii. Interrupt Mask Register (IMR):-
An IMR is a 8-bit register which is used to store the masking pattern for the interrupts, it store
bit per interrupt level.

iv. Priority Resolver :-

Priority resolver is that component which examines the IRR,InSR and IMR and decides the int
of the highest priority and that interrupt is sent by 8259 on the INTR line of the microprocess
v. Control Logic :-
Control Logic unit consists of INT and 𝐼𝑁𝑇𝐴 ̅̅̅̅̅̅̅ lines.
INT line of 8259 is used to interrupt the microprocessor on the INTR line of the microprocesso
The microprocessor sends the response of the interrupt request made by 8259 on the ̅̅̅̅̅̅̅ 𝐼𝑁𝑇𝐴
the 8259.
It is also used to control the remaining blocks of 8259.
vi. Data Bus Buffer :-
it is the bi-directional buffer which is used to interface the 8-bit data bus of 8259 with the ext
System bus.
vii. Read/Write Logic :-
̅̅̅̅, 𝑊𝑅
It is used to accept the 𝑅𝐷 ̅̅̅̅̅ , A0 and CS signal.
It also holds the ICWS and OCWS.
viii. Cascade Buffer/Comparator :-
Cascade Buffer is available only in cascaded configuration.
Cascade Buffer mainly consists of two parts and they are as follows:-
1. CAS0,CAS1,CAS2 Lines :-
In 8259, there are 8 interrupt levels therefore 3 lines are enough, since 2 3=8.
52
Microprocessor Notes
 These lines are used as output lines by the Master to send the slave identification number.
These lines are used as input by the Slaves to receive the Slave Identification number as inpu
̅̅̅̅/𝑬𝑵
2. 𝑺𝑷 ̅̅̅̅:-
In Buffered mode, EN line is used to enable the buffer.
In remaining mode, SP line is available and SP line for master =1 and for slave SP line =0.

Priority modes of 8259 :-

Refer class notes.

53
Microprocessor Notes
Command Words of 8259A

• The command words of 8259A are classified in two groups

1. Initialization command words (ICW) and
2. Operation command words (OCW).
• Initialization Command Words (ICW): Before it starts
functioning, the 8259A must be initialized by writing two to four
command words into the respective command word registers.
These are called as initialized command word

• If A0 = 0 and D4 = 1, the control word is recognized as ICW1. It

contains the control bits for edge/level triggered mode,
single/cascade mode, call address interval and whether ICW4 is
required or not.
• If A0=1, the control word is recognized as ICW2. The ICW2 stores
details regarding interrupt vector addresses. The initialisation
sequence of 8259A is described in form of a flow chart in fig 3
below.
• The bit functions of the ICW1 and ICW2 are self explanatory as
shown in fig below.

54
Microprocessor Notes
 ICW1

ICW2

NO (SINGLE =1) A A : IN CASCADE MODE ?

YES (SINGLE =0)

ICW3

NO (IC4 =0)
B B : IS ICW4 NEEDED ?
YES (IC4 = 1)
ICW4

Ready to Accept
Interrupt Request
Fig 3: Initialisation Sequence of 8259A

55
Microprocessor Notes
A0 D7 D6 D5 D4 D3D2 D1 D0
SNG
0 A7 A6 A5 1 LTIM ADI L IC4

A7-A5 of Interrupt ICW1 1 = ICW4 Needed

vector address MCs
80/85 mode only 0 = No ICW4 Needed
1 – Single
1 – Level Triggered
0 - Cascaded
0 – Edge Triggered
Call Address Interval
1 – Interval of 4 bytes
ICW2 0 – Interval of 8 bytes.

AD D D5D4
DD
3 2 D1 D0
0 7 6

56
Microprocessor Notes
 • T7 – T3 are A15 – A11 of interrupt address
• A10 – A9, A8 – Selected according to interrupt request level. They
are not the address lines of Microprocessor
• A0 =1 selects ICW2
Fig 4 : Instruction Command Words ICW1 and ICW2

• Once ICW1 is loaded, the following initialization procedure is

carried out internally.
a. The edge sense circuit is reset, i.e. by default 8259A
interrupts are edge sensitive.
b. IMR is cleared.
c. IR7 input is assigned the lowest priority.
d. Slave mode address is set to 7.
e. Special mask mode is cleared and status read is set to IRR.
f. If IC4 = 0, all the functions of ICW4 are set to zero.
Master/Slave bit in ICW4 is used in the buffered mode only.

• In an 8085 based system A15-A8 of the interrupt vector address are

the respective bits of ICW2.
• In 8086 based system A15-A11 of the interrupt vector address are
inserted in place of T7 – T3 respectively and the remaining three bits
A8, A9, A10 are selected depending upon the interrupt level, i.e. from
000 to 111 for IR0 to IR7.
57
Microprocessor Notes
• ICW1 and ICW2 are compulsory command words in initialization
sequence of 8259A as is evident from fig, while ICW3 and ICW4 are
optional. The ICW3 is read only when there are more than one 8259A
in the system, cascading is used ( SNGL=0 ).

58
Microprocessor Notes
• The SNGL bit in ICW1 indicates whether the 8259A in the cascade
mode or not. The ICW3 loads an 8-bit slave register. It detailed
functions are as follows.
• In master mode [ SP = 1 or in buffer mode M/S = 1 in ICW4], the 8-
bit slave register will be set bit-wise to 1 for each slave in the system
as in fig 5.
• The requesting slave will then release the second byte of a CALL
sequence. In slave mode [ SP=0 or if BUF =1 and M/S = 0 in ICW4] bits
D2 to D0 identify the slave, i.e. 000 to 111 for slave 1 to slave 8. The
slave compares the cascade inputs with these bits and if they are
equal, the second byte of the CALL sequence is released by it on the
data bus.

59
Microprocessor Notes
 Master mode ICW3
A D D D D
0 7 6 D5 D4 3 2 D1 D0

S S S S S S S
1 7 6 5 4 3 2 1 S0
Sn = 1-IRn Input has a slave
= 0 – IRn Input does not have a slave

Slave mode ICW3

D D D D
A0 7 6 D5 D4 3 2 D1 D0

1 0 0 0 0 0 ID2 ID1 ID0

D2D1D0 – 000 to 111 for IR0 to IR7 or slave 1 to slave 8

ICW4
D D D D
A0 7 6 D5 D4 3 2 D1 D0

1 0 0 0 SFNM BUF M/S AEOI µPM

Fig : ICW3 in Master and Slave Mode, ICW4 Bit Functions

60
Microprocessor Notes
• ICW4: The use of this command word depends on the IC4 bit of
ICW1. If IC4=1, IC4 is used, otherwise it is neglected. The bit functions
of ICW4 are described as follow:
• SFNM: If BUF = 1, the buffered mode is selected. In the buffered
mode, SP/EN acts as enable output and the master/slave is
determined using the M/S bit of ICW4.
• M/S: If M/S = 1, 8259A is a master. If M/S =0, 8259A is slave. If BUF
= 0, M/S is to be neglected.
• AEOI: If AEOI = 1, the automatic end of interrupt mode is selected.

• µPM : If the µPM bit is 0, the Mcs-85 system operation is selected

and if µPM=1, 8086/88 operation is selected.
• Operation Command Words: Once 8259A is initialized using the
previously discussed command words for initialisation, it is ready for
its normal function, i.e. for accepting the interrupts but 8259A has its
own way of handling the received interrupts called as modes of
operation. These modes of operations can be selected by
programming, i.e. writing three internal registers called as operation
command words.

61
Microprocessor Notes
• In the three operation command words OCW1, OCW2 and OCW3
every bit corresponds to some operational feature of the mode
selected, except for a few bits those are either 1 or 0. The three
operation command words are shown in fig with the bit selection
details.
• OCW1 is used to mask the masked and if it is 0 the request is
enabled. In OCW2 the three bits, R, SL and EOI control the end of
interrupt, the rotate mode and their combinations as shown in fig
below.
• The three bits L2, L1 and L0 in OCW2 determine the interrupt level to
be selected for operation, if SL bit is active i.e. 1.
• The details of OCW2 are shown in fig.
• In operation command word 3 (OCW3), if the ESMM bit, i.e. enable
special mask mode bit is set to 1, the SMM bit is neglected. If the
SMM bit, i.e. special mask mode. When ESMM bit is 0 the SMM bit is
neglected. If the SMM bit. i.e. special mask mode bit is 1, the 8259A
will enter special mask mode provided ESMM=1.
• If ESMM=1 and SMM=0, the 8259A will return to the normal mask
mode. The details of bits of OCW3 are given in fig along with their bit
definitions.

62
Microprocessor Notes
 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4 M3 M2 M1 M0

1 – Mask Set
0 – Mask Reset
Fig (a) : OCW1
D D D D
A0 7 6 5 4 D3 D2 D1 D0

0 0 ESMM SMM 0 1 P RR RIS

Fig (b) : OCW3

No Action 0 0 1 – Poll 0 0 No Action

0 1 Command 0 1
Reset Special 1 0 0 – No Poll 1 0 Read IRR on
Mask next RD pulse
Set Special 1 1 Command 1 1
Read IRR on
Mask next RD pulse

63
Microprocessor Notes
 Fig (c) :OCW2
A0 D7 D6 D5 D4 D3 D2 D1 D0

1 R SL EOI 0 0 L2 L1 L0

0 1 2 3 4 5 6 7
0 1 0 0 0 1 0 1
0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1

0 0 1 NON-SPECIFIC EOI COMMAND

0 1 1 SPECIFIC EOI COMMAND
1 0 1 ROTATE ON NON-SPECIFIC EOI MODE (SET)
1 0 0 ROTATE IN AUTOMATIC EOI MODE (SET)
0 0 0 ROTATE IN AUTOMATIC EOI (CLEAR)
1 1 1 ROTATE ON SPECIFIC EOI COMMAND
1 1 0 SET PRIORITY COMMAND*
0 1 0 NO OPERATION
64
Microprocessor Notes
 * - In this Mode L0 – L2 are used

Fig : Operation Command Word

65
Microprocessor Notes
 Interfacing and Working of a Single 8259 :-
A single 8259 can accept 8 interrupts.
Whenever 8259 is interrupt by a device in return it will interrupt the microprocessor on the
INTR line.
First there is a need to enable the INTR signal using the STI instruction (i.e. making IF=1).
It is compulsory to initialize the 8259 with ICWS, ICW1 and ICW2 are compulsory while ICW4 is
optional.
When one or more interrupts occur on the IR lines of 8259, the following sequence of the
events takes place:-
1. The bits are set in the IRR for those IR lines on which the interrupts occur.
2. The priority resolver checks IRR,InSR and IMR and determines the interrupt of
highest priority and interrupts the microprocessor on the INTR line.
3. On the receiving the interrupt on the INTR line, the microprocessor finishes the
̅̅̅̅̅̅̅
current instruction and acknowledges the interrupt by sending first pulse of 𝐼𝑁𝑇𝐴
̅̅̅̅̅̅̅ pin of the 8259.
on the 𝐼𝑁𝑇𝐴
4. On receiving the first ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 signal from the microprocessor, 8259 sets the
corresponding bit in the InSR and the bit in the IRR is reset and 8259 now prepares
to send the vector number N to the microprocessor.
5. Now the microprocessor sends the second 𝐼𝑁𝑇𝐴̅̅̅̅̅̅̅ pulse on the 𝐼𝑁𝑇𝐴
̅̅̅̅̅̅̅ pin of the 8259.
6. On receiving the second ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 pulse, 8259 sends the Vector Number N of one byte
to the microprocessor.
7. Now the microprocessor multiplies N*4, to get the values of CS and IP from the IVT.
8. The microprocessor pushes the contents of flag register, CS, IP in to the stack, clears
IF and TF and transfers program to the address of the ISR and the ISR thus begins.

66
Microprocessor Notes
 67
Microprocessor Notes
 Interfacing and Working of Cascaded 8259 :-
In cascaded configuration there are more than one 8259’s connected to the microprocessor.
A cascaded configuration increases the number of interrupts handled by the system.
In cascaded configuration, the maximum number of interrupts that can be handled are 64.
In cascaded configuration, there is 1 master 8259 and 8 slave 8259’s and master 8259’s ̅̅̅̅ ̅̅̅̅ is
𝑆𝑃/𝐸𝑁
connected to vcc(i.e. ̅̅̅̅
𝑆𝑃/𝐸𝑁̅̅̅̅ =+5v) and slave 8259’s are connected to GND(i.e. ̅̅̅̅ ̅̅̅̅=0).
𝑆𝑃 /𝐸𝑁
Each slave’s INT pin is connected to the IR lines of the master 8259 and master’s INT pin is
connected to the INTR line of the microprocessor.
It is necessary or compulsory to initialize each 8259’s (master as well as slaves) individually with
ICWS.
First the INTR signal of the microprocessor is enabled using the STI instruction.
And in cascaded configuration, the master addresses the individual slaves through the CAS 2, CAS1,
CAS0 lines connected from the master to each of the slaves.
When an interrupt occurs on the IR lines of slaves, the following events takes place:-
1. The slave 8259 will resolve the priority of the interrupts and will send the interrupt of
highest priority to the master 8259 on the IR line.
2. Now, the master 8259 will resolve the priorities among it slaves and will send the interrupt
of highest priority to the microprocessor on the INTR line.
3. On receiving the interrupt request, the microprocessor will finish the execution of its
current instruction and will send the first ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 pulse to the 8259 on the ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 pin.
̅̅̅̅̅̅̅
4. On receiving the first 𝐼𝑁𝑇𝐴 pulse, the master 8259 will send a 3-bit slave identification
number on its CAS lines and it will also set the corresponding bit in its InSR and the slave
8259 will identify its number on the CAS lines and will set the corresponding bit in its InSR
and will also start calculating or preparing the vector number N.
5. On receiving the second pulse of 𝐼𝑁𝑇𝐴̅̅̅̅̅̅̅ signal, the slave 8259 will place the vector number N
on the data bus.
6. Now the microprocessor will push the flag register on the stack along with CS and IP
registers and then it will perform N*4 and fetch the ISR address from the IVT and now the
microprocessor will load the ISR address in to CS and IP registers and thus then the ISR
begins.

68
Microprocessor Notes
 69
Microprocessor Notes
 8255-PPI

Architecture of 8255:-
8255 is a programmable general purpose I/O device.
8255 has 3 8-bit bi-directional I/O ports viz..Port A, Port B, Port C.
8255 provides 3 modes of data transfer and they are as follows:-
a) Simple I/O mode.
b) Handshake I/O mode.
c) Bi-directional Handshake I/O mode.
And 8255 also provides a Bit Set-Reset mode which is applicable only on Port C.

The architecture of 8255 can be divided in to following parts:-

1) Data Bus Buffer :-
It is a 8-bit bi-directional buffer which is used to interface the internal bus of 8255 with
the external data bus (i.e. with the data bus of the microprocessor).
The microprocessor transfers data to and from 8255 through this buffer.
2) Read/Write Logic :-
This unit is used to accept address and control signals from the microprocessor.
A1 and A0 lines of 8255 are connected with A2 and A1lines of the microprocessor and A1
and A0 lines of 8255 are used to select ports and control word register in the following
manner:-

70
Microprocessor Notes
 For 8255 For 8086
A1 A0 A2 A1 Selection
0 0 0 0 Port A
0 1 0 1 Port B
1 0 1 0 Port C
1 1 1 1 Control Word

3) Group A Control :-
The architecture of 8255 is divided in to two groups namely Group A and Group B.
Group A consists of Port A and Port Cupper i.e. PC7 – PC4.
It accepts control signals from the control word and forwards them to the respective
ports.
4) Group B Control :-
The architecture of 8255 is divided in to two groups namely Group A and Group B.
Group B consists of Port B and Port Clower i.e. PC3 – PC0.
It accepts control signals from the control word and forwards them to the respective
ports.
5) Port A, Port B, Port C :-
Port A and Port B can be used as 8-bit bi-directional ports.
Port C can be used as two 4-bit bi-directional ports.
Bit Set-Reset mode is only applicable to Port C.
These ports can be programmed to work in various modes and they are as follows:-
Ports Mode0 Mode1 Mode2
Port A Yes Yes Yes
Port B Yes Yes No
Port C Yes No No

71
Microprocessor Notes
 Control Word of 8255-I/O mode:-
To perform data transfer activities using these ports through 8255, 8255 need to be in
I/O mode.
The bit pattern for the control word in the I/O mode is as follows:-

Control Word of 8255-BSR mode:-

BSR mode stands for Bit Set-Reset mode and this mode is only applicable for Port C.
In this mode the bits of Port C can be individually set or Reset due to which we get 8
individually controllable lines which can be used while interfacing with devices like A to
D converter or a 7-segment display.
The bit pattern for the control word in the BSR mode is as follows:-

72
Microprocessor Notes
 Data Transfer Modes of 8255:-
For performing data transfer activities 8255 needs to be in I/O mode.
Data transfer can be done through 8255 in following modes:-
1) Mode0- Simple Bi-directional I/O mode.
2) Mode1- Handshake I/O mode.
3) Mode2- Bi-directional Handshake I/O mode.
Mode0- Simple Bi-directional I/O mode:-
In Mode0, Port A and Port B can be used as 8 bit bi-directional ports to perform data
transfer activities through 8255 while Port C can be as two 4 bit bi-directional ports and
these ports can be programmed Individually to work as input or output ports.
But in Mode0, no handshake signals are available due to which ports in this mode don’t
have interrupting capability, therefore slower peripheral devices cannot be interfaced.
Mode1- Handshake I/O mode:-
In Mode1, Port A and Port B can be used two 8-bit bi-directional ports which can be
programmed individually to work as an input or output port.
Port A and Port B uses 3 lines each of Port C to operate in Mode1 (i.e. for handshake signals)
due to which Port C cannot operate in Mode1.
In Mode1, the handshake signals are exchanged between the devices before the data
transfer takes place.
Slower peripheral devices can be interfaced in Mode1 due to its interrupting capability.
The handshake signals are different for input and output modes

73
Microprocessor Notes
 Mode1 Input Handshaking:-

The input handshaking takes place in the following manner:-

̅̅̅̅̅̅
𝑆𝑇𝐵(Strobe), 𝐼𝐵𝐹(Input Buffer Full) are signals used for input handshaking and INTR signal
is used to interrupt the 8086 microprocessor.
1) The peripheral devices places the data on the port bus and informs the 8255 by making
̅̅̅̅̅̅
𝑆𝑇𝐵 low.
2) The input port accepts the data and makes IBF high, indicating the peripheral device
that its port is full, so that the peripheral devices should not send more data and should
wait until the port is empty thereby preventing loss of data.
3) And 8255 interrupts the microprocessor through the INTR line provided that the INTE
flip-flop is set.
4) On receiving the interrupt, the microprocessor will issue the ̅̅̅̅ 𝑅𝐷 signal and will read the
data and in the above way the data byte is transferred to the microprocessor.

74
Microprocessor Notes
 5) After the data byte is transferred to the microprocessor, 8255 makes the IBF low
thereby indicating the peripheral device that it can send more data in the above
sequence.

Mode1- Output Handshaking :-

The output handshaking takes place in the following manner:-

̅̅̅̅̅̅
𝑂𝐵𝐹(Output Buffer Full) and ̅̅̅̅̅̅
𝐴𝐶𝐾 (Acknowledgement) are used as handshake signals and
INTR is used to interrupt the microprocessor.
1) The output port is empty that is indicated by a high on the INTR line, then the
microprocessor writes data on the output port by giving the ̅̅̅̅̅
𝑊𝑅 signal.
2) As soon as the 𝑊𝑅 ̅̅̅̅̅ operation is complete, the 8255 makes the INTR low, indicating the
microprocessor should wait and this prevents the microprocessor from sending more
data to 8255 thereby preventing the loss of data.
3) Now, 8255 also makes the ̅̅̅̅̅̅𝑂𝐵𝐹 low to indicate the peripheral device that the data is
available on the data bus and then the peripheral device performs the read operation
(i.e. accepts the data from the data bus) and acknowledges 8255 by making ̅̅̅̅̅̅
𝐴𝐶𝐾 low.

75
Microprocessor Notes
 4) In this way the microprocessor transfers the byte of data to the peripheral device
through 8255.
5) Now, ̅̅̅̅̅̅
𝑂𝐵𝐹 and ̅̅̅̅̅̅
𝐴𝐶𝐾 lines go high.
6) The INTR line also goes high and thereby indicating the microprocessor that an another
byte can be sent i.e. the output port is empty.
This process is repeated for further bytes.

Mode2- Bi-directional Handshake I/O :-

In mode2, there are five lines of Port C are used by Port A to perform bi-directional handshake
I/O.
Only Port A can operate in bi-directional handshake I/O.
Port B can either operate in Mode0 or Mode1.
If Port B is operating is in Mode1, then it will use 3 line of Port C, then entire lines of Port C will
be used for handshake signals.
OR
If Port B is operating in Mode0, then remaining 3 lines of Port C can be used in simple I/O
mode.
In Mode2, five handshake signals are used and they are viz… 𝑆𝑇𝐵 ̅̅̅̅̅̅ , IBF ,𝑂𝐵𝐹
̅̅̅̅̅̅ , 𝐴𝐶𝐾
̅̅̅̅̅̅ and INTR.
The handshaking process is similar to the Mode1.

76
Microprocessor Notes
 8036

Features of 8036:-
1) In 80386, the size of address bus is 32 bits, therefore the maximum
main memory can be accessed is 232 =4GB.
2) In 80386, the size of the data bus is 32 bits and the size of ALU is also
32 bits, therefore 80386 microprocessor is known as 32 bit
microprocessor and since the size of data bus is 32 bits the main
memory is divided in to four banks, each bank’s maximum size can be
1GB, therefore A2-A31 address lines are used to access these banks and
A0 and A1 are used to produces 4 bank signals viz… ̅̅̅̅̅
𝐵𝐸3 to ̅̅̅̅̅
𝐵𝐸0 .
3) 80386 supports address pipelining.
4) 80386 supports virtual memory and the total virtual memory that can
be accessed is 246 =64TB.
5) 80386 supports protection mechanism, in protected model 4 privilege
levels are used.
6) 80386 supports multitasking to give higher System performance.
7) 80386 has a 16 bit I/O address, therefore it can access total 216
=65536 ports.

77
Microprocessor Notes
 Pin diagram of 80386:-

The pin diagram of 80386 consists of the following parts:-

CLK2:-
The input clock to 80386 microprocessor is provided to through this pin.
RESET:-
80386 is reset through this pin and reset vector address for 80386 is FFFF
FFF0H.
̅̅̅̅̅̅̅̅̅̅
𝑹𝑬𝑨𝑫𝒀 :-
This pin is used to synchronize the microprocessor with slower peripheral devices.
If ̅̅̅̅̅̅̅̅̅̅
𝑅𝐸𝐴𝐷𝑌 =0, this indicates that the peripheral device is ready and hence the
microprocessor can continue.
̅̅̅̅̅̅̅̅̅̅ =1, this indicates that the peripheral device is not ready and hence the
If 𝑅𝐸𝐴𝐷𝑌
microprocessor needs to wait, so the microprocessor will insert the wait states
until the ̅̅̅̅̅̅̅̅̅̅
𝑅𝐸𝐴𝐷𝑌 =0.
NMI and INTR :-
These are 2 hardware pins available using which 80386 can be interrupted.
NMI is a non-maskable, edge triggered and vectored interrupt.
INTR is a maskable, level triggered and non-vectored interrupt.
HOLD and HLDA :-
Hold and HLDA pins are used to perform DMA (Direct Memory Access).
DMAC makes a request to became the bus master of system to the
microprocessor by making HOLD=1, in response to this request microprocessor
issues HLDA.
Now, DMAC is the bus master and after performing the bus operations,it will
return back the control of the system bus to the microprocessor by making
HOLD=0.

78
Microprocessor Notes
 PEREQ(PERIPHERAL EXTENSION REQUEST):
This pin is used by the co-processor 80387.
The physical address calculation and protection mechanism is performed by
the 80386co-processor and not by the 80387 co-processor, so whenever 80387 needs to
perform some data transfer operations using the system bus, it will make request the
microprocessor to initialize the bus operation i.e. perform all the physical address
calculations and place the physical address on the address bus by making PEREQ=1,
although the data will be transferred to 80387.
̅̅̅̅̅̅̅̅̅̅̅
𝑬𝑹𝑹𝑶𝑹 :-
This pin is used by the co-processor 80387.
Whenever 80387 will encounter any errors it will make 𝐸𝑅𝑅𝑂𝑅 ̅̅̅̅̅̅̅̅̅̅ =0, thereby informing
the microprocessor about these errors.
̅̅̅̅̅̅̅̅
𝑩𝑼𝑺𝒀 :-
This pin is used by the co-processor 80387.
Whenever the co-processor is busy, it makes ̅̅̅̅̅̅̅̅ 𝐵𝑈𝑆𝑌 =0.
Whenever the microprocessor encounters the WAIT instruction, it will check the ̅̅̅̅̅̅̅̅ 𝐵𝑈𝑆𝑌
pin and if the 𝐵𝑈𝑆𝑌 ̅̅̅̅̅̅̅̅ =0, indicating the co-processor is busy and will enter wait states
̅̅̅̅̅̅̅̅ =1.
until 𝐵𝑈𝑆𝑌
And if the ̅̅̅̅̅̅̅̅
𝐵𝑈𝑆𝑌 =1, the microprocessor will continue.
Address Bus:-
80386 has a 32 bit address bus.
And A2-A31 address lines are used to access the main memory and address lines A 0-A1
are used to produce the bank signals.
Data Bus:-
80386 has a 32 bit data bus.
̅̅̅̅̅̅̅̅
𝑩𝑺𝟏𝟔 :-
80386 can operate with 16 bit data bus also.
So this makes the process easier and cheaper to upgrade from 8086 to 80386.
So if ̅̅̅̅̅̅̅
𝐵𝑆16 =0, then the 16-bit data bus is available for use.
̅̅̅̅̅̅̅ =1, then the 32-bit data bus is available for use.
And if 𝐵𝑆16
𝑴\𝑰𝑶 ̅̅̅̅, 𝑫\𝑪 ̅ , 𝑾\𝑹 ̅ :-
These signals are used to perform control operations in the following manner:-

79
Microprocessor Notes
 ̅̅̅̅ 𝑫\𝑪
𝑴\𝑰𝑶 ̅ 𝑾\𝑹̅ Machine cycle
0 0 0 INTA
0 0 1 Inactive
0 1 0 I/O Read
0 1 1 I/O Write
1 0 0 Memory Read
1 0 1 Halt
1 1 0 Memory Read
1 1 1 Memory Write

̅̅̅̅̅̅̅̅ :-
𝑳𝑶𝑪𝑲
Whenever there is a LOCK prefix written in the instruction, it indicates the processor
that it should not release the control of system bus just after the machine cycle instead
it should release the control of the system bus after the execution of the current
instruction is completed.
̅̅̅̅̅̅̅̅ =0, it will inform the peripheral devices that it will not release the
So by making 𝐿𝑂𝐶𝐾
control of the system until the execution of the current instruction is completed.
̅̅̅̅̅̅
𝑨𝑫𝑺 :-
This signal is made low, when an address is placed on the address bus by the
microprocessor.
In a non-pipelined cycle, the ̅̅̅̅̅̅
𝐴𝐷𝑆 goes low during the T1 T-state of a machine cycle.
̅̅̅̅̅̅
In a pipelined cycle the 𝐴𝐷𝑆 goes low during T2 T-state of the previous machine cycle.
It is used to signal the external devices that the microprocessor has placed a new
address on the address bus.
̅̅̅̅
𝑵𝑨 :-
This signal is used to inform the microprocessor whether it should implement address
pipelining or not.
If ̅̅̅̅
𝑁𝐴 =0, address pipelining will be implemented.
̅̅̅̅ =1, address pipelining will not be implemented.
If 𝑁𝐴

80
Microprocessor Notes
 ARCHITECTURE OF 80386:-

The architecture of 80386 is divided in to following parts:-

1) Bus Unit:-
The data transfer to and from the microprocessor takes places using the bus unit
and the bus unit is connected to external memory and I/O devices and to fetch the
data and the instruction it needs the physical address and the physical address is
calculated by memory management unit (MMU) and passes this physical address to
the bus unit.
2) PreFetch Unit:-
80386 supports pipelining, so this unit is used to prefetch the next instructions and
store them in to the prefetch queue.
In 80386, the maximum size of an instruction can be 15 bytes, therefore this unit
fetches the next 16 bytes of the program and stores them in to the prefetch queue.
The prefetch unit gets refilled after every 4 bytes.
Whenever Execution unit and prefetch unit makes the request to the bus unit
simultaneously then higher priority will be given to the execution unit.
3) Decode Unit:-
This unit is used to decode (i.e. interpret) the instructions.
After decoding the instruction, the decoded instructions are stored in an instruction
queue.
And in an instruction queue at a time, next 3 decoded instructions are stored.

81
Microprocessor Notes
 4) Execution Unit:-
The main task of execution unit is to execute the instructions.
80386 has a 32-bit ALU, so this unit to perform operations on 32-bit operands in one
cycle.
In 80386, the ALU has a dedicated multiplier and a divider, this makes its ALU more
powerful.
5) Memory Unit:-
Memory Unit comprises of segment unit and page unit.
This unit is used to convert the virtual address in to 32 bit physical address.
Segmentation is compulsory and the virtual address is an input to segment unit and
after performing segmentation this virtual address is converted in to 32- bit linear
address and paging is optional if paging is not performed then this 32-bit linear
address is treated as 32-bit physical address.
And if paging is performed then the 32-bit linear address is an input to page unit and
after performing paging the 32-bit linear address is converted in to 32-bit physical
address.

82
Microprocessor Notes
 Flags of 80386:-

There are four new flags are added and remaining flags are same as of 8086 flags
and new flags are explained as follows:-
VM- Virtual 8086 Mode:-
80386 can operate in virtual 8086 mode to run the 8086 programs in the faster
environment of the 80386 and this can be done by making VM=1.
And by making VM=0, the 80386 enters back in the protected mode.
RF- Resume Flag:-
Resume flag is used during debugging, a debug fault in the next instruction(I.e.
resuming to the same instruction instead to next instruction) can occur and by
making RF=1, this fault can be ignored and this flag automatically resets after the
next instruction.
NT- Nested Task:-
This flag is used to indicate that the current program is nested I.e. it is invoked by
another program and after executing the current program it needs to return back to
the program because of which it got invoked.
If NT=1, then the current task is nested and its TSS has a valid back link to the TSS of
the previous task.
This flag is automatically set whenever a Nested task is initiated and it can only be
reset by the software.
I/O Privilege level:-
These bits are used to assign I/O privilege level.
80386 microprocessor has 4 level privilege levels, where privilege level=0 is the
highest and the privilege level=3 is the lowest.

83
Microprocessor Notes
 Real Mode of 80386:-
In real mode, the 80386 microprocessor works as a fast 8086 machine and all
registers are like in 8086 microprocessor even the maximum main memory that can
be accessed is 1MB.
In this mode the physical address is calculated using following formula:-
PA=segment address*10H + offset address.
This mode is basically used to run the BIOS on reset.
Once the required registers are initialized, 80386 can enter in the protected mode
by making PE bit=1 in CR0.
Real mode consists of the following:-
There are six 16-bit segment register are available and they are viz…
CS,SS,DS,ES,FS,GS.
There are five 16-bit offset register are available and they are viz…
IP, SP, BP, SI and DI.
There are four 16-bit general purpose registers available and they are viz…
AX, BX, CX and DX.
Only the lower 12 bits of the flag register is available.
Only PE bit in CR0 register is available in the real mode and remaining bits of CR0
and remaining control registers are not available.
In real mode, the size of main memory can be up to 1MB only and address ranges
from 00000H to FFFFFH.
In real mode, the size of I\O address is 16 bits and therefore the total number of
ports can be accessed =65536.

84
Microprocessor Notes
 Protected Mode of 80386:-
80386 supports the protection mechanism and in protected model four privilege
levels are available where privilege level=0 is the highest and privilege level=3 is the
lowest.

Level0:-
Privilege level=0 is the highest privilege level and it is assigned to the kernel of the
os.
Any program at privilege level=0 can access any data at any of the privilege but the
data present at this level can be accessed only by the programs present at this level
and not by the programs present at remaining privilege levels.
Level1:-
It is the 2nd most privileged level.
This level is assigned to the system services.
Any program present at this level can access the any data which is present at this
level or lower than this level but not the data present at privilege level0.
Level2:-
It is the 3rd most privileged level.
This level is assigned to os extensions.
Any program present at this level can access the any data which is present at this
level or lower than this level but not the data present at privilege level0 and
privilege level1.
Level3:-
It is the least privileged levels.
This level is assigned to the user applications and programs.
The programs present at this level can access any data from the programs present at
this level and not at any other level.

85
Microprocessor Notes
 86
Microprocessor Notes
 Control Registers of 80386:-

In 8086, there are four control registers available and they are explained as follows:-
Control Register 0:-

The various bits of CR0 are explained as follows:-

PG (Paging Enable):-
In 80386, paging is optional, therefore this pin is used to indicate whether paging will be
performed or not.
If PG=1, then paging will be performed and if PG=0, then the paging will not be
performed.
ET (Extension Type):-
In 80386, Extension Type is used to indicate the type of the Math Co-processor interfaced
with 80386.
If ET=1, then 80387 Math Co-processor is interfaced.
If ET=0, then 80287 Math Co-processor is interfaced.
TS (Task Switched):-
80386 supports multitasking and TS bit is used to indicate whether task switch is
performed or not.
If TS=1, then Task switch will be performed.
If TS=0, then Task switch will not be performed.
EM (Emulate Co-processor):-
If co-processor is not connected to the 80386 so the EM bit will always be 1.
If EM=1, then this will indicate that the co-processor is not present in the system and
microprocessor will emulate the co-processor (i.e. will execute the instructions of the co-
processor).
If EM=0, then the microprocessor will not emulate the Co-processor.
MP (Math Co-processor Present):-
If MP=1, then the Math Co-processor is present in the system.
If MP=0, then the Math Co-processor is not present in the system.

87
Microprocessor Notes
 PE (Protection Enable):-
80386 enters in the protected mode by making PE bit =1.
On reset, by default this bit is 0.
Control Register 1:-
Not used.
Control Register 2:-
This is a 32 bit register will stores the 32 bit linear address that caused the last page fault.
Control Register 3:-
This is used to store the upper 20 bits of the starting address of the page directory and
the reason of storing only upper 20 bits is that the page directory is of 4KB and is stored
at 4KB aligned location so the last 12 bits will be assumed to be 0 of the starting address
of the page directory.

88
Microprocessor Notes
 Address Translation Mechanism in Protected Mode:-
1) In 80386, the maximum physical memory (i.e. main memory) that can be accessed is
232 =4GB.
2) Virtual memory is the total space that can be accessed by the processor using its
Registers.
3) Virtual address is made up of 16 bit segment address and a 32 bit offset address,
therefore the virtual address is of 48 bits.
4) Here the segment register is used as a selector which selects a descriptor for the
segment.
5) The size of the selector is 16 bits but two bits are used to give the privilege levels,
which is used for the protection mechanism.

6) Each selector value corresponds to a different segment, hence there can be max 2 14
segments.
7) The total virtual memory that can be accessed 246 =64TB.
8) The total descriptors are 16k which can be stored either in LDT (Local Descriptor
Table) or in GDT (Global Descriptor Table).
9) So basically there are 8k descriptors in GDT and 8K descriptors in LDT.
10) Out of 14 bits of the selector, 1 bit is reserved for TI, which is used to identify
whether the descriptor is present in LDT or in GDT.

89
Microprocessor Notes
 11) If TI=1, then the descriptor is present in LDT and if TI=0, then the descriptor is present
in GDT.
12) And 13 bit selector is enough to select a descriptor from GDT/LDT.
13) The virtual address goes as an input to the segment unit and segmentation is
compulsory and after performing segmentation the 48 bit virtual address is converted
in to 32-bit linear address.
14) And paging is optional, if paging is not being performed then this 32 bit linear address
is treated as 32 bit physical address.
15) And if paging is being performed then this 32 bit linear address goes as an input to
the page unit and after performing paging this 32 bit linear address is converted in to
32 bit physical address.

90
Microprocessor Notes
 Segment Translation:-

1) In 80386, the size of virtual address is 48 bits (i.e. 16 bit segment address and 32
bit offset address).
2) Out of 16 bits of segment address, 2 bits are used for protection mechanism and 1
bit is reserved for TI.
3) So remaining 13 bits of segment address is used as selector to select a descriptor
from LDT/GDT, depending upon the TI bit, if TI=1, then LDT and if TI=0, then GDT.
4) The size of each descriptor is of 8 bytes.
5) The descriptor is copied into an on chip segment descriptor cache.
6) There is a P bit in the descriptor which is used to indicate whether the segment is
present in the physical memory or not.
If P bit =1, then the segment is present in the physical memory and the base
address in the descriptor gives the starting address of the segment.

91
Microprocessor Notes
 If P bit =0, then the segment is not present is not present in the physical memory
and the base address in the descriptor does not gives the starting address of the
segment.
And then the segment will be copied from virtual memory in to the physical
memory and the base address in the descriptor will be updated for the further
use.
7) Now, the offset address of 32 bits will be added on the base address to get the 32
bit linear address of the desired location in the segment.
8) Before giving the access to the desired location a series of protection checks are
performed based on the information given by the access rights in the descriptor,
such as limit not exceeded, type of segment, type of access, privilege level etc.
9) If the checks are valid, then the access to the desired location is given else a
general protection fault occurs.
10) If paging is not implemented, then the 32 bit linear address is treated as 32 bit
physical address.

92
Microprocessor Notes
 Basic structure of a descriptor:-

93
Microprocessor Notes
PAGE Translation:-

1. The virtual memory is divided in to equal size blocks of 4KB called pages.
2. The physical memory is also divided in to equal size blocks of 4KB called page frames.
3. The maximum size of physical memory can be 4GB i.e. 232 and size of each frame is 4KB
i.e. 212, therefore the physical memory can be divided in to 1M such page frames.
4. Now, there is a need to map which page is stored in which page frame in the physical
memory since any page from virtual memory can be loaded in to any available page
frame of main memory, so for the above reason there is a need of a page table.

94
Microprocessor Notes
 5. Now, instead of having a single page table containing 1M entries upright, since it will
make the search process very slow, so we should have 1K page tables each containing
1K entries.
6. So this will help to make the search process little faster and each entry in the page table
will be called as PTE (Page Table entry) and each entry will be of 4 bytes and therefore
size of each page table will be of 4KB and each page table will be stored at a 4KB aligned
location.
7. Each PTE will give following information:-
Upper 20 bits will give the starting address of the page frame and the last 12 bits will be
0 as explained earlier.
D: Dirty Bit indicates whether the page has been modified or not.
If D=1, page is modified.
If D=0, page is not modified.
A: Accessed bit will indicate whether the page has been accessed or not.
If A=1, page is accessed.
If A=0, page is not accessed.
This bit is used by page replacement algorithms.
U/S: User or Supervisor.
R/W: Read or Read and write.
P: Present bit will indicate whether the page is present in the physical memory or not.
If P=1, the page is present in the physical memory and the address indicated by the
upper 20 bits is valid.
If p=0, the page is not present in the physical memory and the address indicated by the
upper 20 bits is invalid.
(And if the page is not present in the physical memory it is termed as a page fault or
page miss and the memory management unit will copy the desired page from the virtual
memory in to available page frame in physical memory using page replacement
algorithms).
8. Now, we also need to keep the track of which page table contains which set of entries
and for that a page directory is required.
9. The total number of entries in the page directory will be 1k and each entry will be of 4
bytes and that entry will be called as PDE (Page Directory Entry), therefore the size of
page directory will be 4KB and It will be stored at a 4KB aligned location.
10. The base address (i.e. starting address) of the page directory will be given by PDBR (Page
Directory Base Register) whose upper 20 bits are stored in CR3 register and last 12 bits
will be 0 since the size of page directory is 4KB and it is stored at a 4KB aligned location.
11. Each PDE gives following information:-
Upper 20 bits gives the starting address of the corresponding table, last 12 bits of the
address will be 0 as explained earlier.
Remaining bits are explained earlier.
12. The 32 bit linear address is divided in to 3 parts and they are as follows:-
1. Upper 10 bits are used to select the desired PDE from 1K PDE’s present in the
page directory.

95
Microprocessor Notes
 2. The next 10 bits are used to select the desired PTE from 1k PTE’s present in the
corresponding page table.
3. The last 12 bits are used as a offset to select a desired location from in the 4KB
page.
13. In this way, the paging is implemented in 80386 and after performing we convert the 32
bit linear address in to 32 bit physical address.

96
Microprocessor Notes
 Pentium
Salient features of Pentium:-
1. Pentium processor has a 32-bit address bus.
This implies it can access maximum main memory of 4GB (i.e. 232 =4GB).
Therefore the address range of main memory is from 00000000H to FFFFFFFFH.

2. Pentium processor has a 64-bit data bus and 32-bit ALU.

3. Pentium processor has a 2 way super scalar architecture i.e. Pentium has two 32 bit ALUs and two full
pipes for execution of two instructions at the same time.

4. Pentium processor performs Pipelining.

Pentium processor performs two types of pipelining
1. Five stage Integer pipeline.
2. Eight stage Floating point instruction pipeline.

5. Pentium processor has the ability to perform branch prediction logic.

6. Pentium processor has on-chip instruction and data L1 cache i.e. it has two separate 8KB caches on chip-
one for instructions and other for data, which allows it to fetch data and instructions from the cache
simultaneously.

97
Microprocessor Notes
 Pentium processor architecture:-

98
Microprocessor Notes
  Pentium has two-way superscalar architecture i.e. it has two 32-bit ALUs and two full pipes for
execution of two instructions simultaneously.
 The architecture has two integer pipelines namely U pipe and V pipe respectively and these
pipes are responsible for executing 80X86 instructions.
 The architecture also has a floating point unit which is responsible for executing floating point
instructions that were previously handled by external 80X87 math coprocessors.
 The simultaneous execution of two instructions is possible if all the conditions of instruction
pairing algorithm are satisfied.
 Pentium processor has a 32-bit address bus and a 64-bit data bus.
 Pentium processor has a 32-bit ALU, so the size of operands is 32-bits but it has a 64-bit data bus
so that data transfer requirements of both pipes can be met simultaneously.
 An 8KB instruction cache is used to provide quick access to frequently used instructions.
 If the instruction is not found in the instruction cache, than the instruction is read or fetched
from main memory with the help of system bus and is placed in to the instruction cache for
further references.
 The Branch Target Buffer (BTB) and prefetch unit work together with the instruction cache to
fetch instructions as fast as possible.
 Pentium processor has two 32 bytes prefetch queues, the size of a prefetch queue is 32 bytes
because the size of an instruction in Pentium is 15 bytes and due to two way superscalar
architecture, two instructions may be required simultaneously.
 The bus connection from L1 code cache to prefetch unit is 256 bits i.e. 32 bytes, so 32 bytes can
be transferred in one clock cycle from the L1 code cache to the prefetch queue.
 A separate 8KB data cache stores a copy of the most frequently accessed memory operands for
fast access.
 The data and instruction caches may both be enabled, with hardware or software. Both also
employ the use of a translation look aside buffer for address translation.
 Pentium processor uses a technique of branch prediction to reduce the penalty due to a branch
on pipelining performance. To carry out branch prediction it uses BTB, which stores the history
of previously executed branch instructions and their behavior. This helps in making a prediction
whether the branch will be taken or not and accordingly instructions from branch address or
sequentially next address are fetched and provided to the pipes.
 While fetching, the first instruction is provided to the U pipe and the second instruction is
provided to the V pipe.
 If the U-pipe instruction stalls, the V-pipe one also stalls but if the V-pipe one stalls then the U-
pipe instruction is allowed to continue.

99
Microprocessor Notes
Integer Pipeline Stages:-
The Pentium's basic integer pipeline is five stages long, with the stages broken down as follows:
1. Pre-fetch/Fetch :
2. Decode1 :
3. Decode2 :
4. Execute :
5. Write-back :

The integer pipeline stages are as follows:

1. Prefetch(PF) :
– Instructions are prefetched from the on-chip instruction cache
2. Decode1(D1):
– Two parallel decoders attempt to decode and issue the next two sequential instructions
– It decodes the instruction to generate a control word
– A single control word causes direct execution of an instruction
– Complex instructions require microcoded control sequencing
3. Decode2(D2):
– Decodes the control word
– Address of memory resident operands are calculated
4. Execute (EX):
– The instruction is executed in ALU
– Data cache is accessed at this stage
– For both ALU and data cache access requires more than one clock.
5. Writeback(WB):
– The CPU stores the result and updates the flags

100
Microprocessor Notes
Instruction pairing algorithm:-
Consider two consecutive instructions I1 and I2, decoded by the microprocessor,

If all the following are true:

I1 is a simple instruction.

I2 is a simple instruction.

I1 is not a jump instruction.

Destination of I1 not the same as Source of I2.

Destination of I1 not the same as Destination of I2.

Then

Issue I1 to U-pipe and I2 to V-pipe.

Else

Issue I1 to U-pipe.

Consider two consecutive instructions I1 and I2:-

If they are pairable, then I1 is issued to U-pipe and I2 is issued to V-pipe.

If the two instructions are not pairable, the I2 instruction in the V pipeline’s D1 stage is deleted and shifted to D1
stage of the U pipeline when I1 is moved to the D2 stage of U pipeline.

101
Microprocessor Notes
Floating point pipeline stage:-
The floating point pipeline has 8 stages as follows:
1. Prefetch(PF) :
– Instructions are prefetched from the on-chip instruction cache
2. Instruction Decode(D1):
– Two parallel decoders attempt to decode and issue the next two sequential instructions
– It decodes the instruction to generate a control word
– A single control word causes direct execution of an instruction
– Complex instructions require microcoded control sequencing
3. Address Generate (D2):
– Decodes the control word
– Address of memory resident operands are calculated
4. Memory and Register Read (Execution Stage) (EX):
– Register read, memory read or memory write performed as required by the instruction to access an
operand.
5. Floating Point Execution Stage 1(X1):
– Information from register or memory is written into FP register.
– Data is converted to floating point format before being loaded into the floating point unit
6. Floating Point Execution Stage 2(X2):
– Floating point operation performed within floating point unit.
7. Write FP Result (WF):
– Floating point results are rounded and the result is written to the target floating point register.
8. Error Reporting(ER)
– If an error is detected, an error reporting stage is entered where the error is reported and FPU status
word is updated

102
Microprocessor Notes
Branch Prediction Logic:-

The Pentium processor has branch prediction logic, allowing it to avoid pipeline stalls if it correctly
predicts whether or not the branch will be taken when the branch instruction is executed.
However, if the branch prediction is not correct a penalty of three cycles is incurred if the branch was
executed in the U pipeline, and four cycles if it was executed in the V pipeline.
The prediction mechanism is implemented using a four way, set associative cache with 256 entries. This
is referred to as the Branch Target Buffer (BTB).
The directory entry for each line contains the following information :
· A valid bit that indicates if the entry is in use.
· History bits that track how often the branch has been taken each time it has entered the pipeline
before.
· The source memory address that the instruction was fetched from for identification.
The BTB is a look-aside cache that sits off to the side of D1 stages of the two pipelines and monitors for
branch instructions.
During D1 stage, when an instruction is decoded and identified as a branch instruction, the address of
the instruction is searched in the BTB for a previous history.
If no history exists, then prediction is made that the branch will not be taken.
If there is a history (BTB hit), then prediction is made as follows:-
If the history bits are 00 or 01(strongly not taken or weakly not taken), then the prediction is that the
branch will not taken.
If the history bits are 10 or 11 (strongly taken or weakly taken) , then the prediction is that the branch
will be taken.
If the branch is predicted to be taken, then the active queue is no longer used. Instead, the prefetcher
starts fetching instructions from the branch address and stores them in to the second queue which now
becomes the active queue. This queue now starts feeding instructions in to the two pipes.
If branch is predicted to be not taken, then nothing changes, and the active queue remains active and
instructions are fetched from the sequentially next locations.

103
Microprocessor Notes
 When the instruction reaches the execution stage, the branch will either be taken or not, if the branch is
taken then the next instruction to be executed should be fetched from the branch target address and if
the branch is not taken then the next instruction to be executed should be the one fetched from the
next sequential memory address after the branch instruction.

If a Branch instruction is encountered for the first time and its entry is not present in BTB, then the
prediction is made that the branch will not be taken and at the execution stage if the branch is actually
not taken, then its entry is not made in BTB and if the branch is actually taken, then its entry is made in
the BTB and its history bits are set to 11 (i.e. strongly taken).

When the branch is taken for the first time, an entry is made in BTB by storing the address of the branch
instruction and history bits are set to strongly taken (i.e. 11) and when the same branch instruction is
encountered the prediction will be made that the branch will be taken and at the execution stage if
branch is taken the history bits will be updated to 11 (i.e. strongly taken) and if the branch is not taken
then the history bits will be updated to 10(i.e. weakly taken) and when again the same branch
instruction is encountered, in its BTB entry history bits will be 10(i.e. weakly taken), so the prediction
will be made that the branch will be taken and at the execution stage if the branch is taken, then the
history bits in BTB entry will be updated to 11 (i.e. strongly taken) and if the branch is not taken
then the history bits in BTB entry will be updated to 01 (i.e. weakly not taken).

The history bits can indicate one of the four possible states:-

History Bits Resulting Prediction Made If Actually Taken If Actually Not

Description Taken

00 Strongly Not Taken Branch Will Not Be Upgrades to Remains Strongly

Taken Weakly Not Taken Not Taken

01 Weakly Not Taken Branch Will Not Be Upgrades to Downgrades to

Taken Weakly Taken Strongly Not Taken

10 Weakly Taken Branch Will Be Upgrades to Downgrades to

Taken Strongly Taken Weakly Not Taken

11 Strongly Taken Branch Will Be Remains Strongly Downgrades to

Taken Taken Weakly Taken

104
Microprocessor Notes
MESI PROTOCOL:-
MESI:
Acronym for Modified, Exclusive, Shared and Invalid. This is a protocol to ensure
cache coherence on the Pentium processor. A protocol is necessary, since more than
one processor has a copy of common data with the right to modify. Through the MESI
protocol data coherence is ensured no matter which of the processors performs writes.

Modified:
State in the MESI protocol. The M state implies that the cache line found by a write hit
was exclusive, and that the current processor has modified the data. The modified
state expresses: Currently not shared, exclusively owned data have been modified. In
a UP system, this is generally expressed by the dirty bit.

Dirty Bit:
State bit associated with a cache line. This bit expresses whether a write hit has
occurred on a system applying write back. Synonym:

Exclusive:
State in the MESI protocol. The E state indicates that the current cache is not aware of
any other cache sharing the same information, and that the line is unmodified. It
allows that in the future another line will contain the same information, in which case
the E state must be changed. Also it is possible that a higher-level cache (L1 for
example viewed from an L2) may actually have a shared copy of the line in exclusive
state; however that level of sharing is transparent to other potentially sharing agents
outside the current processor.

Shared:
State in the MESI protocol. The S state expresses that the hit line is present in more
than one cache. Moreover, the current cache (with the shared state) has not modified
the line after stream-in. Another cache of the same processor may be such a sharing
agent. For example, in a two level cache, the L2 cache will hold all data present in the
L1 cache. Similarly, another processor’s L2 cache may share data with the current
processor’s L2 cache.

Invalid:
State in the MESI protocol. This I state (possibly implemented via special purpose bit)
indicates that the associated cache line is invalid, and consequently holds no valid
data. This invalid (I) state is always set after a system reset.

105
Microprocessor Notes
 106
Microprocessor Notes