Received: 11 June 2020

DOI: 10.1049/cds2.12014
- -Revised: 16 September 2020

O R I G I N A L R E S E A R C H PA P E R
Accepted: 5 October 2020

- IET Circuits, Devices & Systems

A fully differential switched‐capacitor integrator based

programmable resolution hybrid ADC architecture for
biomedical applications

Sreenivasulu Polineni | Rekha S. | M. S. Bhat

Department of ECE, National Institute of Abstract

Technology Karnataka, Surathkal, Karnataka, India
A novel switched‐capacitor integrator based programmable resolution analog to digital
converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be
Correspondence
Sreenivasulu Polineni, Department of ECE,
switched between successive approximation register (SAR) and delta‐sigma modulator
National Institute of Technology Karnataka, (DSM) mode in 8‐bit to 15‐bit resolution. A mathematical relationship showing the effect
Surathkal, Karnataka 575025, India. of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode
Email: [email protected]
operational transconductance amplifier (OTA) operating in a weak inversion region is
designed using gm/ID technique with programmable unity gain bandwidth and slew rate.
Funding information
MeitY, Government of India
The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in
UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC
resolution is programmable from 8‐bit to 15‐bit using a 3‐bit control bus (res[2 : 0]). The
hybrid ADC operates in SAR mode from 8‐bit to 11‐bit resolutions and as the first‐order
DSM with a multi‐bit quantizer in 12‐bit to 15‐bit resolutions. The dynamic performance
of the proposed ADC is verified through post‐layout simulations with a supply voltage of
1.8 V. It exhibits a signal‐to‐noise and distortion ratio of 45–86 dB and consumes a power
of 0.86–98 μW across target resolutions (8–15 bits).

1 | INTRODUCTION The advancements in healthcare system make humans life

better day by day. Biomedical devices [1] help to monitor the
The 21st century is marked as digital era by electronic industries patient's body and provide support systems round the clock
which brought revolution in signal processing. Modern elec- without causing much inconvenience on their day‐to‐day life. It
tronic systems employ sophisticated functional blocks which not only reduces the length of hospital stay for post‐operative
impact power consumption, cost, performance and reliability care but also offers superior monitoring and reporting process.
of the system. Digital signal processor (DSP) is able to Moreover, the pre‐diagnosis of functional disorders and deadly
implement complex algorithms and functions with high diseases by these devices might save the life and also reduces
computational accuracy and power. Along with this, improved the cost of medical care to a greater extent. In many cases, to
noise margin, error detection and correction codes made the monitor the biological signals, a wireless body sensor network
transmission and storage of digital signals less prone to noise. (WBSN) [2] with multiple nodes is used. To extend battery life,
Hence the analog circuit techniques in many applications were the power consumed by these nodes should be as low as
replaced by reliable, cost‐effective, fast and flexible digital possible. In each sensor node, ADC is a critical block that
technologies. Thus, there is an extensive need for analog to interfaces physical world with DSP block. Literature study
digital converters (ADCs) and digital to analog converters suggests that successive approximation register (SAR) ADC is
(DACs) to avail benefits of digital signal processing as the real‐ the most suitable one by virtue of its characteristics like con-
world signals are analogue. Of late, design of ADCs has version accuracy, ultra‐low‐power consumption, simple design
become critical, especially with technology scaling because the and technology scaling amenability [3,4]. Typically, SAR ADC
circuit noise is not decreasing as much as the technology/ [5] is implemented with a binary‐weighted capacitor DAC,
supply voltage does. dynamic comparator and digital logic. The number of

-
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properly cited.
© 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.

IET Circuits Devices Syst. 2021;15:141–155. wileyonlinelibrary.com/journal/cds2 141

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- POLINENI ET AL.

Vin
S/H
SIPO

fs
N-bit
DAC

(a)

Vin
S/H
SIPO

fs
FIGURE 1 Segment depiction of an electrocardiogram signal [6]
1 N-bit

reset @fs 1- z-1

capacitors used in the binary‐weighted DAC is exponentially
(N+1)fs
proportional to the resolution (N bits). The area, energy con-
sumption and distortion due to mismatch are directly related to (b)
the number of capacitors used in DAC. Therefore, there are
numerous switching techniques reported in literature to reduce F I G U R E 2 (a) Successive approximation register analog to digital
the number of capacitors used in DAC circuit. Biomedical converter (SAR ADC) block diagram. (b) SAR ADC with feedback
signals such as the electroencephalogram (EEG), electrocar- integrator digital to analog converter. SIPO, serial‐in–parallel‐out
diogram (ECG), breathing quality, measures of blood param-
eters such as oxygenation, glucose, cholesterol, c‐reactive
protein (CRP), erythrocyte sedimentation rate (ESR), platelet
count, etc. have varying dynamic range and bandwidth. In Vin 1 N-bit
S/H 1-z-1 ADC
addition, within a given application like ECG, to accomplish
low‐ and high‐resolution tasks at different intervals as shown fs fs
in Figure 1, a variable‐resolution ADC may be optimal. Hence,
a power‐efficient and fully programmable resolution ADC can DAC
substantially reduce the size and cost of the WBSN. In [7–16],
adaptive‐resolution ADC architectures are presented for (a)
implantable sensors. In all these papers, SAR ADC is designed
S/H N-bit
with binary‐weighted capacitive DAC using different switching

SIPO
Vin 1 fs
S/H
methods. 1- z-1 1
reset @fs 1- z-1

The switched‐capacitor integrator SAR ADC [7] is imple- fs fs

(N+1)fs

mented using operational transconductance amplifier (OTA)

with programmable unity gain bandwidth (UGB) and slew rate, DAC
dynamic comparator, capacitors, switches and control logic.
(b)
The advantages of switched‐capacitor integrator based SAR
ADC over conventional SAR ADC are summarized as follows: Vin 1
S/H
SIPO

the number of unit capacitors used in the binary‐weighted 1- z-1

DAC is exponentially proportional to the resolution (N bits). N-bit
The area and energy consumption are directly related to the fs fs
number of capacitors and the value of unit capacitor used in
the DAC. One way to reduce the energy consumption is by 1
reducing the unit capacitance. The large number of unit ca- 1- z-1
pacitors with the smaller unit capacitance makes the effect of (N+1)fs
capacitor mismatch more severe. Also, the binary‐weighted
(c)
capacitive SAR requires large number of switches which
introduce more distortion. Whereas the differential switched‐
F I G U R E 3 (a) First‐order multi‐bit delta‐sigma modulator (DSM)
capacitor integrator based SAR ADC requires 6 capacitors and block diagram. (b) First‐order DSM with successive approximation register
16 switches only. Also, the resolution of ADC can be pro- (SAR) quantizer. (c) Reduced block of first‐order DSM with SAR quantizer.
grammable without much modifications to the architecture. DAC, digital to analog converter. SIPO, serial‐in–parallel‐out
POLINENI ET AL.
- 143

S1
Vcm Vcm

S7 S5
C5 SAR Resolution
S9 S3 Controller
−

Switch_Control_logic
Vip Vop +
res[2:0]
v1 C1 + Dout
S10 C2 S4 −
v2 - S1:16
Vim + Vom Programmable
clk Counter
C6
S8 S6
EoC
Vcm Vcm SIPO
S13 S2 S15 clk
v1 v1 N-bit

clk
S11 S12
Vdd S14 S16
C3 v2 C4 v2

(a)
clk
sampling_clk
comparison_clk
vip
v1
v2 vim

vc3 Vdd
Vcm
vc4
0

vop
vom
Doutp
Doutm
1 1 0 0 1 0 1 1 0 0
S9 S10 S11 S12
S3 S4 S7 S8
S 5 S6
S13 S16
S14 S15

(b)

F I G U R E 4 Proposed programmable resolution analog to digital converter architecture: (a) circuit diagram, (b) timing waveform for first‐order delta‐sigma
modulator with successive approximation register quantizer

Another advantage of switched‐capacitor integrator based SAR summarizes the performance parameters and compares with
ADC is that the reference voltages are sampled on the ca- state‐of‐the‐art designs. The paper is concluded with
pacitors C3 and C4 in Figure 4a at the beginning of conversion. Section 6.
This makes the switched‐capacitor integrator based SAR ADC
less prone to any signal‐dependent inaccuracies associated with
the reference voltage compared to binary‐weighted SAR ADC. 2 | OPERATING PRINCIPLE OF
This paper presents a hybrid ADC with programmable PROPOSED HYBRID ADC
resolution from 8 to 15 bits for biomedical applications. This
proposed ADC operates in two modes of operation: (1) SAR The conventional SAR ADC is implemented using a sample
ADC mode for lower resolution of 8–11 bits, and (2) delta and hold (S/H), comparator, serial‐in–parallel‐out (SIPO)
sigma modulator (DSM) with multi‐bit quantizer for higher register and N‐bit feedback DAC blocks as shown in Figure 2a.
resolution of 12–15 bits. The organization of this paper is as Here, fs is the sampling frequency and N is the resolution of
follows. Section 2 explains the working principle and tech- ADC. The feedback DAC is implemented with a 1‐bit DAC
niques used in the proposed programmable resolution ADC. and discrete‐time integrator as shown in Figure 2b. The
Section 3 discusses the impact of circuit non‐idealities on discrete‐time integrator accumulates the scaled reference
proposed ADC. Section 4 presents the design of building voltage after every comparison cycle from 1‐bit DAC and re-
blocks such as OTA with programmable slew rate and UGB, freshes in each sampling phase. Thus, it fulfils the functionality
dynamic comparator and digital control logic. Section 5 of an equivalent N‐bit DAC.
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- POLINENI ET AL.

FIGURE 5 Flow chart of programmable resolution analog to digital converter. OSR, oversampling ratio

Figure 3a shows the block diagram of first‐order multi‐bit implemented with two switches S1 and S2. The feedback 1‐bit
DSM ADC which can achieve high resolutions with over- DAC is implemented using capacitors C1, C2, C3, C4 and
sampling and noise‐shaping technique. The multi‐bit ADC in switches S11:16. Figure 4b shows the timing waveform of the
the loop can be realized with a SAR quantizer which is proposed hybrid ADC in the first‐order DSM with SAR
shown in Figure 2b. In the block diagram shown in quantizer mode. The nodes v1 and v2 are connected to the
Figure 3b, there are two DACs, one operates at frequency Nfs left of capacitors C1 and C2, respectively. Conversion pro-
used for SAR operation and another is an N‐bit DAC which cedure is depicted with a flow chart as shown in Figure 5.
operates at a frequency of fs and used for noise‐shaping The proposed hybrid ADC configured as a switched‐capac-
purpose. This N‐bit DAC can be implemented with a itor integrator based SAR ADC from 8‐bit to 11‐bit resolu-
discrete‐time integrator and 1‐bit DAC as shown in tions and a first‐order multi‐bit DSM from 12‐bit to 15‐bit
Figure 2b. Since both the paths are using the same DAC resolutions. The control bus res[2 : 0] is used to select the
structure, they can be reduced to one path. Further, by resolution of ADC. The signal‐to‐noise ratio (SNR) for first‐
shifting the summing point towards the comparator, the order DSM with multi‐bit quantizer is given by
integrator block operated at frequency fs added into both
forward and feedback paths. The series connection of the � 2�
π
integrator block and reset@fs blocks cancel with each other SNRdB ¼ 6:02N þ 1:76 þ 30log10 ðOSRÞ 10log10
in the feedback path. Therefore, the reduced block diagram 3
of first‐order DSM with SAR quantizer can be redrawn as
shown in Figure 3c. Hence the only difference between SAR The resolution (N) for multi‐bit DSM and OSR is chosen
quantizer of Figure 2b and the first‐order DSM with SAR to target the corresponding SNR for each resolution from 12‐
quantizer of Figure 3c is the reset@fs block. Therefore, it is bit to 15‐ bit. For example, res[2 : 0] ¼ ‘100’ configures the
possible to switch between SAR quantizer and first‐order proposed ADC as the first‐order DSM with 7‐bit SAR quan-
multi‐bit DSM by controlling this reset@fs block. Further, the tizer and an OSR of 16 which targets 75 dB SNR. The sam-
resolution of SAR quantizer is programmable by controlling pling and clock frequency, targeted SNR, SAR quantizer
the N value, and the DSM resolution is controlled with an resolution, and OSR for all modes are calculated according to
oversampling ratio (OSR). the resolution mode chosen by res[2 : 0].
Figure 4a shows circuit level implementation of the The conversion process starts when reset is ‘high’. The
proposed 8‐bit to 15‐bit programmable resolution hybrid total conversion can be divided into four phases as follows:
ADC which is controlled by a 3‐bit input bus res[2 : 0]. The Sampling phase: In this phase, switches S5, S6, S9, S10, S11
discrete‐time integrator is implemented with a switched‐ and S12 are ‘ON’. Capacitors C1 and C2 sample the differ-
capacitor integrator with fully differential OTA; capacitors ential input signals Vip and Vim through S9, S5 and S10, S6
C1, C2, C5, C6; and switches S3:8. The reset@fs block is switches, respectively. Also, capacitor C3 samples the supply
POLINENI ET AL.
- 145

voltage Vdd through switch S11 and capacitor C4 discharges variation in system characteristics can be estimated [17]. In
to ground through switch S12. In 8‐bit to 11‐bit resolution fully differential circuits and charge sharing circuits, the
modes, switches S1 and S2 are ‘ON’ thereby resetting the relative values of capacitors are more important than absolute
capacitors C5 and C6. This phase exists for a positive half values. Therefore, the deviation or mismatch between the
cycle of the clock after the end of conversion (EoC). Further, components is calculated as the normalized deviation from
to avoid the distortion due to charge injection, bootstrapped their mean value.
switches with bottom plate sampling are used. It is assumed that the capacitors C1–C4 are matched well
Charge accumulation phase: This phase comes up during and α1, α2, α3 and α4 are the normalized deviations of ca-
every negative half of clock cycle. In this phase, S3, S4, S7 and pacitors C1–C4 from their mean value, respectively.
S8 switches are ‘ON’ and the remaining switches are ‘OFF'.
Therefore, the capacitors C1 and C2 are connected between
ΔC i C i C m1
Vcm and virtual short node. This forces the charge on capac- αi ¼ ¼
C m1 C m1
itors C1 and C2 to transfer and accumulate on capacitors C5
and C6, respectively. C1 þ C2 þ C3 þ C4
C m1 ¼
Comparison phase: This phase exists for a small interval 4
which starts at the positive edge if EoC signal is low. In this 4
ð1Þ
phase, the differential outputs of OTA are compared and the ∑ αi ¼ α1 þ α2 þ α3 þ α4
i¼1
decision bit is stored in SIPO register.
Passive charge sharing phase: This phase starts after the C1 þ C2 þ C3 þ C4 4C m1
¼ ¼0
comparison phase in positive half cycle, in which the ca- C m1
pacitors C1, C2, C3 and C4 involve in passive charge sharing
through switches S5, S6, S13, S14, S15 and S16 based on the Similarly, α5 and α6 are the normal deviations of C5 and
comparator output. As shown in Figure 5, if the comparator C6, respectively.
output is high, capacitors C1, C4 and C2, C3 share the charge,
otherwise capacitors C1, C3 and C2, C4 share the charge,
respectively. This allows to decide the comparison level for C5 þ C6
C m2 ¼
the next cycle. 2
The conversion starts with sampling phase and then C 5 C m2
followed by accumulation, comparison and passive charge α5 ¼
C m2
sharing phases for N cycles. At the EoC, the capacitors C5
and C6 are discharged by closing switches S1 and S2, C6 C m2
α6 ¼
when the proposed ADC is configured in SAR mode. In the C m2
first‐order DSM mode, at the EoC of SAR quantizer, C 5 þ C 6 2C m2
the capacitors C5 and C6 are left with the quantization er- ∴ α5 þ α6 ¼ ¼0
C m2
ror. Hence, the integration property allows noise shaping
with an OSR. This characteristic allowed to obtain high
Therefore, from a statistical point of view, it can be
resolutions.
assumed that the sum of normalized deviations is zero.
Accordingly,
3 | DISTORTION ANALYSIS
4
The ADC characteristics deviate from ideal due to non‐ ∑ αi ¼ α1 þ α2 þ α3 þ α4 ¼ 0 ð2Þ
idealities of OTA, capacitors' mismatch and switches. i¼1
This non‐linearity reflects as a distortion in the output and
degrades the effective number of bits (ENoB). The esti- α5 þ α6 ¼ 0 ð3Þ
mation of distortion shows the effect of each sub circuit
and the specifications needed to achieve the required The charge sharing between capacitors C1 and C4 de-
resolution. termines the voltage reference levels, whereas capacitors C5
and C6 are involved in accumulation and comparison. There-
fore, the group of capacitors C1–C4 and C5–C6 need to be
3.1 | Capacitor mismatch matched well. The mismatch between them induces an error
voltage in each comparison and causes non‐linearity in ADC
The accuracy of SAR ADC depends on the matching of transfer characteristics. In SAR ADC operation mode, the
feedback capacitors. The physical design and manufacturing deviation of reference voltages in each cycle due to the ca-
process control the variation of mismatch between capacitors. pacitors' mismatch is derived and tabulated in Table 1. The
This kind of mismatch cannot be removed entirely but this maximum integrated non‐linearity (INLmax) can be derived as
can be viewed as a random statistical process and the shown in Equation (4), and it occurs when the comparator
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- POLINENI ET AL.

TA B L E 1 SAR ADC voltage reference levels due to capacitors' mismatch

Cycle Voltage reference level Error in Voltage reference level (Ve)

1 0 0
�
2 ð 1ÞbN 1
1 α1 þα V dd
2
2
22 ð 1ÞbN 1 ðα1 þ α2 Þ V2dd3
� � �
3 ð 1ÞbN 1
1 α1 þα2 V dd
2 22 þ ð 1Þ
bN 2
1 2ðα1 þα2 Þ
2
V dd
23 ð 1ÞbN 1 ðα1 þ α2 Þ V2dd3 þ 2ð 1ÞbN 2 ðα1 þ α2 Þ V2dd4
� � �
4 ð 1ÞbN 1
1 α1 þα2 V dd
2 22 þ ð 1Þ
bN 2
1 2ðα1 þα2 Þ
2
V dd
23 þ ð 1ÞbN 1 ðα1 þ α2 Þ V2dd3 þ 2ð 1ÞbN 2 ðα1 þ α2 Þ V2dd4 þ
� �
�V dd
ð 1ÞbN 3
1 3ðα1 þα2 Þ
2
V dd
24 3ð 1ÞbN 3
α1 þ α2 25

· · ·
· · ·
· · ·
� �
N ∑N bN kðα1 þα2 Þ V dd
∑N bN k
ðα1 þ α2 Þ 2Vðkþ2Þ
k¼1 kð 1Þ
1 k 1 dd
k¼1 ð 1Þ 1 2 2ðkþ1Þ

Abbreviation: SAR ADC, successive approximation register analog to digital converter.

output is ‘1’ in all cycles. The standard deviation (σ) of this left side of C5 is vop[n 1]/A. Thus, the charge on C5
INLmax relates to the standard deviation of capacitor (σΔC) as (q5[n 1]) can be written as
shown in Equation (5).

� �
1
k N 2
N 1
q5 ½n 1� ¼ C 5 1 þ vop ½n 1� ð6Þ
∣ INL ∣max ¼ ðα1 þ α2 Þ2 ∑ k A
k¼1 2
� �
N þ1 In charge integration phase, it is assumed that the charge q
¼ ðα1 þ α2 Þ2N 2 2 ð4Þ
2N 1 flows out from C1 to C5 and the charge on C1 becomes
� �
N þ1
¼ ðα1 þ α2 Þ 2N 1 � �
2 vop ½n�
q1 ½n� q ¼ C1 ð7Þ
N
� σ ΔC A
σ ∣ INL ∣max ¼ 2 N 1 pffiffi ð5Þ
2C
From Equation (7), the transferred charge q can be written
as

3.2 | OTA non‐idealities

� �
vop ½n�
In Section 2, operation of the proposed ADC is demonstrated q ¼ q1 ½n� C1 ð8Þ
A
by assuming infinite gain, bandwidth for OTA and also instant
charge transfer between capacitors. In reality, due to the finite
After, charge (q) transfer takes place, the charge on
gain of OTA, during charge sharing, some charge will be left
capacitor C5 becomes
behind in capacitors C1 and C2, which is known as static error
voltage. Similarly, the finite UGB and slew rate of amplifier
causes settling time error, which is known as dynamic error.
These errors depend on the input signal, which causes har- q5 ½n� ¼ q5 ½n 1� þ q
monics at the output. � �
vop ½n�
q5 ½n� ¼ q5 ½n 1� þ q1 ½n� C1
A
ð9Þ
3.2.1 | Finite gain of OTA q5 ½n 1� þ q1 ½n�
vop ½n� ¼ � �
1 C1
C5 1 þ þ
The switched‐capacitor integrator transfer function is derived A C5A
as follows [18] by analysing the finite gain effect of OTA.
During sampling phase (ϕ1), C1 charges to the input voltage q6 ½n 1� þ q2 ½n�
vom ½n� ¼ � �
(vip[n]), while C5 holds the charge (q5[n 1]) held in previous 1 C2 ð10Þ
C6 1 þ þ
cycle. Owing to the finite gain (A) of OTA, the voltage on the A C6A
POLINENI ET AL.
- 147

Voltage reference levels deviate from the ideal voltage 1 z-plane

references because of this repetitive gain error which results in
non‐linearity in ADC transfer characteristics. Equation (11)
shows the voltage reference error due to the finite gain of OTA 0.5
in the nth cycle of SAR ADC operation: zeros
A
0
C 1 V dd N 1 k
Ve ¼ ∑ ð 1ÞbN k ðkþ1Þ ð11Þ
C 5 A k¼1 2
-0.5
The maximum integrated non‐linearity can be calculated as
-1
C1 N � -1 0 1
∣INL∣fmaxg ¼ 2 N 1 ð12Þ
C5A
(a)
From Equation (12), the OTA gain needs to satisfy the
following relation to achieve INL less than 0.5 LSB:

1 z-plane
C 1 Nþ1 �
A> 2 2N 2 ð13Þ
C5
0.5
In DSM operation, the variation in integrator transfer A
function alters the signal transfer function (STF) and noise 0
transfer function (NTF). By substituting Equation (6) and
q1[n] ¼ C1vip[n] in Equation (9) and applying z transform
results in -0.5

C 1 =C 5 V ðzÞ
V op ðzÞ ¼ � � ip � ð14Þ -1
1 þ A1 ð1 þ ϵÞ 1 z 1
1þϵ
-1 0 1
Similarly, (b)
F I G U R E 6 Pole‐zero mapping: (a) signal transfer function and
C 2 =C 6 V ðzÞ
V om ðzÞ ¼ 1
� � im � ð15Þ
(b) noise transfer function for different operational transconductance
1 þ A ð1 þ ϵÞ 1 z 1 amplifier gains
1þϵ

Therefore, the STF and NTF become

where

LðzÞ g:p
C1 C2 ST FðzÞ ¼ ¼ ð18Þ
ϵ¼ ¼ ð16Þ 1 þ LðzÞ 1 pð1 gÞz 1
C 5 ðA þ 1Þ C 6 ðA þ 1Þ
1 1 pz 1
NT FðzÞ ¼ ¼ ð19Þ
Since C1 ¼ C2 and C5 ¼ C6, the loop filter transfer 1 þ LðzÞ 1 pð1 gÞz 1

function of DSM can be written as

From Equation (17), it can be observed that the finite

V op ðzÞ V om ðzÞ g:p amplifier gain has two effects: a small reduction in the in-
LðzÞ ¼ ¼ ð17Þ
V ip ðzÞ V im ðzÞ 1 pz 1
tegrator's gain constant and an inward shift of the integrator's
pole (z 1). The change in integrator's gain constant is equiv-
where g ¼ CC 15 A
Aþ1 and p ¼ 1þϵ
1
are integrator gain and pole, alent to a coefficient error (ϵ) and also causes the extra poles of
respectively. both STF and NTF move away from the origin. Thus, this
148
- POLINENI ET AL.

120
0 8-bit 9-bit 10-bit 11-bit 12-bit 13-bit 14-bit 15-bit
Magnitude (dB)
A 100
-5

SNR (dB)
80
-10
-15 60

-20 40
In Band
-25 20
0 1 2 3 4 0 1 2 3 4
10 10 10 10 10 10 10 10 10 10
Frequency (Hz) OTA Gain (A)
(a) (a)
0
8-bit 9-bit 10-bit 11-bit 12-bit 13-bit 14-bit 15-bit
0 -20
Magnitude (dB)

THD (dB)
-20 -40
A
-40 -60

-60 -80
In Band
-100
-80
100 101 102 103 104
100 101 102 103 104
OTA Gain (A)
Frequency (Hz)
(b)
(b)

F I G U R E 7 Bode plot: (a) signal transfer function and (b) noise 8-bit 9-bit 10-bit 11-bit 12-bit 13-bit 14-bit 15-bit
transfer function for different operational transconductance amplifier gains 100
SNDR (dB)

80

60
change in integrator gain has a negligible impact on the in‐band
SNR degradation. In contrast to this, the second effect, the shift 40
in pole location of loop filter is more problematic because the
loop filter pole becomes an NTF zero. This movement of an 20
100 101 102 103 104
NTF zero affects the attenuation of noise in pass band.
OTA Gain (A)
This phenomenon is modelled in MATLAB for an inte-
(c)
grator gain (C1/C5) of 0.3. The pole‐zero movement in STF
and NTF with OTA gain (A) is observed and plotted in
F I G U R E 8 Analog to digital converter characteristics versus OTA
Figure 6. One can observe that the pole of STF is moving away gain: (a) signal‐to‐noise ratio, (b) total harmonic distortion, (c) signal‐to‐
from z ¼ 0.7 as OTA gain (A) decreases and zero stays at the noise and distortion ratio
origin. This results in the gain reduction in the signal path, as
shown in frequency response of STF in Figure 7. In the pole‐ register small dc input values (u), the following expression [18]
zero plot of NTF, shown in Figure 6, as OTA gain (A) de- should satisfy
creases, the NTF zero moves from z ¼ 1 towards z ¼ 0 and
pole moves away from z ¼ 0.7 which is similar to STF pole
1
movement. The movement of NTF zero causes reduction of A> ð20Þ
attenuation as can be observed in Figure 7. From all of the 2∣u∣
discussions above, it can be concluded that the finite dc gain of
OTA is one of the limiting factors for modulator to achieve It is assumed that the OTA gain is constant over output
maximum SNR. swing in all the above discussions. In practice, OTA gain is a
Further, a low‐order modulator is susceptible to the non‐ function of input voltage, which causes harmonic distortion.
linear phenomenon of dead bands. A dead band is a range of Since the magnitude of the associated input‐referred error
inputs that yields the same periodic output sequence and hence signal is no more than voutmax/A, the maximum output of
the same post‐decimation output. Therefore, in dead band, a OTA (voutmax) is (C1/C5) vinmax. Therefore, upper limit on the
dc input with a small magnitude appears as a zero input. The total harmonic distortion (THD) of the signal is
reason behind this is the shift in NTF's zero from z ¼ 1 to
z ¼ p, which limits the NTF's DC gain to (1 p)/
(1 p þ gp) ¼ 1/(1 þ A) instead of zero. Thus, the modulator C1 1
T HD ¼ ð21Þ
loses its ability to achieve infinite precision with dc signals. To C5 A
POLINENI ET AL.
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TA B L E 2 Computation of capacitor size C1, slew rate and UGB requirements of PADC for various resolutions

Target resolution OSR SNR (dB) v2n;dif f C1(fF) ≥ SAR fclk (kHz) Slew rate (V/μs) UGB (MHz) I (μA)
2
8 1 50 4.05 (μV) 8.2 8 18 0.08 0.43 0.1
2
9 1 56 1.02 (μV) 32.6 9 20 0.09 0.47 0.12
2
10 1 62 0.26 (μV) 129.7 10 22 0.1 0.51 0.14
2
11 1 68 64.2 (nV) 516.2 11 24 0.11 0.55 0.15
2
12 16 75 12.8 (nV) 161.8 7 256 1.2 4.9 1.5
2
13 16 81 3.2 (nV) 643.8 8 288 1.3 5.4 1.8
2
14 32 86 1.02 (nV) 1018 8 576 2.7 10 4
2
15 128 92 0.26 (nV) 1013 6 1792 9 27 12

Abbreviations: OSR, oversampling ratio; SNR, signal‐to‐noise ratio; UGB, unity gain bandwidth.

Beta Multiplier Programmable Regulated Cascode Bias Generator

Vdd

M55 M53 M50 M48 M46 M43 M40 M38 M36 M34 M32 M30 M28 M26 M22 Vb1
Vbiasp Vbiasp Vbiasp

M39 M37 M35 M33 M31 M29 M27 M25 M21 Vb2
M51 Vreg R7 R6 R5 R4 R3 R2 R1 R0

M45 M42 Vb3

M54 M52 Vbiasn M49 M47 M24 M20
Vbiasn Vb4
M44 M41 M23 M19

Vdd

M10 Vb1 M11 M17 M18

M8 Vb2 M9 M13 Vcm M15

Vom Vop M14 M16 Vom
Vip Vim
M6 Vb3 M1 M2 Vb3 M7 Vcmfb
Vb4 Vb4
M4 Vcmfb M3 M5 M12

Subthreshold Folded Cascode OTA CMFB circuit

FIGURE 9 Folded cascode operational transconductance amplifier with programmable bias circuit

Even if there is no explicit distortion limit for the ADC, it dBc, which is needed in case of 15‐bit resolution. From this
is needed to ensure that the loop filter is sufficiently linear so result it is concluded that, OTA with 80 dB gain serves our
that the distorted out‐of‐band quantization noise does not fall purpose of designing an ADC that is programmable from 8‐
in the noise notch. Based on these considerations, the amplifier bit to 15‐bit.
is designed for a particular gain, followed by modulator sim-
ulations to verify that the amplifier's linearity is adequate.
Further, the programmable resolution ADC with finite 3.2.2 | Settling time considerations
OTA gain is modelled in MATLAB. The ADC is simulated
with a sinusoidal signal of frequency 123 Hz for resolutions In charge integration phase it is assumed that every conversion
from 8‐bit to 15‐bit. As the OTA gain is varied from 0 to is given sufficient time for charge transfer to settle completely
80 dB, SNR, THD and signal to noise and distortion ratio within the required resolution. This settling time must be less
(SNDR) are observed as shown in Figure 8. It can be seen than half the clock period [19]. Typically, at large inputs, the
that the SNR improves with the OTA gain. It is observed OTA saturates and the charge transfer is limited by the bias
that, the gain around 80 dB ensures the THD below 90 current. This is known as slewing and the rate at which the
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- POLINENI ET AL.

Vdd
clk clk
M10 M8 M6 M7 M9 M11

outm outp
M4 M5

Vip M1 M2 Vim

clk
M3

FIGURE 13 StrongARM comparator

F I G U R E 1 0 Folded cascode operational transconductance amplifier

AC analysis: (a) magnitude response and (b) phase response

82 I =100nA
b
I =120nA FIGURE 14 Layout of PADC
b
DC Gain (dB)

81 Ib=140nA
Ib=160nA
80
I =2 A within the required accuracy. This is known as linear settling
b
79 Ib=4 A phase. It is assumed here that, slewing phase exists for x part of
I =12 A
b
Tclk/2 and rest of Tclk/2 is allocated for linear settling phase.
The boundary conditions for bias current and the trans-
-0.6 -0.4 -0.2 0 0.2 0.4 0.6
Output swing (V) conductance can be derived as follows. The maximum charge
that needs to be transferred from capacitor C1 to C5 is C1Vdd
F I G U R E 1 1 Folded cascode operational transconductance amplifier in xTclk/2 time and therfore, the bias current should follow the
DC gain versus output swing relation as shown in Equation (22).

C 1 V dd
I> ð22Þ
xT clk =2
PSD(dBFS/NBW)

-50

In linear settling phase, the time constant can be written

-100 [18] as

-150 C 1 þ C L þ C 1 C L =C 5 C 1
τ¼ ≈ ð23Þ
gm gm
0 200 400 600 800 1000
Frequency (Hz)
The settling time required to keep normalized error voltage
FIGURE 12 Bootstrapped switch output spectrum. PSD, power below 100 dB is
spectral density
� � � �
T clk
1 x ¼ τln 105 ≈ 12τ ð24Þ
charge transfer happens is called slew rate. Once the OTA 2
input voltage falls under the input range of OTA, the trans-
conductance (gm) decides the minimum time needed to settle The required gm can be computed as
POLINENI ET AL.
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0
gm 12 x
¼ ð26Þ
I V dd 1 x
PSD(dBFS/NBW)
SNDR = 44.93 dB
-20

-40

-60
4 | REALIZATION OF
-80 PROGRAMMABLE RESOLUTION ADC
0 200 400 600 800 1000
Frequency (Hz) The ADC works as SAR ADC for 8‐bit to 11‐bit resolution
(a) and a multi‐bit quantizer DSM for 12‐bit to 15‐bit. Here, the
SAR ADC works as a multi‐bit quantizer. The proposed pro-
0 grammable resolution ADC is built with OTA, comparator,
digital control logic, bootstrapped switch, capacitors and
SNDR = 51.14 dB
PSD(dBFS/NBW)

-20 switches. This section discusses the design of each of these

-40 blocks. The total input‐referred noise power for a switched‐
capacitor integrator [20] is given as
-60
2kT
-80 v2n;dif f ≈ 4 ⋅ ð27Þ
C1
-100
0 200 400 600 800 1000
Frequency (Hz) By considering the in‐band mean‐square noise, the value of
capacitor C1 is calculated and tabulated as shown in Table 2
(b) using Equation (28) for a required SNR. Therefore, the
0 capacitor C1 is determined as 1 pF subject to the noise for 15‐
SNDR = 57.06 dB
bit resolution. The value of capacitor C5 is determined as
PSD(dBFS/NBW)

-20 3.3 pF from the integrator gain which is 0.3:

-40

-60 64kT
C1 ≥ 10SNR=10 ð28Þ
-80 V 2dd OSR
-100
0 200 400 600 800 1000
Frequency (Hz) 4.1 | OTA
(c)
The folded cascode (FC) OTA [21] is used to implement the
0 switched‐capacitor integrator as shown in Figure 9. In the
previous section, it is discussed that a DC gain of 80 dB is
SNDR = 62.8 dB
PSD(dBFS/NBW)

-20 sufficient to keep the third harmonic distortion below

-40
90 dBc. The slew rate and UGB requirements of OTA
depend on the clock frequency used for a particular resolution
-60 from 8‐bit to 15‐bit. The designed ADC operates as SAR ADC
from 8‐bit to 11‐bit resolutions and first‐order multi‐bit SAR
-80
quantizer DSM from 12‐bit to 15‐bit resolutions. Therefore, a
first‐order N‐ bit quantizer DSM requires (N þ 1) OSR clock
0 200 400 600 800 1000
Frequency (Hz) cycles for conversion. The Nyquist sampling frequency is
(d) 2 kHz. Table 2 lists the quantizer resolution, OSR and fre-
quency (fclk) of the clock. The required slew rate and UGB of
F I G U R E 1 5 PADC output spectrum for various resolutions OTA are determined from clock frequency using Equations
@fin ¼ 117 Hz, 256 fast fourier transform points (a) 8‐bit, (b) 9‐bit, (c) 10‐ (22) and (23) and are tabulated. The bias current of FC OTA
bit, (d) 11‐bit and clock frequency are chosen according to ADC resolution.
The FC OTA is designed such that it operates in weak
C1 inversion region for all bias currents. The transistors are sized in
gm ≈ ð25Þ
ð1 xÞT clk =24 such a way that, the flicker noise as well as the effect of transistor
mismatch [22] are less. Figure 10 shows AC response of FC OTA
From Equations (22) and (25), the gm/I ratio can be for all bias currents. It is observed that, the DC gain of OTA is
written as greater than 80 dB in all these cases and also the required slew
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- POLINENI ET AL.

0 0
-20 -20

PSD(dBFS/NBW)

PSD(dBFS/NBW)
SNDR = 69.3 dB SNDR = 72.39 dB
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
1 2 3 4 1 2 3 4
10 10 10 10 10 10 10 10
Frequency (Hz) Frequency (Hz)
(a) (b)

0 0
PSD(dBFS/NBW)

PSD(dBFS/NBW)
SNDR = 79.65 dB SNDR = 85.88 dB
-50 -50

-100 -100

101 102 103 104 101 102 103 104 105

Frequency (Hz) Frequency (Hz)
(c) (d)

F I G U R E 1 6 PADC output spectrum for various resolutions @fin ¼ 117 Hz (a) 12‐bit, 4096 fast fourier transform (FFT) points (b) 13‐bit, 4096 FFT points
(c) 14‐bit, 8192 FFT points (d) 15‐bit, 32,768 FFT points

T A B L E 3 PADC post‐layout simulation

Target resolution OSR SAR fclk ENoB (bits) SFDR (dB) Power (μW)
results summary
8 1 8 18 7.17 58.37 0.856

9 1 9 20 8.2 63.5 1.02

10 1 10 22 9.18 69.14 1.17

11 1 11 24 10.14 66.3 1.287

12 16 7 256 11.22 76.4 12.47

13 16 8 288 11.73 77.8 14.95

14 32 8 576 12.9 83.7 33.06

15 128 6 1792 13.97 91.63 98.35

Abbreviations: ENoB, effective number of bits; OSR, oversampling ration; SAR, successive approximation register;
SFDR, spurious‐free dynamic range.

rate and UGB have been achieved. Also, the phase margin is transmission gate is used as a switch when node voltages swing
above 60o for all cases which can be seen from Figure 10. between 0 and Vdd. Sampling switches S9, S10 and S3, S4 are
Further, the DC analysis is carried out by varying the input implemented using bootstrapped switch [23] to reduce the input
voltage. Figure 11 shows the DC gain variation over output dependent non‐linearity. Switches S1, S2, S5, S6, S7, S8, S12, S15 and
swing. It confirms the variation in DC gain is less than 1 dB over S16 are implemented with NMOS transistors and S11, S13 and S14
�0.54 V output swing, which helps to reduce the harmonics. are implemented using PMOS transistors. Figure 12 shows the
output spectrum of bootstrapped circuit, which ensures that all
harmonics are less than 100 dBc.
4.2 | Switches

The proposed programmable resolution ADC consists of a total 4.3 | StrongARM dynamic comparator
of 16 switches. It is required to consider the effects like charge
injection, clock feed‐through and gate voltage dependent resis- The schematic diagram of a strongARM comparator [24] is
tance while implementing switches, to reduce harmonic distor- shown in Figure 13, which is generally used in ADCs because
tion. The NMOS transistor can switch ‘ON' for voltages below of its positive feedback, high input impedance, rail‐to‐rail
Vdd Vthn, and the PMOS transistor can switch ‘ON' for output swing and negligible static power consumption. In reset
voltages above |Vthp| without distortion. In other cases, phase, the clk signal is low, thus the transistor M3 is in ‘cut‐off’
POLINENI ET AL.
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8-bit 9-bit 10-bit 11-bit 12-bit 13-bit 14-bit 15-bit 100

100 OTA

ADC Power ( W)
80 Digital control logic
80 DAC
60 Comparator
SNDR (dB)

60
40
40
20
20
0
0 8 9 10 11 12 13 14 15
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
Input Amplitude (dBFS) Resolution (bits)

F I G U R E 1 7 Variation in signal‐to‐noise and distortion ratio with FIGURE 19 PADC power consumption versus resolution
input amplitude for various resolutions

8-bit 9-bit 10-bit 11-bit 12-bit 13-bit 14-bit 15-bit comparator output (Dout), EoC and clk as input signals and
100 generates the control signals for all switches (S1:16) in every
clock cycle.
80
SNDR (dB)

60

40 5 | RESULTS
20
The proposed programmable resolution ADC is laid out in
0 UMC 180 nm 1P6M CMOS technology as shown in
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz) Figure 14 and occupies an area of 725 μm � 315 μm. The
capacitors C1 ¼ C2 ¼ C3 ¼ C4 ¼ 1 pF and
F I G U R E 1 8 Variation in signal‐to‐noise and distortion ratio over C5 ¼ C6 ¼ 3.3 pF are implemented using metal‐insulator‐
input signal bandwidth for various resolutions metal capacitors and dummy capacitors are placed around
this capacitor bank to minimize the interference as well as
region and the output nodes outp, outm charged to Vdd mismatch. Also, the analog and digital layouts are separated
through the transistors M8 and M9, respectively. When clk by guard rings and distinct supply voltages are used to
signal goes high, the decision phase starts and output nodes reduce cross talk. Further, the post layout simulations are
start discharging at different rates depending upon the input carried out with an ADC full scale range of 1.8 V differ-
voltages Vip and Vim. Meanwhile, when one of the output ential with a Nyquist sampling frequency of 2 kS/s. Fig-
nodes reaches Vdd |Vthp|, corresponding transistor M6 or ures 15 and 16 show the ADC output spectrum for
M7 switches ‘ON’ and the positive feedback between back‐to‐ resolutions from 8‐bit to 15‐bit, respectively. The first‐order
back connected inverters (M4, M6 and M5, M7), also known as noise shaping (20 dB/decade) can be observed in the res-
latch, enables and pulls one of the output nodes to Vdd and olution modes 12‐bit to 15‐bit. The number of fast fourier
other to gnd. This charge and discharge process takes some transform (FFT) points used for ADC simulations from 8‐
time to make decision which is known as a comparator delay. bit to 11‐bit is 256. Twelve‐bit and thirteen‐bit ADC sim-
This delay can be classified into two parts: ton is the time ulations used 4096 FFT points. Fourteen‐bit ADC simula-
required to discharge one of the output nodes to Vdd |Vthp| tions used 8192 FFT points and 15‐bit ADC simulations
and tlatch is the time needed for latch decision. used 32,768 FFT points. The results of ADC simulations
for various resolution modes (8‐bit to 15‐bit) are summa-
rized in Table 3. The proposed ADC offers adequate
4.4 | Digital control logic unit ENoB for each resolution mode.
Figure 17 shows the plot of SNDR of the proposed ADC
The block level diagram of digital control logic circuit is shown over a normalized input with respect to full signal swing for all
in Figure 4a. It is designed using Verilog‐A and then synthe- resolution modes (8‐bit to 15‐bit). Also, Figure 18 depicts a
sized. The resolution of ADC is programmable using a 3‐bit consistent SNDR over an input signal frequency for all target
select bus res[2 : 0]. The SAR resolution controller programs resolutions. Figure 19 shows the stacking diagram of power
the counter as per the chosen resolution. The counter starts consumption by OTA, digital control logic, DAC and
counting on every positive edge of clock and generates EoC comparator. Table 4 shows the comparison of the performance
signal when it reaches the upper limit. Meanwhile, the of proposed ADC with similar type ADCs. It can be seen that
comparator output (Dout) is stored in SIPO for every clock the proposed ADC is on par with many designs found in state‐
cycle. At the EoC, EoC signal triggers SIPO and gives out the of‐the‐art and demonstrated a new approach to implement
N‐ bit digital data. The switch control logic takes the programmable resolution ADC.
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TA B L E 4 A summary of performance and comparison

[25] [26] [10] [9] [27] [12] This Work

Technology (nm) 65 45 65 130 180 180 180

Supply voltage (V) 0.8 1.2 1 1 0.5 – 0.9 1 1.8

Resolution (bits) 8, 10, 12 4, 5, 6 5 –10 1–8 6 –10 1–10 8–15

Sampling rate 200 MS/s 240 MS/s 200 kS/s 1 MS/s 2 MS/s 5 kS/s 2 kS/s
2
Area (mm ) ‐ ‐ 0.3525 0.1638 0.21 0.0205 0.228

SNDR (dB) 69.1 @ 12 23.4 @ 4 30.4–55 48.1 @ 8 36.8–56.4 57.59 @ 10 45–86

28.8 @ 5

35.4 @ 6

Power (μW) 16,000 @ 8 80 @ 4 0.91 – 2.77 1.76 – 8.8 10.4–22.1 0.42 @ 10 0.86–98

20,000 @ 10 96 @ 5

24,000 @ 12 1150 @ 6

FoMS (dB) 168.3 @ 12 148.17 @ 4 143.8–163.5 98.65 @ 8 149.6–165.9 158.35 @ 10 138.7–159.1

152.87 @ 5

78.6 @ 6

Abbreviations: FoMS, figure‐of‐merit by Schreier; SNDR, signal‐to‐noise and distortion ratio.

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