BACHELOR OF ENGINEERING

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
ENGINEERING

EC 3561-VLSI LABORATORY

LABORATORY MANUAL
 LIST OF EXPERIMENTS

1 DESIGN OF BASIC COMBINATIONAL ANDSEQUENTIAL (FLIP-

FLOPS) CIRCUITS

2.a SIMULATION AND IMPLEMENTATION OF8-BIT ADDER

2.b SIMULATION AND IMPLEMENTATION OFMULTIPLIER

3 DESIGN AND IMPLEMENTATION OFUNIVERSAL SHIFT

REGISTER
4 SIMULATION AND IMPLEMENTATION OFMEMORY

5 SIMULATION AND IMPLEMENTATION OFFINITE STATE MACHINE

6 DESIGN 3-BIT SYNCHRONOUSUP/DOWN COUNTER.

7 DESIGN 4-BIT ASYNCHRONOUSUP/DOWN COUNTER.

8 DESIGN AND SIMULATE A CMOS INVERTER LAYOUT

9 DESIGN AND SIMULATE UNIVERSALGATES LAYOUT

10 DESIGN AND SIMULATE DIGITAL CIRCUITS USING MICROWIND

AND DSCHV3.1

11 STUDY OF TANNER EDA DESIGN TOOL.

12 DESIGN AND SIMULATE A CMOS INVERTING AMPLIFIER

13 DESIGN AND SIMULATE BASIC COMMONSOURCE, COMMON GATE

AND COMMONDRAIN AMPLIFIER

14 SCHEMATIC SIMULATION OFDIFFERENTIAL

AMPLIFIER
Expt No:1 Design of basic Combinational and Sequential
Date : (Flip-Flops) Circuits

AIM:
To design and simulate a CMOS basic gates & flip-flops using HDL.
SOFTWARE USED:
 XILINX

 Modelsim

Theory

AND Gate:
And gate is an electronic circuit that gives a high output (1) only if all its
inputs are high. A dot (.) is used to show the AND operation i.e. A.B.

OR gate:
OR gate is an electronic circuit that gives a high output (1) if one or more
of its inputs are high. A plus (+) is used to show the OR operation.

NOT gate:
NOT gate is an electronic circuit that produces an inverted version of
the input at its output. It is also known as an inverter. If the input variable is A
the inverted output is known as NOT A. This is also shown as A’ or A with a
bar over the top, as shown at the outputs.
NAND Gate:

This is a NOT-AND gate which is equal to an AND gate followed by a

NOT gate. The outputs of all NAND gates are high if any of the inputs are low.
The symbol is an AND gate with a small circle on the output. The small circle
represents inversion.

NOR gate:

This is a NOT-OR gate which is equal to an OR gate followed by a

NOT gate. The outputs of all NOR gates are low if any of the inputs are
high. The symbol is an Or gate with a small circle on the output. The small
circle represents inversion.

EXOR gate
 The ‘Exclusive -OR’ gate is a circuit which will give a high output if
either, but not both of its two inputs are high. An encircled plus sign (O)is
used show the EXOR operation.

EXNOR gate
The ‘Exclisive-NOR’ gate circuit does the opposite to the EXOR gate.
It will give a low output if either, but not both of its two inputs are high.
The symbol is an EXOR gate with a small circle on the output. The small
circle represents inversion.

PROCEDURE:
1. Click on Start -> All Programs -> Xilinx Designer Tools -> Project
Navigator.
2. Click on File -> New Project.
3. Select a Name and Location, then click -> Next.
4. In the Project Setting use the following configuration.

Family as Spartan 3E
Device as XC3S100E
Package as TQ144
Speed as -4
5. Click on -> Next -> Finish.
6. Click on Project -> New Source -> Verilog Module and type a filename.
7. Click on -> Next -> Finish.
8. Type your source file and save.
9. Click on Simulation radio button on the left corner of the screen.
10. Select your filename in the hierarchy.
11.Expand ISIM Simulator and check for behaviour and simulate the
program.
12.Select the necessary input values by right click on value -> Force
Constant .
13. Enter the value in the Force to Value dialog box .
 14. Click on "Run for specific time" in the toolbar.
15. Observe the waveforms.

AND Gate:

TRUTH TABLE:
2 Input AND gate
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
WAVEFROM

OR Gate:

TRUTH TABLE:
2 Input OR gate
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1

WAVEFROM
PROGRAM:
AND GATE:
module and_gate (a,b,y);
input a,b;
output y;
assign y = a & b;
endmodule

OR GATE:
module or_gate (a,b,y);
input a,b;
output y;
assign y = a | b;
endmodule

XOR GATE:
module xor_gate (a,b,y);
input a,b;
output y;
assign y = a ^ b;
endmodule

NOT GATE:
module not_gate (a,b) ;
input a ;
output b;
assign b = ~ a;
endmodule

NAND GATE:
module nand_gate (a,b,y);
input a,b;
output y;
assign y = ~ (a & b);
endmodule
NOR GATE:
module nor_gate (a,b,y);
input a,b;
output y;
assign y = ~ (a | b);
endmodule

EXNOR GATE:
module exnor_gate (a,b,y);
input a,b;
output y;
assign y = ~ (a ^ b);
endmodule

NAND Gate:

TRUTH TABLE:
2 Input NAND gate
A B AB
0 0 1
0 1 1
1 0 1
1 1 0
WAVEFROM

NOR Gate:

TRUTH TABLE:
2 Input NOR gate
A B A+B
0 0 1
0 1 0
1 0 0
1 1 0
WAVEFROM

XOR Gate:

TRUTH TABLE:
2 Input EXOR
gate
A B AOB
0 0 0
0 1 1
1 0 1
1 1 0

WAVEFROM

XNOR Gate:

TRUTH TABLE:
2 Input EXNOR gate
A B AOB
0 0 1
0 1 0
1 0 0
1 1 1
WAVEFROM

NOT Gate:

TRUTH TABLE:
NOT gate
A A
0 1
1 0

WAVEFROM

D Flip-Flop:

TRUTH TABLE:

D Qn+1
0 0
1 1
 OUTPUT
CLOCK RESET INPUT (D)
q
0 0 0 0
1 0 0 0
0 0 1 0
1 0 1 0
0 0 0 0
1 0 0 0
0 1 1 0
1 1 1 1
0 1 0 1
1 1 0 0
0 1 1 0
1 1 1 1
0 0 0 0
1 0 0 0
0 0 0 0

PROGRAM:
// Module Name: DFF
module DFF(Clock, Reset, d, q);
input Clock;
input Reset;
input d;
output q;
reg q;
always@(posedge Clock or negedge Reset)
if (~Reset) q=1'b0;
else q=d;
endmodule

PROGRAM:
// Module Name: TFF
module TFF(Clock, Reset, t, q);
input Clock;
input Reset;
input t;
output q;
reg q;
always@(posedge Clock , negedge Reset) if(~Reset) q=0; else if (t) q=~q;
else q=q;
endmodule
TRUTH TABLE:

CLOCK RESET INPUT (T) OUTPUT

Truth Table:

CLOCK RESET J K Q
PROGRAM:
// Module Name: JKFF
module JKFF(Clock, Reset, j, k, q);
input Clock;
input Reset;
input j;
input k;
output q;
reg q;
always@(posedge Clock, negedge Reset) if(~Reset)q=0;
else
begin
case({j,k}) 2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
2'b11: q=~q;
endcase
end
endmodule

RESULT:
 Date:
Ex No : 2. a SIMULATION AND IMPLEMENTATION OF 8-BIT ADDER

AIM : To simulate and implement 8-bit Ripple Carry adder in FPGA using
Verilog code.
SOFTWARE USED:
 Xilinx 8.1 ISE Sim
 Spartan 3E

THEORY:
FULL ADDER:
Full adder is a Logic circuit that performs addition operation on three bit binary
numbers. Full adder Produces the sum of three inputs and carry Value.
TRUTH TABLE :

a b c sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
LOGIC DIAGRAM:
8- BIT RIPPLE CARRY ADDER USING FULL ADDER
A ripple carry adder is a logic circuit in which the carry-out of each full adder is
the carry-in of the succeeding next most significant full adder. It is called a ripple carry
adder because each carry bit gets rippled into the next stage. A standard 8-bit ripple-
carry adder built as a cascade from eight 1-bit full-adders.

PROCEDURE:
SIMULATION :
1. Click on Start -> All Programs -> Xilinx Designer Tools -> Project Navigator.
2. Click on File -> New Project.
3. Select a Name and Location, then click -> Next.
4. In the Project Setting use the following configuration.

Family as Spartan 3E
Device as XC3S100E
Package as TQ144
Speed as -4
5. Click on -> Next -> Finish.
6. Click on Project -> New Source -> Verilog Module and type a filename.
7. Click on -> Next -> Finish.
 8. Type your source file and save.
9. Click on Simulation radio button on the left corner of the screen.
10. Select your filename in the hierarchy.
11. Expand ISIM Simulator and check for behaviour and simulate the program.
12.Select the necessary input values by right click on value -> Force Constant.
13.Enter the value in the Force to Value dialog box.
14. Click on "Run for specific time" in the toolbar.
15. Observe the waveforms.

IMPLEMENTATION:
 Click on project, go to new source. Select implementation constraints file type
and enter file name & click next, then finish
 Write the inputs, outputs & its pin location in proper format of .ucf file.
 Open main program &double click on synthesize-XST. After successful
completion of synthesis , double click on implementation design. (Translate,
Map, Place &Route)
 After Successful completion of implement design double click on Programming
file Generation.
 After the successful completion of all these processes double click on configure
Target Device and a new ISE iMPACT window open.
 Connect the Xilinx board to your PC using USB board.
 Double click on Boundary Scan. Check auto cable connection out.
 Click on File->Initialize chain.
 After that they ask for “Do You want to continue and assign configuration files?”
 Click on Yes and Select the generated bit-stream file.
 Click on open. After that they ask “Do you want to attach an SPI or BPI PROM
to this device”. Click on operation ->program. If programming successful then
they show Program succeeded.
 Output can be viewed in the board by using LEDs and switches.
//FULL ADDER
module fulladder (a,b,c,sum,cout);
output sum, cout;
input a,b,c;
assign sum = a^b^c;
assign cout=(a&b)|(b&c)|(c&a);
endmodule

//8-BIT RCA
module ripple_8adder( input [7:0] a, input [7:0] b, input cin, output [7:0] sum,
output carry );
wire [6:0]c;
fulladder FA1(a[0],b[0],cin,sum[0],c[0]);
fulladder FA2(a[1],b[1],c[0],sum[1],c[1]);
fulladder FA3(a[2],b[2],c[1],sum[2],c[2]);
fulladder FA4(a[3],b[3],c[2],sum[3],c[3]);
fulladder FA5(a[4],b[4],c[3],sum[4],c[4]);
fulladder FA6(a[5],b[5],c[4],sum[5],c[5]);
fulladder FA7(a[6],b[6],c[5],sum[6],c[6]);
fulladder FA8(a[7],b[7],c[6],sum[7],carry);
endmodule

RESULT:
Date:
Ex No : 2.b SIMULATION AND IMPLEMENTATION OF MULTIPLIER

AIM : To simulate and implement 4-bit multiplier in FPGA using Verilog code.
SOFTWARE USED:

 Xilinx 8.1 ISE Sim

 Spartan 3E

THEORY:
4- BIT ARRAY MULTIPLIER
Binary multiplication is done by doing additions. Partial products are
calculated by multiplying the multiplicand by each bit of the multiplier and then
summing the partial products.

Example
 „0‟

„0‟

Fig. 4X4 Array Multiplier

PROCEDURE:
1. Click on Start -> All Programs -> Xilinx Designer Tools -> Project
Navigator.
2. Click on File -> New Project.
3. Select a Name and Location, then click -> Next.
4. In the Project Setting use the following configuration.

Family as Spartan 3E
Device as XC3S100E
Package as TQ144
Speed as -4
5. Click on -> Next -> Finish.
6. Click on Project -> New Source -> Verilog Module and type a filename.
7. Click on -> Next -> Finish.
 8. Type your source file and save.
9. Click on Simulation radio button on the left corner of the screen.
10. Select your filename in the hierarchy.
11.Expand ISIM Simulator and check for behaviour and simulate the program.
12.Select the necessary input values by right click on value -> Force Constant.
13.Enter the value in the Force to Value dialog box.
14. Click on "Run for specific time" in the toolbar.
15. Observe the waveforms.

IMPLEMENTATION
 Click on project, go to new source. Select implementation constraints file
type and enter file name & click next, then finish
 Write the inputs, outputs & its pin location in proper format of .ucf file.
 Open main program &double click on synthesize-XST. After successful
completion of synthesis , double click on implementation design. (Translate,
Map, Place &Route)
 After Successful completion of implement design double click on
Programming file Generation.
 After the successful completion of all these processes double click on
configure Target Device and a new ISE iMPACT window open.
 Connect the Xilinx board to your PC using USB board.
 Double click on Boundary Scan. Check auto cable connection out.
 Click on File->Initialize chain.
 After that they ask for “Do You want to continue and assign configuration
files?”
 Click on Yes and Select the generated bit-stream file.
 Click on open. After that they ask “Do you want to attach an SPI or BPI
PROM to this device”. Click on operation ->program. If programming
successful then they show Program succeeded.
 Output can be viewed in the board by using LEDs and switches.
PROGRAM:

//Full Adder
module Full_Adder(input x, y, cin, output s, cout);
wire c1,c2,c3;
xor(s,x,y,cin);
and(c1,x,y),(c2,x,cin),(c3,y,cin);
or(cout,c1,c2,c3);
endmodule

//4-Bit array multiplier

module Mul_4bit(input [3:0] Q,input [3:0] M,output [7:0]P);
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11;
wire d1,d2,d3,d4,d5,d6,d7;
wire e1,e2,e3;
wire f1,f2,f3,f4,f5,f6,f7;
wire g1,g2,g3,g4;
and(c1,M[3],Q[1]),(c2,M[2],Q[2]),(c3,M[1],Q[3]),(c4,M[3],Q[0]),(c5,M[2],Q[1]),
(c6,M[1],Q[2]),(c7,M[2],Q[0]),(c8,M[1],Q[1]),(c9,M[0],Q[2]),(c10,M[1],Q[0]),
(c11,M[0],Q[1]),(P[0],M[0],Q[0]);
Full_Adder fa1(c1,c2,c3,d2,d1);
Full_Adder fa2(c4,c5,c6,d4,d3);
Full_Adder fa3(c7,c8,c9,d6,d5);
Full_Adder fa4(c10,c11,0,P[1],d7);
and(e1,M[2],Q[3]),(e2,M[3],Q[2]),(e3,M[0],Q[3]);
Full_Adder fa5(e1,e2,d1,f2,f1);
Full_Adder fa6(d2,d3,f5,f4,f3);
Full_Adder fa7(d4,e3,d5,f6,f5);
Full_Adder fa8(d6,d7,0,P[2],f7);
and(g1,M[3],Q[3]);
Full_Adder fa9(g1,f1,g2,P[6],P[7]);
Full_Adder fa10(f2,f3,g3,P[5],g2);
Full_Adder fa11(f4,0,g4,P[4],g3);
Full_Adder fa12(f6,f7,0,P[3],g4);
endmodule

Result:
Date:
Ex No : 3.DESIGN AND IMPLEMENTATION OF UNIVERSAL SHIFT
REGISTER

AIM : To design, simulate and implement Universal Shift Register in FPGA

using Verilog code.
SOFTWARE USED:

 Xilinx 8.1 ISE Sim

 Spartan 3E

THEORY:
The Shift Register is a sequential logic circuit that can be used for the
storage or the transfer of binary data. Universal shift register is capable of
converting input data to parallel or serial which also does shifting of data
bidirectional, unidirectional (SISO, SIPO, PISO, PIPO) and are parallel load this is
called as Universal shift register.
Shift Registers are used as: Data storage device, Delay element,
communication lines, digital electronic devices etc.

Fig. Block Diagram of 4-bit USR

 Table: Function Table

PROGRAM:

module SHFTREG(I,select,lfin,rtin,A,CLK,Clr);
input[3:0]I; //Parallel input
input[1:0]select; //Mode select
input lfin,rtin,CLK,Clr; //Serial inputs,clock,clear
output[3:0]A; //Parallel output

/Instantiate the four stages

stage ST0(A[0],A[1],lfin,I[0],A[0],select,CLK,Clr);
stage ST1(A[1],A[2],A[0],I[1],A[1],select,CLK,Clr);
stage ST2(A[2],A[3],A[1],I[2],A[2],select,CLK,Clr);
stage ST3(A[3],lfin,A[2],I[3],A[3],select,CLK,Clr);
endmodule

//One stage of shift register

module stage(i0,i1,i2,i3,Q,select,CLK,Clr);
input i0,i1,i2,i3,CLK,Clr;
input[1:0]select;
output Q;
reg Q;
reg D;
//4x1 multiplexer
always@(i0 or i1 or i2 or i3 or select)
case(select)
 2'b00:D=i0;
2'b01:D=i1;
2'b10:D=i2;
2'b11:D=i3;
endcase
//D flip-flop
always@(posedge CLK or negedge Clr)
if(~Clr) Q=1'b0;
else Q=D;
endmodule

RESULT:
Date:
Ex No :4 SIMULATION AND IMPLEMENTATION OF MEMORY

AIM : To simulate and implement memory in FPGA using Verilog code.

SOFTWARE USED:

 Xilinx 8.1 ISE Sim

 Spartan 3E

THEORY:
A memory is just like a human brain. It is used to store data and instruction.
Computer memory is the storage space in computer where data is to be processed
and instructions required for processing are stored.
A RAM constitutes the internal memory of the CPU for storing data,
program and program result. It is read/write memory. It is called random access
memory (RAM).
Since access time in RAM is independent of the address to the word that is,
each storage location inside the memory is as easy to reach as other location &
takes the same amount of time. We can reach into the memory at random &
extremely fast but can also be quite expensive.
RAM is volatile, i.e. data stored in it is lost when we switch off the computer
or if there is a power failure. Hence, a backup uninterruptible power system (UPS)
is often used with computers. RAM is small, both in terms of its physical size and
in the amount of data it can hold.

PROGRAM
module mem_ram_sync(clk, rst, read_rq, write_rq, rw_address,write_data,
read_data);
input clk, rst, read_rq, write_rq;
input[5:0] rw_address;
input[7:0] write_data;
output[7:0] read_data;
reg[7:0] read_data;
integer i;
// Declare memory 64x8 bits = 512 bits or 64 bytes
reg [7:0] memory_ram_d [63:0];
reg [7:0] memory_ram_q [63:0];

// Use positive edge of clock to read the memory

 // Implement cyclic shift right
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
for (i=0;i<64; i=i+1)
memory_ram_q[i] <= 0;
end
else
begin
for (i=0;i<64; i=i+1)
memory_ram_q[i] <= memory_ram_d[i];
end
end
always @(*)
begin
for (i=0;i<64; i=i+1)
memory_ram_d[i] = memory_ram_q[i];
if (write_rq && !read_rq)
memory_ram_d[rw_address] = write_data;
if (!write_rq && read_rq)
read_data = memory_ram_q[rw_address];
end
endmodul

Result:
 EX.NO:5. A
DESIGN AND IMPLEMENTATION OF FINITE STATE MACHINE
(MOORE MACHINE) USING HDL
DATE:

AIM:

To write a verilog program for finite state machine (moore machine) to synthesize and simulate using
Xilinx software tool and implement in FPGA.

TOOLS REQUIRED:
Software:
1. Xilinx ISE Design Suite
2. Xilinx SPARTAN3E FPGA kit

THEORY:
A synchronous sequential circuit is also called as Finite State Machine FSM, if it has finite number of
states. There are two types of FSMs.
 Mealy State Machine
 Moore State Machine
Moore State Machine:
A Finite State Machine is said to be Moore state machine, if outputs depend only on present
states.
PROCEDURE:

SIMULATION USING VERILOG

1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the
synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output wave form can be observed in model sim.

IMPLEMENTATION USING FPGA

Software Part

1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double clicking
on the synthesis in the process window
4. Perform the functional simulation using Xilinx ISE simulator.
5. Open a new UCF file and lock the pins of the design with FPGA I/O pins.
6. Implement the design by double clicking on the implementation tool selection.
7. Create programming file (i.e., bit file) for downloading into the specified device.

Hardware part
 1. Connect the power supply cable to the FPGA kit using power supply adapter.

2.Connect FPGA board to parallel port of PC using parallel port cable

3.Connect FRC1 of FPGA board with the switches (i/ps) of GPIO card - II using FRC cable.
4.Connect FRC2 of FPGA board with the LEDs (o/ps) of GPIO card - II using FRC cable.
5.To simulation go to model sim and verify the output waveform.(for simulation execute the program
with test bench)

FINITE STATE MACHINE (STATE DIAGRAM OF MOORE MACHINE):

PROGRAM:
Verilog code for moore state machine:
module moore( clk, rst, inp,
outp); input clk, rst, inp;
output outp;
reg [1:0]
state; reg
outp;
always @( posedge clk,
posedge rst ) begin
if( rst )
state <=
2'b00; else
begin
case( state ) 2'b00:
begin
if( inp ) state
<= 2'b01; else
state <= 2'b10;
end
2'b01:
begin
if( inp ) state <=
2'b11; else state
<= 2'b10;
end
2'b10:
 begin
if( inp ) state <=
2'b01; else state
<= 2'b11;
end
2'b11:
begin
if( inp ) state <=
2'b01; else state
<= 2'b10;
end
endc
ase
e
nd
end
always @(posedge clk,
posedge rst) begin
if( rst )
outp <= 0;
else if( state ==
2'b11 ) outp
<= 1;
else outp
<=0; end
endmodule

RESULT:
Thus the verilog program for finite state machine (moore machine) were written, synthesized and
implemented in FPGA using Xilinx tool.
 EX.NO:5.B
DESIGN AND IMPLEMENTATION OF FINITE STATE MACHINE
(MEALY MACHINE) USING HDL
DATE:

AIM:

To write a verilog program for finite state machine (mealy machine) to synthesize and simulate using
Xilinx software tool and implement in FPGA.

TOOLS REQUIRED:
Software:
1. Xilinx ISE Design Suite
2. Xilinx SPARTAN3E FPGA kit

THEORY:
A synchronous sequential circuit is also called as Finite State Machine FSM, if it has finite number of
states. There are two types of FSMs.
 Mealy State Machine
 Moore State Machine
Mealy State Machine:
A Finite State Machine is said to be Mealy state machine, if outputs depend on both present
inputs & present states.

PROCEDURE:

SIMULATION USING VERILOG

1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the
synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output wave form can be observed in model sim.

IMPLEMENTATION USING FPGA

Software Part

1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double clicking
on the synthesis in the process window
4. Perform the functional simulation using Xilinx ISE simulator.
5. Open a new UCF file and lock the pins of the design with FPGA I/O pins.
6. Implement the design by double clicking on the implementation tool selection.
7. Create programming file (i.e., bit file) for downloading into the specified device.
Hardware part
1. Connect the power supply cable to the FPGA kit using power supply adapter.
2.Connect FPGA board to parallel port of PC using parallel port cable.
3.Connect FRC1 of FPGA board with the switches (i/ps) of GPIO card - II using FRC cable.
4.Connect FRC2 of FPGA board with the LEDs (o/ps) of GPIO card - II using FRC cable.
5.To simulation go to model sim and verify the output waveform.(for simulation execute the program
with test bench)

FINITE STATE MACHINE (STATE DIAGRAM OF MEALY MACHINE):

PROGRAM:
Verilog code for mealy state machine
module mealy( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg [1:0] state; reg outp;
always @( posedge clk, posedge rst )
begin
if( rst )
begin
state <= 2'b00;
outp <= 0; end
else begin
case( state ) 2'b00: begin
if( inp ) begin state <= 2'b01; outp <= 0;
end
else begin
state <= 2'b10; outp <= 0;
end
end

2'b01: begin
if( inp ) begin state <= 2'b00; outp <= 1;
end
else begin
state <= 2'b10; outp <= 0;
end
end
 2'b10: begin
if( inp ) begin state <= 2'b01; outp <= 0;
end
else begin
state <= 2'b00; outp <= 1;
end
end

default: begin
state <= 2'b00; outp <= 0;
end

endcase
end
end
endmodule

RESULT:
Thus the verilog program for finite state machine (mealy machine) were written, synthesized and
implemented in FPGA using Xilinx tool.
Expt. No: 6
Date:

DESIGN OF 3-BIT SYNCHRONOUS UP/DOWN COUNTER

AIM:
To design a 3-bit synchronous up/down counter using HDL.

SOFTWARE REQUIRED:
PC with Windows XP.
XILINX 9.2i
FPGA-SPARTAN-3 KIT
PARALLEL TO JTAG CABLE

THEORY

An ‘N’ bit binary counter consists of ‘N’ flip-flops. If the counter counts from 0 to 2𝑁
− 1, then it is called as binary up counter. Similarly, if the counter counts down from 2𝑁 − 1
to 0, then it is called as binary down counter.
There are two types of counters based on the flip-flops that are connected in
synchronous or not.
● Asynchronous counters
If the flip-flops do not receive the same clock signal, then that counter is called as
Asynchronous counter. The output of system clock is applied as clock signal only to first flip-
flop. The remaining flip-flops receive the clock signal from output of its previous stage flip-
flop. Hence, the outputs of all flip-flops do not change affect at the same time.
● Synchronous counters
If all the flip-flops receive the same clock signal, then that counter is called as
Synchronous counter. Hence, the outputs of all flip-flops change affect at the same time.

Synchronous 3 bit Up/Down counter

1. Decide the number and type of FF

Here we are performing 3 bit or mod-8 Up or Down counting, so 3 Flip Flops are
required, which can count up to 23-1 = 7. Here T Flip Flop is used.
2. Write excitation table of Flip Flop
3. Decision for Mode control input M
When M=0, then the counter will perform up counting.
When M=1, then the counter will perform down counting.
4. Draw the state transition diagram and circuit excitation table
5. Circuit excitation table
The circuit excitation table represents the present states of the counting sequence and
the next states after the clock pulse is applied and input T of the flip-flops. By seeing the
transition between the present state and the next state, we can find the input values of 3 Flip
Flops using the Flip Flops excitation table. The table is designed according to the required
counting sequence. If there is a change in the output state of a flip flop (i.e. 0 to 1 or 1 to 0),
then the corresponding T value becomes 1 otherwise 0.
6. Find a simplified equation using k map
Here we are finding the minimal Boolean expression for each Flip Flop input T using
k map.
CIRCUIT EXCITATION TABLE

SIMPLIFIED EQUATION USING K MAP

7. Create a circuit diagram
8. The simplified expression for Flip Flops is used to design circuit diagrams. Here all the
connections are made according to simplified expressions for Flip Flops.

ALGORITHM:
1. New project and type the project name and check the top-level source type as HDL
2. Enter the device properties and click Next
3. Click New Source and Select the Verilog Module and then give the file name.
4. Give the Input and Output port names and click finish.
5. Type the Verilog program and save it
6. Double click the synthesize XST and check syntax
7. Simulate the waveform by behavioral simulation
8. For implementation Select User constraints and give input and output port pin
number
9. Click Implement design for Translate, map and place & route
10. Generate .bit file using programming file
11. Implement in FPGA through parallel-JTAG cable
12. Check the behavior of design in FPGA by giving inputs
CIRCUIT DIAGRAM

RTL SCHEMATIC:
 PROGRAM:
module counter(clk,reset,up_down,load,data,count);
//define input and output ports
input clk,reset,load,up_down;
input [3:0] data;
output reg [3:0] count;
//always block will be executed at each and every positive edge of the clock
always@(posedge clk)
begin
if(reset) //Set Counter to Zero
count <= 0;
else if(load) //load the counter with data value
count <= data;
else if(up_down) //count up
count <= count + 1;
else //count down
count <= count - 1;
end
endmodule :counter
Expt. No: 7 DESIGN 4-BIT ASYNCHRONOUS UP/DOWN COUNTER
Date:
AIM:
To implement 4-BIT ASYNCHRONOUS UP/DOWN COUNTER USING HDL

SOFTWARE REQUIRED:

PC with Windows XP.

XILINX 9.2i
FPGA-SPARTAN-3 KIT
PARALLEL TO JTAG CABLE
ALGORITHM:
1. Click on Start -> All Programs -> Xilinx Designer Tools -> Project
Navigator.
2. Click on File -> New Project.
3. Select a Name and Location, then click -> Next.
4. In the Project Setting use the following configuration.

Family as Spartan 3E
Device as XC3S100E
Package as TQ144
Speed as -4
5. Click on -> Next -> Finish.
6. Click on Project -> New Source -> Verilog Module and type a filename.
7. Click on -> Next -> Finish.
8. Type your source file and save.
9. Click on Simulation radio button on the left corner of the screen.
10. Select your filename in the hierarchy.
11.Expand ISIM Simulator and check for behaviour and simulate the
program.
12.Select the necessary input values by right click on value -> Force
Constant .
13. Enter the value in the Force to Value dialog box .
14. Click on "Run for specific time" in the toolbar.
15. Observe the waveforms.
 PROGRAM:
VERILOG CODE
module JK_flipflop (
input clk, rst_n,
input j,k,
output reg q, q_bar
);

always@(posedge clk or negedge rst_n) begin // for asynchronous reset

if(!rst_n) q <= 0;
else begin
case({j,k})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= ~q; // Toggle
endcase
end
end
assign q_bar = ~q;
endmodule

module updown_selector(input q, q_bar, bit up, output nclk);

assign nclk = up?q_bar:q;
endmodule

module asynchronous_counter #(parameter SIZE=4)(

input clk, rst_n,
input j, k,
input up,
output [3:0] q, q_bar
);
wire [3:0] nclk;
genvar g;
/*
// Up Counter (at output q)
JK_flipflop jk1(clk, rst_n, j, k, q[0], q_bar[0]);
JK_flipflop jk2(q_bar[0], rst_n, j, k, q[1], q_bar[1]);
JK_flipflop jk3(q_bar[1], rst_n, j, k, q[2], q_bar[2]);
JK_flipflop jk4(q_bar[2], rst_n, j, k, q[3], q_bar[3]);

// Down Counter (at output q)

JK_flipflop jk1(clk, rst_n, j, k, q[0], q_bar[0]);
JK_flipflop jk2(q[0], rst_n, j, k, q[1], q_bar[1]);
JK_flipflop jk3(q[1], rst_n, j, k, q[2], q_bar[2]);
JK_flipflop jk4(q[2], rst_n, j, k, q[3], q_bar[3]);

// Up and Down Counter (at output q)

JK_flipflop jk1(clk, rst_n, j, k, q[0], q_bar[0]);
updown_selector ud1(q[0], q_bar[0], up, nclk[0]);

JK_flipflop jk2(nclk[0], rst_n, j, k, q[1], q_bar[1]);

updown_selector ud2(q[1], q_bar[1], up, nclk[1]);
 JK_flipflop jk3(nclk[1], rst_n, j, k, q[2], q_bar[2]);
updown_selector ud3(q[2], q_bar[2], up, nclk[2]);

JK_flipflop jk4(nclk[2], rst_n, j, k, q[3], q_bar[3]);

*/

// Using generate block

JK_flipflop jk0(clk, rst_n, j, k, q[0], q_bar[0]);
generate
for(g = 1; g<SIZE; g++) begin
updown_selector ud1(q[g-1], q_bar[g-1], up, nclk[g-1]);
JK_flipflop jk1(nclk[g-1], rst_n, j, k, q[g], q_bar[g]);
end
endgenerate
endmodule

RTL SCHEMATIC:

Wave form

Result:
Thus the verilog program for Asynchronous up/down counter were written, synthesized and
simulated using Xilinx tool.
Date:

EX. NO. 8 DESIGN AND SIMULATE A CMOS INVERTER LAYOUT

AIM:

To design and simulate a CMOS inverter layout using Microwind.

TOOLS REQUIRED:
1. MICROWIND V3.1

THEORY:

Fig. CMOS inverter

A CMOS (Complementary Metal-oxide Semiconductor) inverter is a device

that produces logic functions and is the primary component of all integrated circuits.
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain
and gate terminals, a supply voltage VDD at the PMOS source terminal, and a
ground connected at the NMOS source terminal, were VIN is connected to the gate
terminals and VOUT is connected to the drain terminals. It is important to notice
that the CMOS does not contain any resistors, which makes it more power efficient
that a regular resistor-MOSFET inverter. As the voltage at the input of the CMOS
device varies between 0 and 5 volts, the state of the NMOS and PMOS varies
accordingly
PROCEDURE:

1. Double click on Microwind and go to file and click new.

2. Select MOS Generator and select PMOS device and click Generate Device.
3. Similarly generate NMOS device and place it.
4. Select Polysilicon from the Palette and connect the gate of PMOS and
NMOS
5. Now connect the two transistors using a metal1 layer from the Palette.
6. Now make connections for input and output using corresponding layers.
7. Choose Vdd(supply) from Palette and place it in the metal 1 and N-well of
PMOS.
8. Choose Vss(ground) from the Palette and place it in the metal 1 of nNMOS.
9. Now provide input, by choosing ‘Add a Clock’ from the Palette, select
assign and place it at the input side.
10. Now output is placed by choosing ‘Visible node symbol’ from the Palette
and click assign to place it at the output port.
11. Save the file and select ‘Run Simulation’ from the Menu bar.
12. Output waveform is generated in a new window.

RESULT:
Date:

EX. NO. 9 DESIGN AND SIMULATE UNIVERSAL GATES LAYOUT

AIM:
To design and simulate NAND gate and NOR gate layouts using Microwind.

TOOLS REQUIRED:
1. MICROWIND V3.1

THEORY:

Fig. CMOS NAND gate

The figure shows a 2-input Complementary MOS NAND gate. It consists of

two series NMOS transistors between Y and Ground and two parallel PMOS
transistors between Y and VDD.If either input A or B is logic 0, at least one of the
NMOS transistors will be OFF, breaking the path from Y to Ground. But at least
one of the pMOS transistors will be ON, creating a path from Y to VDD.

Fig. CMOS NOR gate

A 2-input NOR gate is shown in the figure. The NMOS transistors are in
parallel to pull the output low when either input is high. The PMOS transistors are
in series to pull the output high when both inputs are low, as given in below table.
The output is never left floating.

PROCEDURE:

1. Double click on Microwind and go to file and click new.

2. Select MOS Generator and select PMOS device, type 2 in ‘Nbr of Fingers’
and click Generate Device.
3. Similarly generate NMOS device and place it.
4. Select Polysilicon from the Palette and connect the gates of PMOS and
NMOS
5. Now connect the two transistors using a metal1 layer from the Palette.
6. Now make connections for inputs and output using corresponding layers.
7. Choose Vdd(supply) from Palette and place it in the metal 1 and N-well of
PMOS.
8. Choose Vss(ground) from the Palette and place it in the metal 1 of nNMOS.
9. Now provide inputs, by choosing ‘Add a Clock’ from the Palette, select
assign and place it at the input side.
10. Now output is placed by choosing ‘Visible node symbol’ from the Palette
and click assign to place it at the output port.
11. Save the file and select ‘Run Simulation’ from the Menu bar.
12. Output waveform is generated in a new window.

RESULT:
Date:

EX. NO. 10 DESIGN AND SIMULATE DIGITAL CIRCUITS USING

MICROWIND AND DSCH V3.1
AIM:

To design and simulate digital circuits such as NAND and NOR gates ,
flipflops and counter using Microwind and DSCH V3.1

TOOLS REQUIRED:
1. MICROWIND V3.1
2. DSCH V3.1

THEORY:
NAND GATE:

The figure shows a 2-input Complementary MOS NAND gate. It consists of

two series NMOS transistors between Y and Ground and two parallel PMOS
transistors between Y and VDD. If either input A or B is logic 0, at least one of the
NMOS transistors will be OFF, breaking the path from Y to Ground. But at least
one of the pMOS transistors will be ON, creating a path from Y to VDD. Hence, the
output Y will be high. If both inputs are high, both of the nMOS transistors will be
ON and both of the pMOS transistors will be OFF. Hence, the output will be logic
low.
Truth Table
NOR
GATE:

A 2-input NOR gate is shown in the figure. The NMOS transistors are in
parallel to pull the output low when either input is high. The PMOS transistors are
in series to pull the output high when both inputs are low, as given in below table.
The output is never left floating.
Truth Table

LIPFLOP:

D flip-flop operates with only positive clock transitions or negative clock

transitions. Whereas, D latch operates with enable signal. That means, the output of
D flip-flop is insensitive to the changes in the input, D except for active transition of
the clock signal. The next state equation is Q(t+1)= D.
4-BIT SYNCHRONOUS COUNTER:

A 4-bit synchronous up counter, we will need four flip-flops. These flip-flops

will have the same RST signal and the same CLK signal. Here D flip-flops are used
to design this counter. The 4-bit synchronous up counter should follow the sequence
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0.

PROCEDURE:
1. Open the DSCH2
2. Drag the components like pmos, nmos, voltage source, ground, and LED from
the symbol library.
3. Connect the circuit as in the circuit diagram.
4. Save the circuit & run the simulation Make verilog file go to Microwind and
compile the verilog file saved in DSCH2
5. Compile it and obtain the layout diagram & simulate to get the waveform.

Result:
Date:
Ex No:11 STUDY OF TANNER EDA DESIGN TOOL

AIM : To study Tanner EDA tool for designing, simulating and layout extraction of Integrated
Circuits.

THEORY:
Tanner EDA is a suite of tools for the design of integrated circuits. These tools allow you to enter
schematics, perform SPICE simulations, do physical design (i.e., chip layout), and perform design rule
checks (DRC) and layout versus schematic (LVS) checks. There are 3 tools that are used for this process:

S-edit - a schematic capture tool

T-SPICE - the SPICE simulation engine integrated with S-
edit L-edit - the physical design tool

Using S-Edit (Schematic Entry Tool) & T-SPICE (Analog Simulation Tool)

Example: IV Curves of an NMOS Transistor

S-edit is a schematic entry tool that is used to document circuits that can be driven forward into a
layout of an integrated circuit. It also provides the ability to perform SPICE simulations of the circuits
using a simulation engine called T-SPICE. T-SPICE can be setup and invoked from with in S-edit.

Part 1: Setup your Directory Structure & download Libraries

a) Log onto a computer on 6th floor Cobleigh.

b) You want to create a directory for all of your Tanner EDA projects. You also will need to
download and unzip a set of library & model files from the course website that will be used for
your simulations.

- Create a directory structure named “EELE414_VLSI_Fall2011\Tanner_Projects

c) Go to the course website and download the zip file called “Tanner_Libraries.zip”. Unzip it into
your Tanner Projects directory. This group of files contain the necessary information to enter
components into S-edit (circuit symbols), perform SPICE simulations (models), and do
physical layout (layer definitions, DRC, LVS)

Part 2: Start a New Design & Setup Libraries

a) Start S-Edit:
- Start – All Programs – Tanner EDA – Tanner Tools v12.6 – S-Edit v12.6
b) Start a New Design:

Using the pull down menus, create a new design:

- File – New - New Design

A dialog will appear asking for a design name and location. When you give the name, S- edit
will create a folder of that name in the directory that you provide that will contain all of the
design files. You should give a descriptive name that represents each simulation you will be
running.

- Enter the name “HW03_NMOS_IV_Part1” and browse to

your “EELE414_VLSI_Fall2011\Tanner_Projects” directory

- Click “OK”

c) Create a new Cell

A “cell” is a design element. A cell can contain multiple views such as schematics and
symbols. Cells can be instantiated in other cells. When performing a simulation, we will
typically call the cell “TOP”. When we are testing a circuit, for example an inverter, the
inverter will have its own cell that contains a schematic of the devices and a symbol. The
inverter cell is instantiated in the TOP cell that contains ideal elements such as voltage sources
and probes that are only used for simulation. This allows us to separate the cells that are
actually going to be implemented on the die versus cells that are only used for simulation.

Using the pull down menus, create a new cell view:

- Cell – New View:

- enter the cell name “TOP”. Ensure the design name is “HW03_NMOS_IV_Part1”
and click OK. You can leave the interface and view names “view0”.

A blank schematic page will appear. It is a good idea to save this right now.
d) Enter the symbol libraries:

First, you need to include a library which contains the symbols for all basic
circuit elements such as resistors, NMOS, capacitors, etc… The libraries for all
the basic symbols are in the Tanner_Libraries.zip file you downloaded and
unzipped.

- On the left side of the S-edit screen you’ll see a Libraries window, click on the
“Add” button.

e) Browse to “Libraries\All\All.tanner” and click “OK” You should

see a set of libraries appear

 f) Setup the SPICE Models for the Generic_025 kit.

The libraries that you just added have symbols for NMOS and PMOS transistors. However, all
non-linear components such as MOS transistors require a model to describe their behavior. If
you simply enter an NMOS symbol in your schematic, SPICE will not know what to do
since each NMOS transistor fabricated in a different technology behave differently.

In this example, we will use a transistor technology called “Generic_025”, which represents a
standard, 0.25um CMOS process. You will need to setup the SPICE models for this process
in S-edit. Once you do that, when you enter an NMOS or PMOS transistor, you can then
associate the 0.25um model to that symbol.

Using the pull down menus, setup the SPICE models:

- Setup – SPICE Simulation

- In the dialog that appears, you should highlight “General” on the left.

- On the right, click in the “Library Files” field. This is where you will specify any SPICE
models you will be using in your simulations. Browse & select “Generic_025_Kit\
Generic_025_SPICE_Models_Level1.lib”

- On the right, click in the “SPICE File Name” field. This is where you specify the name and
location of the SPICE Netlist output. Browse to your design directory
“EELE414_VLSI_Fall2011\Tanner_Projects\HW03_NMOS_IV_Part1” and enter the
filename “TOP.sp”.

- On the right, click in the “Simulations Results File Name” field. This is where the results of
the simulation will be written. This file is what the waveform viewer will look for when you
go to plot your results. Browse to your design directory
“EELE414_VLSI_Fall2011\Tanner_Projects\HW03_NMOS_IV_Part1” and enter the
filename “TOP.out”.

- Before you can exit this window, you will need to select an analysis type. We will setup the
details of the analysis later, but for now, just check the “DC Sweep Analysis” and click
“OK” to close the setup window.
Part 3: Enter the Schematic to simulate the IV behavior of an NMOS Transistor

We will be entering the following circuit.

a) Enter the NMOS transistor

- On the left, click on “Devices” in the upper window. This will display all of the
symbols available in this group. You should see all of the components that you can
implement on a CMOS integrated circuit.

- On the bottom left window, click once on “NMOS”. You should see the symbol of
 the NMOS transistor show up in the symbol viewer window at the bottom.

- To place the NMOS, you will click on the “Instance” button. Two things happen when
you click on this button. First, a dialog will appear that will allow you to setup the
parameters for the NMOS. Second, the symbol will attach to your mouse. We will place the
NMOS in the schematic first and then set its properties later. This is an easier way to enter
the device. Click in the schematic window to drop an instance of the NMOS. Hit
the “Esc” button to end the insert-mode.
A note on zooming:

- [Home] = zoom fit

- [-] = zoom out
- [=] = zoom in
- the scroll wheel also zooms in/out.

- To setup the NMOS, click on the NMOS symbol. You will see the properties of
the device on the left. We want to setup the following:

- Model : enter “NMOS”. This model is found in the

Generic_025 library you added

- Name: M1. The SPICE designation for MOS transistors is to have the name start with
an “M”. S-edit automatically appends an M to the name is the final name will be
“MM1” in the TOP.sp file. But it is good practice to name all MOS transistors with
M’s.

- W Set to 2.5u. This is the default.

- L Set to 0.25u. This is the default.

b) Enter a DC source for VGS

- Using the same process you used for the NMOS symbol, enter a
“SPICE_Elements:VoltageSource”. This is a generic voltage source symbol that is configured as a
DC, TRAN, PWL, etc.. in its properties dialog.
- Click on the voltage source and enter the following:

- MasterInterface: DC (this is the default but this is how you would change it
to something else.

- Name: VGS_Source (it is a good idea to use descriptive names)

- V This is where you will set the DC voltage (i.e., 4v, 5v).
However, for this example we will use a parameter instead of a hardcoded value. We will enter a
parameter name here and then set up the parameter later. Enter “VGS_param” for the value
of V. When performing a DC sweep, you must use parameters for the sweep.
 c) Enter a DC source for VDS

- Using the same process as above, enter a DC source for VGS with the following:

- MasterInterface: DC (this is the default but this is how you would change it to something else.

- Name: VDS_Source

-V “VDS_param”

A note on zooming:

- Hold down ALT-M to move a component. While holding these buttons down,
click and drag the components.

- To rotate, click on the device and click the [r] button.

d) Enter Grounds

- Using the same process as above, enter 3 grounds from Misc:Gnd

e) Enter Wires

- You can enter wires by clicking on the “wire” icon at the top

- Enter wires by clicking on a symbol node and then dragging. Enter corners by clicking
once where you want to turn.

- You can label nets using the “Net Label” icon at the top

f) Enter a Current Probe to monitor IDS

- Enter the SPICE_Commands:PrintCurrent component. This doesn’t connect to

anything. You just place it anywhere and then tell it what current to monitor in its
properties dialog.

- In its properties dialog, setup:

Terminal: D (this is the Drain of the NMOS)

Device: MM1 (this is the name of the device. Notice that we called it M1, but S-edit
automatically appends another M to the name. You will only see this once you run
the Netlist.
 Analysis: DC (VERY IMPORTANT TO SELECT THIS!!!!)

Part 4: Setup the Parameters that will be used during the DC sweep analysis

When we entered the VGS and VDS sources, we set their values to “VGS_param” and
“VDS_param”. We now need to setup these parameters.

Using the pull down menus:

- Setup – SPICE Simulations

- On the left, click on “Parameters”

- On the right, click on the “Add Parameters” button (it is in the upper right corner next to the red X)

Enter: Name:
VGS_para
m Value:1V

- On the right, click on the “Add Parameters”

button Enter: Name: VDS_param

Value: 2.5V
We will overwrite these values during our sweep, but the parameters need to exist first.

Part 5: Setup the SPICE DC Sweep Analysis

Using the pull down menus:

- Setup – SPICE Simulations

- On the left, click on “DC Sweep Analysis”

- On the right, enter the following for Source (this is what will be

swept) Source or Parameter Name: VDS_param

Start Value: 0
Stop Value: 2.5
Step: 0.1
Sweep Type: lin

- On the right, enter the following for Source (this is what will be

swept) Source or Parameter Name: VGS_param

Start Value: 1
Stop Value: 1.5
Step: 0.5
 Sweep Type: lin

NOTE: The first parameter you setup in this dialog will be plotted on the independent axis.

Part 6: Simulate the Design

a) First, check you design using the pull down menus:

- Tools – Design Checks (any warnings or errors will be shown at the bottom)

b) Simulate your design:

- Clock on the Green Arrow to start the simulator:

The T-Spice window will appear. If everything is OK, the waveform viewer will also
appear. If everything worked, your waveforms should look like this:

c) View the Netlist:

- In the T-spice window, right click on the file at the bottom and select “Show Netlist”

This will bring up the TOP.sp Netlist that was created and used by the spice engine. This
is a good place to look when you get errors. This is the text based description of what
you entered in S-edit.

d) View the Waveform:

- If the windows viewer did NOT automatically appear, you can click on the file in the
T- spice window and select “Show Waveform”

RESULT:
Date:
Ex. No: 12 DESIGN AND SIMULATE CMOS INVERTING AMPLIFIER USING
TANNER EDA

AIM :To design and simulate CMOS inverter using digital flow with Tanner EDA.

SOFTWARE USED:
 Tanner tool
PROCEDURE :
 Open S Edit 13.0.
 Go to help and then to setup examples.
 View the files in my documents in Tanner EDA folder.
 Create a new folder in Local Disk (‘D’) and name it.
 Then goto File ->New -> New Design.
 Give the design name and browse for it in the local disk (D).
 In libraries window click add and give any name and give browse.
 Then go to my documents ->Tanner EDA -> Tanner tool -> libraries ->All->
open and then press ok.
 Goto cell and select new view and give any name and give the view type as
Schematic and press ok.
 In libraries window select the device for pMOS and nMOS and interface choose
pMOS3 and nMOS3.
 In libraries window select MISC for VDD.
 In general select libraries file and browse.
 Then goto my documents ->Tanner EDA->Tanner tool ->libraries-> models -
>Generic.
 Leave some space and type ‘tt’
 Then select Transient| Fourier analysis and then set the stop time to 1000n.
 Then go to tools and start simulation .
 Select file go to export and export SPICE.
 Then in desktop view the folder CMOS inverter.
THEORY:
The figure shows a CMOS invertor or NOT gate using one nMOS transistor
and one pMOS transistor. The horizontal bar at the top indicates GND when the input A is
zero. The nMOS transistor is off and pMOS transistor is ON. Thus the output y is pulled
up to ‘1’ because it was connected to VDD but not to GND. When A is 1, the nMOS
transistor is ON, pMOS is OFF and y is pulled down to ‘0’.
There are 3 modes:
Vgs< Vt; cutoff.
Vgs>t; Vds<Vgs-Vt linear.
Vgs>Vt;Vds>Vgs-Vt saturation.

Fig. Circuit Diagram

RESULT:
Date:
Ex. No: 13 DESIGN AND SIMULATE CS, CG AND CD AMPLIFIER USING
TANNER EDA

AIM :To design and simulate basic common source, common gate and common drain using
digital flow with Tanner EDA.

SOFTWARE USED:
 Tanner tool

PROCEDURE :
 Open S Edit 13.0.
 Go to help and then to setup examples.
 View the files in my documents in Tanner EDA folder.
 Create a new folder in Local Disk (‘D’) and name it.
 Then goto File ->New -> New Design.
 Give the design name and browse for it in the local disk (D).
 In libraries window click add and give any name and give browse.
 Then go to my documents ->Tanner EDA -> Tanner tool -> libraries ->All->
open and then press ok.
 Goto cell and select new view and give any name and give the view type as
Schematic and press ok.
 In libraries window select the device for pMOS and nMOS and interface choose
pMOS3 and nMOS3.
 In libraries window select MISC for VDD.
 In general select libraries file and browse.
 Then goto my documents ->Tanner EDA->Tanner tool ->libraries-> models -
>Generic.
 Leave some space and type ‘tt’
 Then select Transient| Fourier analysis and then set the stop time to 1000n.
 Then go to tools and start simulation .
 Select file go to export and export SPICE.
THEORY:
Common Source:

Fig. Circuit Diagram

A common-source amplifier is one of three basic single-stage field-effect transistor

amplifier topologies, typically used as a voltage or transconductance amplifier. The signal
enters the gate, and exits the drain. The only terminal remaining is the source. This is a
common-source FET circuit. The common-source (CS) amplifier may be viewed as a
transconductance amplifier or as a voltage amplifier. As a transconductance amplifier, the
input voltage is seen as modulating the current going to the load. As a voltage amplifier,
input voltage modulates the amount of current flowing through the FET, changing the
voltage across the output resistance according to Ohm's law. However, the FET device's
output resistance typically is not high enough for a reasonable transconductance amplifier,
nor low enough for a decent voltage amplifier. Another major drawback is the amplifier's
limited high-frequency response.

Common Drain:

Fig. Circuit Diagram

 Common drain amplifier is a source follower or buffer amplifier circuit using a
MOSFET. The advantage of this circuit is that the MOSFET can provide current and power
gain; the MOSFET draws no current from the input. It provides low output impedance to
any circuit using the output of the follower, meaning that the output will not drop under
load. Its output impedance is not as low as that of an emitter follower using a bipolar
transistor but it has the advantage that the input impedance is infinite. The MOSFET is in
saturation, so the current across it is determined by the gate source voltage. Since a current
source keeps the current constant, the gate-source voltage is also constant.

SCHEMATIC OF COMMON GATE:

RESULT:
Thus the characteristics of Common gate, source, drain amplifier have been analyzed.
Date:
EX:NO:14 SCHEMATIC SIMULATION OF DIFFERENTIAL
AMPLIFIER USING TANNER

AIM :To design and simulate differential amplifier using Tanner EDA.

SOFTWARE USED:
 Tanner Tool
PROCEDURE:
 Go to tanner and open s-edit.
 Help and link tutorial and set up the library file.
 Go to file click new design and give file name and the browse and save it in
appropriate folder.
 Then go to library and browse my computer and then click ok.
 Go to all click new view give cell name and ok.
 Go to library and select appropriate devices and SPICE element and draw the
schematics.
 Then select the wire and give connection to the schematic and select i/o port.
 Then select the AL analysis and give the start, stop and sweep time.
 Go to tools and give start simulation.
 The output waveform obtained is for common mode.
 The go to schematic and change the phase to 1800 and then simulate.
 This output waveform is differential mode.
 Then export this simulation to the particular folder.

THEORY:

The differential pair stress current to two outputs. If the input voltages are equal then
the output currents are equal. If the inputs are substantially higher than the other allows
draws all of the current. Hence differential pair is widely used because they are insensitive
to many noise sources. For this reason, differential pairs are used in sense Amplifier on
RAM built line circuitry. Differential pairs are earliest to analysis finding input voltage
different from the output current difference. In analog circuits the transistors normally
operate in the saturation.
SCHEMATIC OF DIFFERENTIAL AMPLIFIER:

RESULT:
Thus the characteristics of differential amplifier like Gain, CMRR and
bandwidth has been analyzed.