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    ETE Practice Questions Set - 2

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    Nikhil Patel

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    ETE Practice Questions Set - 2

    Uploaded by

    Nikhil Patel
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    ETE Practice Questions Set_2

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    10 views2 pages

    ETE Practice Questions Set - 2

    Uploaded by

    Nikhil Patel

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    © All Rights Reserved
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    Practice Set -2 for COA ETE Examination

    Q.1 Write short notes on the following:


    a) Associative Memory
    b) Auxiliary Memory

    Q.2 Distinguish between Strobe Control and Handshaking techniques for asynchronous data transfer.
    Q.3 What is locality of Reference phenomena used in Cache Memory? What are the cache mapping
    techniques? Explain Direct Mapping technique in detail.
    Q.4 Explain different modes of transfer: Programmed I/O, Interrupt-driven I/O, and DMA (Direct
    Memory Access)?
    Q.5 Describe about the components of a magnetic disk and establish the relationships between the
    following terms concerning disks in a formula: access time, seek time, rotational delay, and transfer
    time.
    Q.6 Discuss paging and segmentation concept with respect to Virtual Memory.
    Q.7 Discuss the various types of pipeline hazards and their consequences.
    Q.8 Write an assembly language program for addition of two 8-bit nos.
    Q.9 Write an assembly language program for subtraction of two 8-bit nos.
    Q.10 Demonstrate the block diagrams and functionalities of integrated circuit chips for RAM and ROM.
    Q.11 Describe the concept of daisy-chaining. Devise a single-stage daisy-chaining priority logic circuit
    and elucidate its operation, detailing how it manages interrupt-initiated I/O requests.
    Q.12 A cache memory has access time of 40 ns and main memory access time is 180 ns. Calculate the
    average access time of CPU if the hit ratio is 70%.
    Q.13 A block set associative cache consists of a total of 64 K blocks divided into 4 block sets. The main
    memory contains 4096 blocks, each consisting of 128 words.
    a) Calculate no. of bits are there in a main memory address?
    b) Calculate no. of bits are there in each of the TAG, SET and WORD fields?

    Q.14 A computer uses RAM chips of 1024x1 capacity.


    a) How many chips are needed to provide a memory capacity of 1024 bytes?
    b) How many chips are needed to provide a memory capacity of 16K bytes?

    Q.15 A non-pipeline system takes 50 ns to process a task. The same task can be processed in six -
    segment pipeline with a clock cycle of 10 ns. Determine the speedup ratio of the pipeline for 100 tasks.
    What is the maximum speed up that can be achieved?
    Q.16 A computer has 16 MB main memory and 64 KB cache. The block size is 16 bytes. Determine
    the number of cache lines does the computer have and number of blocks does the main memory have.
    Explain how a given address is retrieved from the memory system.
    Q.17 Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32-
    bit addresses. Find the number of bits needed for cache indexing and the number of tag bits are
    respectively.
    Q.18 Formulate the logical and physical address formats for the following specifications: The logical
    address space in a computer system consists of 128 segments. Each segment can have up to 32 pages
    of 4K words in each. Physical memory consists of 4K blocks of 4K words in each.
    Q.19 Explain the concept of Arithmetic Pipeline with the help of a numerical example.
    Q.20 Design a six-segment instruction pipeline for a computer. Specify operations to be performed in
    each segment.
    Q.21 Design parallel priority interrupt hardware for a system with four interrupt sources using priority
    encoder.
    Q.22 Explain the Direct Memory Transfer (DMA) techniques used for data transfer in a computer
    system in detail.
    Q.23 Differentiate between the following:
    a) RISC vs CISC Processor
    b) Hardwired Control Unit vs Micro-programmed Control Unit
    c) Vectored and Non- vectored Interrupts
    d) Write -Through and Write Back policy of Cache
    Q.24 Explain the following concepts:
    a) Memory Hierarchy
    b) Memory Interleaving
    c) Pipelining
    Q.25 Compare and contrast 2 and 2.5 D memory Organization.

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