VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
ENGINEERING

QUESTION BANK

V SEMESTER

EC8552-COMPUTER ARCHITECTURE AND ORGANIZATION

Regulation – 2017
Academic Year 2019 – 2020

Prepared by

Ms. G. Sangeetha, Assistant Professor/CSE Mr. G.

Kumaresan, Assistant professor/CSE Ms. A. Lalitha,
Assistant professor/CSE
 VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur-603203
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
QUESTION BANK
SUBJECT : EC8552-COMPUTER ARCHITECTURE AND ORGANIZATION
SEM/YEAR: V/III

UNIT I COMPUTER ORGANIZATION & INSTRUCTIONS

Basics of a computer system: Evolution, Ideas, Technology, Performance, Power wall, Uniprocessors to
Multiprocessors. Addressing and addressing modes. Instructions: Operations and Operands, Representing
instructions, Logical operations, control operations.
PART-A
Q.No Questions BT Competence
Level
1 Express the equation for the dynamic power required per BTL 2 Understanding
transistor.
2 Identify general characteristics of Relative addressing mode with BTL 4 Analyzing
an example.
3 List the eight great ideas invented by computer architects. BTL 1 Remembering
4 Tabulate are the components of computer system. BTL 1 Remembering
5 Distinguish Pipelining from Parallelism. BTL 2 Understanding
6 Interpret the various instructions based on the o er tions they BTL 2 Understanding
perform and give one example to each category.
7 Differentiate DRAM and SRAM. BTL 4 Analyzing
8 Give the components of a computer system and list their BTL 2 Understanding
functions.
9 What is the MIPS code for the stateme t f= (g+h)-(i+j). BTL 1 Remembering
10 Calculate throughput and r sponse t me. BTL 3 Applying
11 Compose the CPU performance quation. BTL 6 Creating
12 Measure the performance of the comput rs: BTL 5 Evaluating
If computer A runs a p og am in 10 seconds, and computer B
runs the same program in 15 seconds, how much faster is A over
B?
13 Formulate the equation of CPU execution time for program.
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BTL 6 Creating
14 State the need for indirect addressing mode. Give an example. BTL 1 Remembering
15 Show the formula for CPU clock cycles required for a program. BTL 3 Applying
16 Define Stored Program Concept. BTL 1 Remembering
17 Name the different addressing modes. BTL 1 Remembering
18 Compare multi-processor and uniprocessor. BTL 4 Analyzing
19 Illustrate relative addressing mode with example. BTL 3 Applying
20 Consider the following performance measurements for a program BTL 5 Evaluating
Measurement Computer A Computer B
Instruction 10 billion 8 billion
Count
Clock rate 4GHz 4GHz
CPI 1.0 1.1
Which computer has the higher MIPS rating
 PART B
1 i).Summarize the eight great ideas of computer Architecture. (7) BTL 5 Evaluating
ii). Explain the technologies for Building Processors. (6)
2 List the various components of computer system and explain (13) BTL 1 Remembering
with neat diagram.
3 i).Define addressing mode. (4) BTL 1 Remembering
ii).Describe the basic addressing modes for MIPS and give one (9)
suitable example instruction to each category.
4. Examine the operands and operations of computer hardware. (13) BTL 1 Remembering
5 i).Discuss the logical operations and control operations of (7) BTL 2 Understanding
computer.
ii). Express the concept of Powerwall processor. (6)
6 Consider three different processors P1, P2, and P3 executing the BTL 4 Analyzing
same instruction set. P1 has a 3 GHz clock rate and a CPI of 1 5
P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4 0 GHz
clock rate and has a CPI of 2.2.
i).Which processor has the highest performance expressed in (3)
instructions per second?
ii).If the processors each execute a program in 10 seconds, .find (5)
the number of cycles and the number of instructions?
iii).We are trying to reduce the execution time by 30% b t this (5)
leads to an increase of 20% in the CPI. Wh t clock r te should
we have to get this time reduction?
7 Assume a program requires the execution of 50 × 106 FP BTL 3 Applying
instructions,110 × 106 INT i structio s, 80 × 106 L/S
instructions, and 16 × 106 branch struct o s The CPI for each
type of instruction is 1, 1, 4, and 2, respect vely. Assume that the
processor has a 2 GHz clock rate.
i).By how much must we improve the CPI of FP instructions if (4)
we want the program to run two tim s faster?
ii).By how much must we imp ove the CPI of L/S instructions? (4)
iii).By how much is the x cution time of the program improved (5)
if the CPI of INT and FP Inst uctions are reduced by 40% and
the CPI of L/S and Branch is reduced by 30%?
8 Recall how performance is calculated computer system and (13) BTL 2 Understanding
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derive the necessary performance equations.
9 i).Formulate the performance of CPU. (7) BTL 6 Creating
ii).Compose the factors that affect performance. (6)
10 i).Illustrate the following sequence of instructions and identify (7) BTL 3 Applying
the addressing modes used and the operation done in every
instruction
(1) Move (R5)+, R0
(2) Add(R5)+, R0
(3) Move R0, (R5)
(4) Move 16(R5),R3
(5) Add #40, R5 (6)
ii).Calculate which code sequence will execute faster according
to execution time for the following conditions:
Consider the computer with three instruction classes and CPI
measurements as given below and instruction counts for each
 instruction class for the same program from two different
compilers are given. Assume that the computer’s clock rate is
1GHZ.
Code from CPI for the instruction class
A B C
CPI 1 2 3
Code from CPI for the instruction class
A B C
Compiler1 2 1 2
Compiler2 2 1 1
11 Consider two different implementation of the same instruction (13) BTL 1 Re embering
set architecture, The instruction can be divided into four classes
according to their CPI ( class A,B,C and D). P1 with clock rate
2.5 Ghz and CPI s of 1,2,3, and 3 respectively and P2 with lock
rate 3 Ghz and CPI s of 2,2,2and 2 respectively. Given a
6
program with a dynamic instruction count of 1.0*10 instru tion
divided into classes as follows: 10% class A, 20% class B, 50%
class C, and 20% class D, which implementation is faster? What
is the global CPI for each implementation? Find the clock cyc es
required in both cases.
12 i). Compare uni-processors and multi- processors. (3) BTL 4 Analyzing
ii). Analyze how instructions that involve decision m king are (10)
executed with an example.
13 Analyze the various instruction formats and illustrate with an (13) BTL 4 Analyzing
example.
14 (i)With suitable examples, Summar ze the compilation of (8) BTL 2 Understanding
assignment statements into MIPS.
(ii)Translate the following C code to MIPS assembly code .Use a (5)
minimum number of instruct ons. Assume that I and k
correspond to register $s3 and $s5 and the base of the array save
is in $s6.What is the MIPs ass mbly code corresponding to this
is C segment
While(save[i]==k) i+=1;
PART C
1 Assume that the variables f and g are assigned to register $s0 and (15) BTL 6 Creating
$s1 respectively. Assume that base address of the array A is in
register $s2. Assume f is zero initially.
f- -g – A[4]
A[5]=f + 100
Translate the above C statement into MIPS code . how many
MIPS assembly instructions are needed to perform the C
statements and how many different registers are needed to carry
out the C statements ?
2 Integrate the eight ideas from computer architecture to the BTL 6 Creating
following ideas from other fields: (5)
i). Assembly lines in automobile manufacturing. (5)
ii). Express elevators in buildings. (5)
iii).Aircraft and marine navigation systems that incorporate wind
information.
 3 Evaluate a MIPS assembly instruction in to a machine (15) BTL 5 Evaluating
instruction, for the add $to, $s1,$s2 MIPS instruction.
4 Explain the steps to convert the following high level language (15) BTL 5 Analyzing
such as C into a MIPS code.
a=b+e; c=b+f;
UNIT II -ARITHMETIC
Fixed point Addition, Subtraction, Multiplication and Division. Floating Point arithmetic, High performance
arithmetic, Subword parallelism
PART-A
Q.No Questions BT Co petence
Level
1 Calculate the following: Add 510 to 610 in binary and Subtract -610 BTL 3 Applying
from 710 in binary.
2 Analyze overflow conditions for addition and subtraction. BTL 4 Analyzing
3 Construct the Multiplication hardware diagram. BTL 3 Applying
4 List the steps of multiplication algorithm. BTL 1 Remembering
5 What is meant by ALU fast multiplication? BTL 1 Remembering
6 Subtract (11011)2 – (10011)2 using 1’s complement and 2’s BTL 2 Understanding
complement method.
7 Illustrate scientific notation and normalization with example. BTL 3 Applying
8 Perform X-Y using 2’s complement arithmetic for the given two BTL 4 Analyzing
16-bit numbers X=0000 1011 1110 1111 and Y=1111 0010 1001
1101.
9 Contrast overflow and underflow with exam les. BTL 2 Understanding
10 State the rules to add two integers. BTL 6 Creating
11 Name the floating point instruct o s MIPS. BTL 1 Remembering
12 Formulate the steps of floating po t add t on. BTL 6 Creating
13 Evaluate the sequence of floating po nt mult plication. BTL 5 Evaluating
14 Define scientific notation and normaliz d notation. BTL 1 Remembering
15 Express the IEEE 754 floating point format. BTL 2 Understanding
16 State sub-word parallelism and the data path CPU. BTL 1 Remembering
17 Interpret single precision floating point number representation BTL 2 Understanding
with example and the ep esentation of double precision floating
point number.
18 Divide 1,001,010 by 1000 .
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19 Describe edge triggered clocking. BTL 1 Remembering
20 For the follo ing MIPS assembly instructions above, decide the BTL 5 Evaluating
corresponding C statement? add f, g, h & add f, i, f
PART-B
1 i).Discuss the multiplication algorithm its hardware and its (6) BTL 2 Understanding
sequential version with diagram.
ii).Express the steps to Multiply 2*3. (7)
2 Illustrate the multiplication of signed numbers using Booth (13) BTL 3 Applying
algorithm. A=(-34)10=(1011110)2 and B=(22)10=(0010110)2
where B is multiplicand and A is multiplier.
3 Describe about basic concepts of ALU design. (13) BTL 1 Remembering
4 Develop algorithm to implement A*B. Assume A and B for a pair (13) BTL 6 Creating
of signed 2’s complement numbers with values: A=010111,
B=101100
5 i).State the division algorithm with diagram and examples. (6) BTL 1 Remembering
ii).Divide 00000111 by 0010. (7)
6 i).Express in detail about Carry looks ahead Adder. (8) BTL 2 Understanding
ii).Divide(12)10 by (3)10 (7)
7 Point out how ALU performs division with flow chart and block (13) BTL 4 Analyzing
diagram.
8 i).Examine with a neat block diagram how floating point addition (10) BTL 1 Remembering
is carried out in a computer system.
ii).Give an example for a binary floating point addition. (3)
9 Tabulate the IEEE 754 binary representation of the number- BTL 1 Re embering
0.75 10
i).Single precision. (6)
ii).Double precision. (7)
10 i).Design an arithmetic element to perform the basic floating (7) BTL 2 Understanding
point operations.
ii).Discuss sub word parallelism. (6)
11 i).Explain floating point addition algorithm with diagram (6) BTL 5 Evaluating
ii).Assess the result of the numbers (0.5)10 and (0.4375)10 using (7)
binary Floating point Addition algorithm.
12 Calculate using single precision IEEE 754 representation. BTL 4 Analyzing
i). 32.75 (6)
ii).18.125 (7)
13 Arrange the given number 0.0625 BTL 4 Analyzing
i). Single precision. (6)
ii). Double precision formats. (7)
14 Solve using Floating point mult pl cat on algorithm BTL 3 Applying
10 -5
i). A= 1.10 10 X 10 B= 9.200X10 (7)
ii). 0.5 10 X 0.4375 10 (6)
PART C
1 Create the logic circuit for CLA. What are the disadvantages of (15) BTL 6 Creating
Ripple carry addition and how it is ov rcome in carry look ahead
adder?
Evaluate the sum of 2 6125 * 101 and 4.150390625 * 101 by (15) BTL 5 Evaluating
hand, assuming A and B are storedthe 16-bit half precision.
2. Assume 1 guard, 1 round bit and 1 sticky bit and round to the
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nearest even. Show all the steps.

3 Summarize 4 bit numbers to save space, which implement the (15) BTL 5 Evaluating
multiplication algorithm for 00102 , 00112 with hardware design.
4 Design 4 bit version of the algorithm to save pages, for dividing (15) BTL 6 Creating
000001112 by 00102 with hardware design.
UNIT III- THE PROCESSOR
Introduction, Logic Design Conventions, Building a Datapath - A Simple Implementation scheme - An
Overview of Pipelining - Pipelined Datapath and Control. Data Hazards: Forwarding versus Stalling, Control
Hazards, Exceptions, Parallelism via Instructions.
PART-A
Q.No Questions BT Competence
Level
1 Express the truth table for AND gate and OR gate. BTL 2 Understanding
2 Define hazard. Give an example for data hazard. BTL 2 Understanding
3 Recall pipeline bubble. BTL 1 Remembering
4 List the state elements needed to store and access an instruction. BTL 1 Remembering
5 Describe the main idea of ILP. BTL 2 Understanding
6 Distinguish the hazards with respect to processor function. BTL 2 Understanding
7 Name the use of different logic gates. BTL 1 Remembering
8 Evaluate branch taken and branch not taken in instruction BTL 5 Evaluating
execution.
9 State the ideal CPI of a pipelined processor. BTL 1 Remembering
10 Design the instruction format for the jump instruction. BTL 6 Creating
11 Classify the different types of hazards with examples. BTL 4 Analyzing
12 Illustrate the two steps that are common to implement any type of BTL 3 Applying
instruction.
13 Assess the methods to reduce the pipeline stall. BTL 5 Evaluating
14 Tabulate the use of branch prediction buffer. BTL 1 Remembering
15 Show the 5 stages pipeline. BTL 3 Applying
16 Point out the concept of exceptions. Give one examp e of MIPS BTL 4 Analyzing
exception.
17 What is pipelining? BTL 1 Remember
18 Illustrate how to organize a multiple issue processor? BTL 3 Applying
19 Neatly sketch three primary units of dynamically sched led BTL 4 Analyzing
pipeline.
20 Generalize Exception. Give one example for MIPS exception. BTL6 Creating
PART-B
1 Discuss the basics of logic design conventions. (13) BTL 2 Understanding
2 i) State the MIPS implementation in detail with necessary (7) BTL 1 Remembering
multiplexers and control lines.
ii) Examine and draw simple MIPS datapath with the control
unit and the execution of ALU nstruct ons. (6)
3 i).Define parallelism and its typ s. (3) BTL 1 Remembering
ii).List the main charact ristics and limitations of Instruction level (10)
parallelism.
4 Design and develop an inst uction pipeline working under various (13) BTL 6 Creating
situations of pipeline stall
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5 i).What is data hazard? (3) BTL 1 Remembering

ii). Explain stalls ith neat diagrams and suitable examples. (10)
6 i).Summarize the speculation scheme. (3) BTL 2 Understanding
ii).Distinguish static and dynamic techniques for speculation. (10)
7 i).Differentiate sequential execution and pipelining. (3) BTL 4 Analyzing
ii). Explain the process of building single data path with neat (10)
diagram.
8 Recommend the techniques for BTL 5 Evaluating
i).Dynamic branch prediction. (7)
ii).Static branch prediction. (6)
9 Examine the approaches would you use to handle exceptions in (13) BTL 3 Applying
MIPS.
10 i).Analyze the hazards caused by unconditional branching (7) BTL 4 Analyzing
statements and pipelining a processor using an example.
ii).Describe operand forwarding in a pipeline processor with a (6)
diagram.
 11 Express the simple data path with control unit and modified data (13) BTL 2 Understanding
path to accommodate pipelined executions with a diagram.
12 With a suitable set of sequence of instructions show what happens (13) BTL 3 Applying
when the branch is taken, assuming the pipeline is optimized for
branches that are not taken and that we moved the branch
execution to the ID stage.
13 i) Define multiple issue. (3) BTL 1 Remembering
ii) Differentiate static and dynamic multiple issues. (10)
14 i).Explain single cycle and pipelined performance with examples. (7) BTL 4 Analyzing
ii).Point out the advantages of pipeline over single cycle and (6)
limitations of pipelining a processor’s datapath. Suggest the
methods to overcome the later part
PART C
1 Assume the following sequence of instructions are executed on a BTL6 Creating
5 stage pipelined processor
Or r1,r2,r3
Or r2,r1,r4
Or r1,r1,r2
i) Indicate dependences andrejinpaultheirtype. Indicate hazards and add NOP instructions to
elimin te them. (5)
ii) Assume there is no forwarding this pipelined processor. (5)

iii) Assume there is a full forwarding .Indic te h z rd nd add NOP (5)

instructions to eliminate them.

2 Consider the following code segment C: A=b+e; c=b+f; Here (15) BTL 5 Evaluating
is the generated MIPS code for this segme t, assuming all
variables are in memory and are addressable as off sets from $t0:
lw $t1, 0($t0)
lw $t2, 4($t0)
add $t3, $t1, $t2
sw $t3, 12($t0)
lw $t4, 8($t0)
add $t5, $t1, $t4
sw $t5, 16($t0)
Find the hazards in the preceding code segment and reorder the
instructions to avoid any pipeline stalls.
3 Consider the follo ing loop: BTL 5 Evaluating
Loop: lw r1,0(r1)
and r1,r1,r2
lw r1,0(r1)
lw r1,0(r1)
beq r1,r0,loop
Assume that perfect branch prediction is used (no stalls) that there
are no delay slots, and that the pipeline has full forwarding
support. Also assume that many iterations of this loop are
executed before the loop exits.
i).Assess a pipeline execution diagram for the third iteration of (8)
this loop.
ii).Show all instructions that are in the pipeline during these (7)
cycles (for all iterations).
 4 Plan the pipelining in MIPS architecture and generate the (15) BTL 6 Creating
exceptions handled in MIPS.
UNIT IV- MEMORY AND I/O ORGANIZATION
Memory hierarchy, Memory Chip Organization, Cache memory, Virtual memory. Parallel Bus
Architectures, Internal Communication Methodologies, Serial Bus Architectures, Mass storage, Input and
Output Devices
PART-A
Q.No Questions BT Competence
Level
1 Distinguish the types of locality of references. BTL 2 Understanding
2 Define the structure of memory hierarchy in a typical computer BTL 1 Re embering
system and draw its diagram.
3 Give how many total bits are required for a direct mapped cache BTL 2 Understanding
with 16KB of data and 4-word blocks, assuming a 32 bit address
4 Compare and contrast SRAM and DRAM. BTL 4 Analyzing
5 What is miss penalty? BTL 1 Remembering
6 Describe Rotational Latency. BTL 1 Remembering
7 State is direct-mapped cache. .
BTL 1 Remembering
8 Evaluate Hit Ratios and Effective Access Times in cache BTL 5 Evaluating
9 Formulate Fragmentation in virtual memory BTL 6 Creating
10 Analyze the writing strategies in cache memory. BTL 4 Analyzing
11 Integrate the functional steps required in n instruction cache BTL 6 Creating
miss.
12 State hit rate and miss rate. BTL 1 Remembering
13 Summarize the various block placeme t schemes in cache BTL 2 Understanding
memory.
14 Identify the purpose of Dirty/Mod f ed b t Cache memory. BTL 1 Remembering
15 Point out the use of parallel bus arch tecture? BTL 4 Analyzing
16 Show the role of TLB in virtual m mory. BTL 3 Applying
17 Illustrate the advantages of virtual m mory. BTL 3 Applying
18 Assess the use of Ove lays m mory. BTL 5 Evaluating
19 Differentiate Paging and segmentation. BTL 2 Understanding
20 Demonstrate the sequence of events involved in handling Direct BTL 3 Applying
Memory Access.
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PART-B
1 i).Define parallelism and its types. (7) BTL 1 Remembering
ii).List the main characteristics and limitations of Instruction level (6)
parallelism.
2 i).Define virtual memory and its importance. (7) BTL 2 Understanding
ii).Examine TLB ith necessary diagram .What is its use? (6)
3 i).List the various memory technologies and examine its (7) BTL 2 Understanding
relevance in architecture design.
ii). Identify the characteristics of memory system. (6)
4 Apply how Internal Communication Methodologies is useful in (13) BTL 3 Applying
developing computer architecture.
5 i).Demonstrate the DMA controller. Discuss how it improves the (7) BTL 1 Remembering
overall performance of the system.
ii).Illustrate how DMA controller is used for direct data transfer (6)
between memory and peripherals?
 6 Point out the need for cache memory. Explain the following three (13) BTL 4 Analyzing
mapping methods with examples.
i). Direct.
ii).Associative.
iii).Set associative.
7 Evaluate the features of Bus Arbitration-Masters and Slaves. (13) BTL 5 Evaluating
8 Generalize the Bus Structure, Protocol, and Control in Parallel (13) BTL 6 Creating
Bus Architecture
9 i).Classify the types of memory chip organization. (7) BTL 4 Analyzing
ii).Analyze the advantages of cache and virtual memory (6)
10 Elaborate in detail about the following in Parallel Bus
Architectures (7) BTL 1 Re embering
i). The Synchronous Bus (6)
ii). The Asynchronous Bus
11 i).Give the advantages of cache. (6) BTL 4 Analyzing
ii).Identify the basic operations of cache in detail with diagram
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(7)
12 Describe the principle approaches of Serial Bus Archite tures (13) BTL 1 Remembering
with necessary diagrams.
13 Illustrate the following in detail BTL 3 Applying
i). Magnetic Disks (5)
ii). Magnetic Tape (4)
iii). Optical Disks (4)
14 Discuss the following in detail BTL 2 Understanding
i). Input Devices. (7)
ii). Output Devices. (6)
PART C
1 Generalize the merits and demer ts of Parallel Bus Architectures, (15) BTL 6 Creating
Bridge-Based Bus Architectures and Ser al Bus Architectures.
2 For a direct mapped cache d sign with a 32 bit address, the BTL 5 Evaluating
following bits of the add ss us d to access the cache.
Tag : 31-10 Index: 9-5 Offs t: 4-0
i). Judge what is the cache block size? (5)
ii).Decide how many ent ies does the cache have? (5)
iii).Assess what is the ratio between total bits required for such a (5)
cache implementation over the data storage bits?
3 Develop methods to constructing large RAMS from small RAMS (15) BTL 6 Creating
and commercial memory modules
4 Summarize the virtual memory organization followed in digital (15) BTL 5 Evaluating
computers.
UNIT V- ADVANCED COMPUTER ARCHITECTURE
Parallel processing architectures and challenges, Hardware multithreading, Multicore and shared memory
multiprocessors, Introduction to Graphics Processing Units, Clusters and Warehouse scale computers -
Introduction to Multiprocessor network topologies.
PART-A
Q.No Questions BT Competence
Level
1 Describe the main idea of Parallel processing architectures. BTL 2 Understanding
2 Illustrate how to organize a clusters. BTL 3 Applying
3 List the network topologies in parallel processor. BTL 1 Remembering
4 Analyze the main characteristics of SMT processor. BTL 4 Analyzing
5 Quote the importance of Graphics Processing Units. BTL 1 Remembering
6 Define multicore microprocessor. BTL 1 Remembering
7 Express Warehouse scale computers. BTL 2 Understanding
8 State the overall speedup if a webserver is to be enhanced with a BTL 1 Remembering
new CPU which is 10 times faster on computation than an old
CPU .The original CPU spent 40% of its time processing and
60% of its time waiting for I/O.
9 Differentiate between SIMD and MIMD. BTL 2 Understanding
10 Show the performance of cluster organization. BTL 3 Applying
11 Compare SMT and hardware multithreading. BTL 5 Evaluating
12 Identify the Flynn classification and give an example for each BTL 1 Re embering
class in Flynn’s classification.
13 Integrate the ideas of multistage network and cross bar network BTL 6 Creating
14 Discriminate UMA and NUMA. BTL 5 Evaluating
15 Describe fine grained multithreading. BTL 1 Remembering
16 Express the need for instruction level parallelism. BTL 2 Understanding
17 Formulate the various approaches to hardware multithreading .
BTL 6 Creating
18 Categorize the various multithreading options. BTL 4 Analyzing
19 Compare fine grained multithreading and coarse grained BTL 4 Analyzing
multithreading.
20 Classify shared memory multiprocessor b sed on the memory BTL 3 Applying
access latency.
PART-B

1 i).Define parallelism and its types. (4) BTL 1 Remembering

ii).List the main characteristics and l m tat ons of Instruction level (9)
parallelism.
2 i).Give the software and hardware techniques to achieve (4) BTL 2 Understanding
Instruction level parall lism.
ii).Summarize the facts or chall ng s faced by parallel processing i (9)
enhancing computer a chitectu .
3 Express in detail about hardware multithreading. (13) BTL 2 Understanding
4 Apply your kno ledge on graphics processing units and explain
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(13) BTL 3 Applying
how it helps computer to improve processor performance.
5 Describe data level parallelism in BTL 1 Remembering
i).SIMD. (6)
ii).MISD. (7)
6 i).Point out how ill you classify shared memory multi-processor (7) BTL 4 Analyzing
based on memory access latency.
ii).Compare and contrast Fine grained, Coarse grained (8)
multithreading and Simultaneous Multithreading.
7 Evaluate the features of Multicore processors. (13) BTL 5 Evaluating
8 i).Classify the types of multithreading. (9) BTL 4 Analyzing
ii).Analyze the advantages in multithreading. (4)
9 Formulate the classes in Flynn’s Taxonomy of computer (13) BTL 6 Creating
Architecture classification with example.
10 Elaborate in detail about the following
 i).SISD. (8) BTL 1 Remembering
ii).MIMD (5)
11 Explain simultaneous Multithreading with example. (13) BTL 4 Analyzing
12 Describe the four principle approaches to multithreading with (13) BTL 1 Remembering
necessary diagrams.
13 Illustrate the following in detail BTL 3 Applying
i). Clusters (7)
ii). Wharehouse scale computers (6)
14 Discuss the multiprocessor network topologies in detail. (13) BTL 2 Understanding
PART C
1 Evaluate the below C code using MIMD and SIMD machine as (15) BTL 5 Evaluating
efficient as possible:
For(i=0;i<2000;i++)
For(j=0;j<3000;j++) rejinpaul
X_array[i][j]=y_array[j][i]+200;
2 Write down a list of your daily activities that you typica y do on (15) BTL 6 Creating
a weekday. For instance get out of bed, take a shower, get
dressed, eat breakfast, brush your teeth, dry yo r hair etc
(minimum ten activities). Which of these activities can be done in
form of parallelism. For each activity discuss if they are working
in parallel, but if not, why they are not. Estim te how m ch
shorter time it will take to complete all the ctivities if it is done
in parallel.
3 Consider the following portions of two different programs BTL 6 Creating
running at the same time on four rocessors a symmetric
multicore processor (SMP). Assume that before this code is run,
both x and y are 0?
Core 1: x=2;
Core 2: y=2;
Core 3: w= x + y +1;
Core 4: z= x + y;
i. What if all the possible sulting values of w,x,y,z ? For each (8)
possible outcomes, explain how we might arrive at those values.
ii. Develop the execution more deterministic so that only one set (7)
of values is possible?
4 Summarize the merits and demerits of clusters and warehouse (15) BTL 5 Evaluating
scales computer.