EXP NO: 01

Implement a Parameterized simple FIFO with queue Inputs:

data_in, w_fifo, r_fifo; Outputs: empty, full, data_out.
DATE: Manage them with built in methods and show the output.

AIM:
To design and implement a parameterized First-In-First-Out (FIFO) queue
using System Verilog. This FIFO queue will handle data storage and retrieval in the
sequence it is received, essential for sequential data processing in digital systems.

APPARATUS REQUIRED:

Sl. List of components Quantity

No.

1 Cadence software 1

2 Personal computer 1

PRECAUTIONS:

Make sure that there is no syntax and semantic error

PROCEDURE:

1. Double click the terminal shortcut from desktop.

2. The window appears with [root@ local host ~] # after this type the
following commands:

3. cd cadence_db
4. csh
5. source cshrc1
6. NCO/rclabs/rtl

10
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 7. gedit filename.sv
8. Press enter. A window appears type the program and save it.
9. Open the terminal window and press ctrl+C.
10. Type the command as ncvlog –mess and press enter. The program is
compiled.
11. Type the command as gedit filename_tb.sv. A
window appears type the test bench program and save it.
12. Compile it by typing the command nco filename_tb.sv
–mess and press enter.
13. To run the program type the command as
i. ncelab filename(without extension) –access +rwc –mess
14. Similarly run the test bench program.

15. To simulate the test bench program, type the

command ncsim testbench file name(without
extension) –gui. A window appears.
16. Select the nco_output and select all the inputs and outputs.
17. Right click and select send to waveform window.
18. Click run/continue netlist button and after some timeperiod stop it.
19. The digital domain output is displayed.
20. In nco_output right click and select trace-> analog sample and hold.
21. The analog domain output is displayed.

11
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
PROGRAM:

//Design_code

// Function to calculate the ceiling of log2

function int clog2(input int value);
int result;
begin
result = 0;
while (value > 1) begin
value = (value + 1) >> 1; // Divide by 2
result = result + 1;
end
return result;
end
endfunction

module fifo #(
parameter DATA_WIDTH = 8, // Width of the data
parameter FIFO_DEPTH = 16 // Depth of the FIFO
)(
input logic clk,
input logic rst_n,
input logic [DATA_WIDTH-1:0] data_in,
input logic w_fifo, // Write enable
input logic r_fifo, // Read enable
output logic empty, // FIFO empty flag
output logic full, // FIFO full flag
output logic [DATA_WIDTH-1:0] data_out //
Data output );

// Internal storage for FIFO

logic [DATA_WIDTH-1:0] fifo_mem[FIFO_DEPTH-1:0];
logic [clog2(FIFO_DEPTH)-1:0] wr_ptr, rd_ptr; // Write and
read pointers logic [clog2(FIFO_DEPTH):0] count; // Count of
items in FIFO

// Initialize pointers and count

initial begin
wr_ptr = 0;
rd_ptr = 0;
count = 0;
end

// Write and Read operation

always@(posedge clk or negedge rst_n) begin

12
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 if (!rst_n) begin
wr_ptr <= 0;
rd_ptr <= 0;
count <= 0;
end else begin
// Write operation
if (w_fifo && !full) begin
fifo_mem[wr_ptr] <= data_in; // Write data to FIFO wr_ptr <=
(wr_ptr + 1) % FIFO_DEPTH; // Increment write pointer count
<= count + 1; // Increment count
end

// Read operation
if (r_fifo && !empty) begin
data_out <= fifo_mem[rd_ptr]; // Read data from FIFO
rd_ptr <= (rd_ptr + 1) % FIFO_DEPTH; // Increment read
pointer count <= count - 1; // Decrement count
end
end
end

// Update empty and full flags

always_comb begin
empty = (count == 0);
full = (count == FIFO_DEPTH);
end

endmodule

// Testbench
module tb_fifo;

parameter DATA_WIDTH = 8;
parameter FIFO_DEPTH = 4;

logic clk;
logic rst_n;
logic [DATA_WIDTH-1:0] data_in;
logic w_fifo;
logic r_fifo;
logic empty;
logic full;
logic [DATA_WIDTH-1:0] data_out;

fifo #(
.DATA_WIDTH(DATA_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH)
) uut (

13
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
.clk(clk),
.rst_n(rst_n),
.data_in(data_in),
.w_fifo(w_fifo),
.r_fifo(r_fifo),
.empty(empty),
.full(full),
.data_out(data_out)
);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // 10 time units
clock period end

// Test sequence
initial begin
rst_n = 0; // Assert reset
#10;
rst_n = 1; // Deassert reset

// Write data to FIFO

w_fifo = 1; // Enable writing
for (int i = 0; i < 6; i++) begin
data_in = i; // Assign value
to write #10; // Wait for a
clock cycle
if (full) begin
$display("FIFO is full, cannot write
%d", i); end else begin
$display("Writing %d to
FIFO", i); end
end
w_fifo = 0; // Disable writing

// Wait for a moment before reading

#10;

// Read data from FIFO

r_fifo = 1; // Enable reading
for (int i = 0; i < 6; i++) begin
#10; // Wait for a clock cycle
if (empty) begin
$display("FIFO is empty, cannot
read"); end else begin
$display("Reading %d from FIFO",
data_out); end

14
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 end
r_fifo = 0; // Disable reading

// End of test sequence

#10;
$finish; // Ends the simulation
end
endmodule

OUTPUT:

Writing 0 to FIFO
Writing 1 to FIFO
Writing 2 to FIFO
FIFO is full, cannot write 3
FIFO is full, cannot write 4
FIFO is full, cannot write 5
Reading 0 from FIFO
Reading 1 from FIFO
Reading 2 from FIFO
FIFO is empty, cannot read
FIFO is empty, cannot read
FIFO is empty, cannot read

Aim & Execution (5) Viva Voce Output (5) Total Relevance to
Algorithm/ (5) (20) POs/PSOs
Apparatus
Required (5)

PO1,2,3,4,5,9,11,PSO1

RESULT:
Thus the system verilog code for logic gates using parameterized
simple FIFO using input was verified.

15
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
EXP. NO: 02 Design a content addressable memory using
associative array and show their output in System
DATE: Verilog

AIM:
To write the system Verilog code to design a content addressable memory
using associate array and show their output in system Verilog.

APPARATUS REQUIRED:

Sl. List of components Quantity

No.

1 Cadence software 1

2 Personal computer 1

PRECAUTIONS:

Make sure that there is no syntax and semantic error.

PROCEDURE:

1. Double click the terminal shortcut from desktop.

2. The window appears with [root@ local host ~] # after this type the
following commands:

3. cd cadence_db
4. csh
5. source csh rc1
6. NCO/rclabs/rtl
7. gedit filename.sv
8. Press enter. A window appears type the program and save it.

16
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 9. Open the terminal window and press ctrl+C.
10. Type the command as ncvlog –mess and press enter. The program is
compiled.

11. Type the command as gedit filename_tb.sv. A window

appears

type the test bench program and save it.

12. Compile it by typing the command nco filename_tb.sv
–mess and press enter.
13. To run the program type the command as
i. ncelab filename(without extension) –access +rwc –mess
14. Similarly run the test bench program.
15. To simulate the test bench program, type the
command ncsim testbench file name(without
extension) –gui. A window appears.
16. Select the nco_output and select all the inputs and outputs.
17. Right click and select send to waveform window.
18. Click run/continue netlist button and after some timeperiod stop it.
19. The digital domain output is displayed.
20. In nco_output right click and select trace-> analog sample and hold.
21. T he analog domain output is displayed.

17
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
PROGRAM:

module CAM;

bit [2:0] mem [byte];

byte last_index;

bit [2:0] search_val = 3'b100;

byte found_index;

bit found = 0;

initial begin

//1st assigning values to the index positions sir

mem[8'h00] = 3'b001;

mem[8'h01] = 3'b010;

mem[8'h02] = 3'b011;

mem[8'h03] = 3'b100;

$display("Printing the whole CAM:");//2) printing

whole mem foreach(mem[i])

$display("Index: %0h, Content: %b", i, mem[i]);

//3)content at specific index

$display("Content at index 8'h02 is %b",mem[8'h02]);

18
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 //4)Checking the index presence

if (mem.exists(8'h05))

$display("Content present at index");

else

$display("No content at index");

//5)Printing the element at last index and getting the last

index value foreach(mem[i])

last_index = i;

$display("Last Index: %0h, Last Content: %b", last_index,

mem[last_index]);

//6)Check specific value is present or not in the mem, if present print the
index of that value

foreach(mem[i]) begin

if (mem[i] == search_val) begin

found_index = i;

found = 1;

$display("Value %b found at index %0h", search_val,

found_index); break;

end

end

if (!found)

$display("Value %b not found in memory", search_val);

end

endmodule

19
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 OUTPUT:

Printing the whole CAM:

Index: 0, Content: 001
Index: 1, Content: 010
Index: 2, Content: 011
Index: 3, Content: 100
Content at index 8'h02 is 011
No content at index
Last Index: 3, Last Content: 100
Value 100 found at index 3

Aim & Execution (5) Viva Voce Output (5) Total Relevance to
Algorithm/ (5) (20) POs/PSOs
Apparatus
Required (5)

PO1,2,3,4,5,9,11,PSO1

RESULT:
Thus the system verilog code to design a content addressable memory
Using associate array and show their output was verified.

20
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
EXP NO: 03

Declare a register to perform write read operation

DATE: using Pre and post randomization methods.

AIM:
To write the system verilog code to declare a register to perform write
read operation using Pre and post randomization methods using test bench.

APPARATUS REQUIRED:

Sl. List of components Quantity

No.

1 Cadence software 1

2 Personal computer 1

PRECAUTIONS:

Make sure that there is no syntax and semantic error

PROCEDURE:

1. Double click the terminal shortcut from desktop.

2. The window appears with [root@ local host ~] # after this type the
following commands:

3. cd cadence_db
4. csh
5. source csh rc1
6. NCO/rclabs/rtl
7. gedit filename.sv
8. Press enter. A window appears type the program and save it.

21
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 9. Open the terminal window and press ctrl+C.
10. Type the command as ncvlog –mess and press enter. The program is compiled.

11. Type the command as gedit filename_tb.sv. A window appears

type the test bench program and save it.

12. Compile it by typing the command nco filename_tb.sv
–mess and press enter.
13. To run the program type the command as
i. ncelab filename(without extension) –access +rwc –mess
14. Similarly run the test bench program.
15. To simulate the test bench program, type the command ncsim
testbench file name(without extension) –gui. A window appears.
16. Select the nco_output and select all the inputs and outputs.
17. Right click and select send to waveform window.
18. Click run/continue netlist button and after some time period
stop it.

19. The digital domain output is displayed.

20. In nco_output right click and select trace-> analog sample and
hold.
21. The analog domain output is displayed.

22
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
PROGRAM:

class Register;
// Register properties
rand bit [7:0] data; // 8-bit register
bit [7:0] initial_value;

// Constructor to initialize the register with an

initial value function new(bit [7:0] init_value);
this.initial_value = init_value;
this.data = init_value;
endfunction

// Pre-randomization method
function void pre_randomize();
// Perform any necessary operations before randomization //
For example, logging or adjusting data based on initial_value
$display("Pre-randomization: Initial value is %0d",
this.initial_value); endfunction

// Post-randomization method
function void post_randomize();
// Perform any necessary operations after randomization //
For example, constraints checking or logging the randomized
value $display("Post-randomization: Randomized value is
%0d", this.data); endfunction

// Randomize method that calls pre and post

randomization function void
randomize_register();
// Call pre-randomization
this.pre_randomize();

// Randomize the data

if (!this.randomize()) begin
$error("Randomization failed!");
end

// Call post-randomization
this.post_randomize();
endfunction
endclass

23
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 // Testbench to demonstrate usage
module tb_register;
initial begin
Register reg1 = new(8'hAA); // Initialize with some value
reg1.randomize_register(); // Perform the randomization operation
end
endmodule

OUTPUT:

Pre-randomization: Initial value is 170

Pre-randomization: Initial value is 170
Post-randomization: Randomized value is 163
Post-randomization: Randomized value is 163

Aim & Execution (5) Viva Voce Output (5) Total Relevance to
Algorithm/ (5) (20) POs/PSOs
Apparatus
Required (5)

PO1,2,3,4,5,9,11,PSO1

RESULT:
Thus, the System Verilog code for code to declare a register to perform
write read operation using Pre and post randomization methods using Verilog
test bench was verified.

24
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
EXP NO: 04
Design an Inter Process Synchronization- Mailbox between
DATE: Generator and Driver component to receive the
transaction using System Verilog

AIM:

To write the system verilog code to design an Inter process

Synchronization - Mailbox between Generator and Driver component to receive the

transaction using System Verilog.

APPARATUS REQUIRED:

Sl. List of components Quantity

No.

1 Cadence software 1

2 Personal computer 1

PRECAUTIONS:

Make sure that there is no syntax and semantic error

PROCEDURE:

1. Double click the terminal shortcut from desktop.

2. The window appears with [root@ local host ~] # after this type the
following commands:

25
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 3. cd cadence_db
4. csh
5. source csh rc1
6. NCO/rclabs/rtl
7. gedit filename.sv
8. Press enter. A window appears type the program and save it.
9. Open the terminal window and press ctrl+C.
10. Type the command as ncvlog –mess and press enter. The program is
compiled.
11. Type the command as gedit filename_tb.sv. A window appears
type the test bench program and save it.
12. Compile it by typing the command nco filename_tb.sv
–mess and press enter. 13. To run the program type the
command as
i. ncelab filename(without extension) –access +rwc –mess
14. Similarly run the test bench program.
15. To simulate the test bench program, type the
command ncsim testbench file name(without
extension) –gui. A window appears.
16. Select the nco_output and select all the inputs and outputs.
17. Right click and select send to waveform window.
18. Click run/continue netlist button and after some
timeperiod stop it. 19. The digital domain output is
displayed.
20. In nco_output right click and select trace-> analog
sample and hold.
21. The analog doma in output is displayed.

26
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
PROGRAM:

// Transaction type

class transaction;

rand bit [7:0] data; //

Example data field //

Constructor

function new();

data = 8'b0;

endfunction

27
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 // Method to display the

transaction function

void display();

$display("Transaction Data:

%h", data); endfunction

endclass

module tb;

// Define the mailbox to

hold transactions mailbox

#(transaction) mail;

// Instantiate the generator and

driver processes initial begin

mail = new(); // Create a

new mailbox fork

generator(mail); // Start the

generator driver(mail); // Start

the driver join

end
endmodule

// Generator process

task generator(mailbox #(transaction) mail);

transaction trans;

28
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 // Generate transactions

for (int i = 0; i < 10; i++) begin

trans = new(); // Create a new transaction

trans.randomize(); // Randomize the data

mail.put(trans); // Send the transaction to the mailbox

$display("Generator: Sent Transaction %0d with Data: %h", i,

trans.data); #10ns; // Simulate some delay

end

endtask

// Driver process

task driver(mailbox #(transaction) mail);

transaction trans;

// Receive transactions

for (int i = 0; i < 10; i++) begin

mail.get(trans); // Receive the transaction from the mailbox

$display("Driver: Received Transaction %0d with Data: %h", i,

trans.data); trans.display(); // Display the transaction details

end

endtask

29
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
OUTPUT:

Generator: Sent Transaction 0

with Data: 28 Driver: Received
Transaction 0 with Data: 28
Transaction Data: 28
Generator: Sent Transaction 1
with Data: df Driver: Received
Transaction 1 with Data: df
Transaction Data: df
Generator: Sent Transaction 2
with Data: b8 Driver: Received
Transaction 2 with Data: b8
Transaction Data: b8
Generator: Sent Transaction 3
with Data: 11 Driver: Received
Transaction 3 with Data: 11
Transaction Data: 11
Generator: Sent Transaction 4
with Data: 5c Driver: Received
Transaction 4 with Data: 5c
Transaction Data: 5c
Generator: Sent Transaction 5
with Data: 22 Driver: Received
Transaction 5 with Data: 22
Transaction Data: 22
Generator: Sent Transaction 6
with Data: 47 Driver: Received
Transaction 6 with Data: 47
Transaction Data: 47
Generator: Sent Transaction 7
with Data: 19 Driver: Received
Transaction 7 with Data: 19
Transaction Data: 19
Generator: Sent Transaction 8
with Data: c2 Driver: Received
Transaction 8 with Data: c2
Transaction Data: c2
Generator: Sent Transaction 9
with Data: d1 Driver: Received
Transaction 9 with Data: d1
Transaction Data: d1

30
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 Aim & Execution (5) Viva Voce Output (5) Total Relevance to
Algorithm/ (5) (20) POs/PSOs
Apparatus
Required (5)

PO1,2,3,4,5,9,11,PSO1

RESULT:

Thus, the Inter process Synchronization - Mailbox between Generator

and Driver component to receive the transaction using System Verilog was
verified.

31
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 EXP NO: 05
Design an interface with Modport and Clocking
Block using System Verilog
DATE:

AIM:

To design an interface with modport and clocking block using system Verilog.

APPARATUS REQUIRED:

Sl. List of components Quantity

No.

1 Cadence software 1

2 Personal computer 1

PRECAUTIONS:

Make sure that there is no syntax and semantic error

PROCEDURE:

1. Double click the terminal shortcut from desktop.

2. The window appears with [root@ local host ~] # after this type the
following commands:

3. cd cadence_db
4. csh
5. source csh rc1
6. NCO/rclabs/rtl
7. gedit filename.sv
8. Press enter. A window appears type the program and save it.

32
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 9. Open the terminal window and press ctrl+C.
10. Type the command as ncvlog –mess and press enter.
The program is compiled.

11. Type the command as gedit filename_tb.sv. A window

appears type the test bench program and save it.
12. Compile it by typing the command nco filename_tb.sv
–mess and press enter. 13. To run the program type the
command as
i. ncelab filename(without extension) –access +rwc –mess
14. Similarly run the test bench program.
15. To simulate the test bench program, type the command
ncsim testbench file name(without extension) –gui. A
window appears.
16. Select the nco_output and select all the inputs and outputs.
17. Right click and select send to waveform window.
18. Click run/continue netlist button and after some
timeperiod stop it. 19. The digital domain output is
displayed.
20. In nco_output right click and select trace-> analog
sample and hold. 21. The analog doma in output is
displayed.

33
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
PROGRAM:

// Master.sv Design Code

interface my_interface(input bit clk);
// Signals within the interface
logic reset;
logic [7:0] data_in;
logic [7:0] data_out;
logic valid;
logic ready;

// Define a clocking block

clocking cb @(posedge clk);
input reset, ready;
output data_in, valid;
endclocking

// Define modports for different roles, including clk

modport master (input clk, reset, ready, output
data_in, valid); modport slave (input clk, reset,
data_in, valid, output data_out, ready); endinterface
module my_master_module(my_interface.master intf);
always @(posedge intf.clk) begin
if (intf.reset)
intf.data_in <= 8'h00;
else if (intf.ready)
intf.data_in <= intf.data_in + 1;
end
endmodule
module my_slave_module(my_interface.slave intf);
always @(posedge intf.clk) begin

34
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
if (intf.reset)
intf.data_out <= 8'h00;
else if (intf.valid)
intf.data_out <= intf.data_in;
end
endmodule
`timescale 1ns / 1ps
module top_tb;
bit clk;

// Instantiate the interface with the clock signal

my_interface intf(clk);

// Instantiate master and slave modules with

interface handles my_master_module
master_inst(intf);
my_slave_module slave_inst(intf);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // 100 MHz clock
end

// Test sequence
initial begin
// Initialize signals
intf.reset = 1;
intf.valid = 0;
intf.ready = 0;

// Display a message when the test starts

35
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
$display("Starting test...");
$display("Time=%0t : Reset applied.", $time);

// Deassert reset after some time

#10 intf.reset = 0;
intf.ready = 1;
$display("Time=%0t : Reset deasserted, ready signal is high.", $time);

// Start sending data and observe data transfer

#10 intf.valid = 1;
$display("Time=%0t : Valid signal set high, data transfer begins.", $time);

// Display data flow every clock cycle

forever begin
@(posedge clk);
$display("Time=%0t : Data_in = %0h, Data_out = %0h, Valid = %b,
Ready = %b", $time, intf.data_in, intf.data_out, intf.valid,
intf.ready);
// Stop displaying after 100ns
if ($time >= 100) begin
$display("Time=%0t : Ending test.", $time);
$finish;
end
end
end
endmodule

36
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 OUTPUT:

Starting test...
Time=0 : Reset applied.
Time=10000 : Reset deasserted, ready signal is high.
Time=20000 : Valid signal set high, data transfer begins.
Time=25000 : Data_in = 1, Data_out = 0, Valid = 1, Ready = 1
Time=35000 : Data_in = 2, Data_out = 1, Valid = 1, Ready = 1
Time=45000 : Data_in = 3, Data_out = 2, Valid = 1, Ready = 1
Time=55000 : Data_in = 4, Data_out = 3, Valid = 1, Ready = 1
Time=65000 : Data_in = 5, Data_out = 4, Valid = 1, Ready = 1
Time=75000 : Data_in = 6, Data_out = 5, Valid = 1, Ready = 1
Time=85000 : Data_in = 7, Data_out = 6, Valid = 1, Ready = 1
Time=95000 : Data_in = 8, Data_out = 7, Valid = 1, Ready = 1
Time=105000 : Data_in = 9, Data_out = 8, Valid = 1, Ready = 1
Time=105000 : Ending test.

Aim & Execution Viva Voce Output (5) Total Relevance to

Algorithm/ (5) (5) (20) POs/PSOs
Apparatus
Required (5)

PO1,2,3,4,5,9,11,PS
O1

RESULT:

Thus, the System Verilog code to design an interface with modport and
clocking block was written and executed and hence the output was
verified.

37
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 EXP NO: 06
Implement and test a stack data structure using
parameterized classes, allowing for various data
DATE:
types and depths

AIM:
To implement and test a stack data structure using parameterized classes,
allowing for various data types and depths using system Verilog.

APPARATUS REQUIRED:

Sl. List of components Quantity

No.

1 Cadence software 1

2 Personal computer 1

PRECAUTIONS:

Make sure that there is no syntax and semantic error

PROCEDURE:

1. Double click the terminal shortcut from desktop.

2. The window appears with [root@ local host ~] # after this type the
following commands:

3. cd cadence_db
4. csh
5. source csh rc1
6. NCO/rclabs/rtl
7. gedit filename.sv

38
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 8. Press enter. A window appears type the program and save it.
9. Open the terminal window and press ctrl+C.
10. Type the command as ncvlog –mess and press enter.
The program is compiled.

11. Type the command as gedit filename_tb.sv. A window

appears type the test bench program and save it.
12. Compile it by typing the command nco filename_tb.sv
–mess and press enter. 13. To run the program type the
command as
i. ncelab filename(without extension) –access +rwc –mess
14. Similarly run the test bench program.
15. To simulate the test bench program, type the command
ncsim testbench file name(without extension) –gui. A
window appears.
16. Select the nco_output and select all the inputs and outputs.
17. Right click and select send to waveform window.
18. Click run/continue netlist button and after some
timeperiod stop it. 19. The digital domain output is
displayed.
20. In nco_output right click and select trace-> analog
sample and hold. 21. The analog doma in output is
displayed.

39
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
PROGRAM:

class stack #(type T = int, int DEPTH = 10);

T queue_data[$];

function void push(T item);

if (queue_data.size() < DEPTH) begin
queue_data.push_back(item);
$display("Pushed: %0d", item);
end else begin
$display("Stack overflow: Cannot push more data.");
end
endfunction

function T pop();
T item;
if (queue_data.size() > 0) begin
item = queue_data.pop_front();
$display("Popped: %0d", item);
end else begin
$display("Stack underflow: No data to pop.");
end
return item;
endfunction
endclass

class stack_ext1 extends stack;

endclass

class stack_ext2 #(type S = string) extends stack#(integer);

function void show_string();
foreach (queue_data[i]) begin
$display("String element: %s", queue_data[i]);
end
endfunction
endclass

module top;
stack #(.T(byte), .DEPTH(20)) data = new();
byte data_array[20];
stack_ext1 data_ext1 = new();
stack_ext2#(.S(string)) data_ext2 = new();

initial begin

40
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 foreach (data_array[i]) begin
data_array[i] = $urandom_range(0, 255);
data.push(data_array[i]);
end

for (int i = 0; i < 20; i++) begin

byte popped_value = data.pop();
if (popped_value != data_array[i])
$display("Error: Mismatch at index %0d. Popped = %0d, Expected =
%0d", i, popped_value, data_array[i]);
else
$display("Matched: Popped = %0d, Expected = %0d",
popped_value, data_array[i]);
end

foreach (data_array[i]) begin

if (i < 10) begin
data_ext1.push(data_array[i]);
end
end

for (int i = 0; i < 10; i++) begin

byte popped_value_ext1 = data_ext1.pop();
end

data_ext2.push("Hello");
data_ext2.push("World");
data_ext2.show_string();
end
endmodule

OUTPUT:
Stack underflow: No data to pop.
Stack underflow: No data to pop.
Pushed: 54
Pushed: 60
Pushed: 125
Pushed: -30
Pushed: 11
Pushed: -33
Pushed: 64

41
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
Pushed: -9
Pushed: -90
Pushed: 27
Pushed: -75
Pushed: -6
Pushed: 78
Pushed: 21
Pushed: 125
Pushed: 114
Pushed: -106
Pushed: 49
Pushed: -60
Pushed: -86
Error: Mismatch at index 0. Popped = 0, Expected = 54
Error: Mismatch at index 1. Popped = 0, Expected = 60
Error: Mismatch at index 2. Popped = 0, Expected = 125
Error: Mismatch at index 3. Popped = 0, Expected = -30
Error: Mismatch at index 4. Popped = 0, Expected = 11
Error: Mismatch at index 5. Popped = 0, Expected = -33
Error: Mismatch at index 6. Popped = 0, Expected = 64
Error: Mismatch at index 7. Popped = 0, Expected = -9
Error: Mismatch at index 8. Popped = 0, Expected = -90
Error: Mismatch at index 9. Popped = 0, Expected = 27
Error: Mismatch at index 10. Popped = 0, Expected = -75
Error: Mismatch at index 11. Popped = 0, Expected = -6
Error: Mismatch at index 12. Popped = 0, Expected = 78
Error: Mismatch at index 13. Popped = 0, Expected = 21
Error: Mismatch at index 14. Popped = 0, Expected = 125
Error: Mismatch at index 15. Popped = 0, Expected = 114
Error: Mismatch at index 16. Popped = 0, Expected = -106
Error: Mismatch at index 17. Popped = 0, Expected = 49
Error: Mismatch at index 18. Popped = 0, Expected = -60
Error: Mismatch at index 19. Popped = 0, Expected = -86
Pushed: 54

42
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 Pushed: 60
Pushed: 125
Pushed: -30
Pushed: 11
Pushed: -33
Pushed: 64
Pushed: -9
Pushed: -90
Pushed: 27
Pushed: 1701604463
Pushed: 1869769828
String element: ello
String element: orld

Aim & Execution (5) Viva Voce Output (5) Total Relevance to
Algorithm/ (5) (20) POs/PSOs
Apparatus
Required (5)

PO1,2,3,4,5,9,11,PSO1

RESULT:

Thus, the System Verilog code to implement and test stack data
structure was written and executed and hence the output was verified.

43
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 EXP NO: 07
Demonstrate the creation, randomization,
DATE: and copying of objects between classes,

AIM:
To implement and to demonstrate the creation, randomization, and copying of
objects between classes, using system Verilog.

APPARATUS REQUIRED:

Sl. List of components Quantity

No.

1 Cadence software 1

2 Personal computer 1

PRECAUTIONS:

Make sure that there is no syntax and semantic error

PROCEDURE:

1. Double click the terminal shortcut from desktop.

2. The window appears with [root@ local host ~] # after this type the
following commands:

3. cd cadence_db
4. csh
5. source csh rc1
6. NCO/rclabs/rtl
7. gedit filename.sv
8. Press enter. A window appears type the program and save it.

44
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 9. Open the terminal window and press ctrl+C.
10. Type the command as ncvlog –mess and press
enter. The program is compiled.

11. Type the command as gedit filename_tb.sv. A

window appears type the test bench program and save it.
12. Compile it by typing the command nco filename_tb.sv
–mess and press enter. 13. To run the program type the
command as
i. ncelab filename(without extension) –access +rwc –mess
14. Similarly run the test bench program.
15. To simulate the test bench program, type the
command ncsim testbench file name(without
extension) –gui. A window appears.
16. Select the nco_output and select all the inputs and outputs.
17. Right click and select send to waveform window.
18. Click run/continue netlist button and after some
timeperiod stop it. 19. The digital domain output is
displayed.
20. In nco_output right click and select trace-> analog
sample and hold.
21. The analog domain output is displayed

45
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
PROGRAM:

class my_pkt;
int m_count;

function new();
m_count = 0;
endfunction
endclass

class eth_pkt;
rand bit [7:0] sof;
rand bit [15:0] len;
int count;
my_pkt m_pkt;

function new();
m_pkt = new();
endfunction

constraint len_c {
len < 40;
len > 20;
}

function void print();

$display("eth_pkt: sof = %0d, len = %0d, count = %0d, m_count = %0d",
sof, len, count, m_pkt.m_count);
endfunction

function void set();

sof = 10;
$display("eth_pkt set: sof = %0d", sof);
endfunction

function void copy(output eth_pkt pkt);

pkt = new();
pkt.sof = this.sof;
pkt.len = this.len;
pkt.count = this.count;
pkt.m_pkt = new();
pkt.m_pkt.m_count = this.m_pkt.m_count;
endfunction
endclass

46
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
module top;
eth_pkt pkt1;
eth_pkt pkt2;

initial begin
pkt1 = new();
pkt1.randomize();

pkt1.m_pkt.m_count = 'h5;

pkt1.print();

pkt2 = new();

pkt2.print();

pkt1.copy(pkt2);

pkt2.print();

pkt1.m_pkt.m_count = 'h4;
pkt1.sof = 'h1;
pkt1.len = 'h5;

pkt1.print();
pkt2.print();
end
endmodule

OUTPUT:

eth_pkt: sof = 185, len = 24, count = 0, m_count = 5

eth_pkt: sof = 0, len = 0, count = 0, m_count = 0

eth_pkt: sof = 185, len = 24, count = 0, m_count = 5

eth_pkt: sof = 1, len = 5, count = 0, m_count = 4

eth_pkt: sof = 185, len = 24, count = 0, m_count = 5

47
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 Aim & Execution (5) Viva Voce Output (5) Total Relevance to
Algorithm/ (5) (20) POs/PSOs
Apparatus
Required (5)

PO1,2,3,4,5,9,11,PSO1

RESULT:

Thus, the System Verilog code to demonstrate the creation, randomization, and
copying of objects between classes, was written and executed and hence the output
was verified.

48
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 EXP NO: 08
Explore inheritance, constraints, and method
DATE: overriding in object-oriented programming

AIM:
To implement and to explore inheritance, constraints, and method overriding in
object-oriented programming using system Verilog.

APPARATUS REQUIRED:

Sl. List of components Quantity

No.

1 Cadence software 1

2 Personal computer 1

PRECAUTIONS:

Make sure that there is no syntax and semantic error

PROCEDURE:

1. Double click the terminal shortcut from desktop.

2. The window appears with [root@ local host ~] # after this type the
following commands:

3. cd cadence_db
4. csh
5. source csh rc1
6. NCO/rclabs/rtl
7. gedit filename.sv

49
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 8. Press enter. A window appears type the program and save it.
9. Open the terminal window and press ctrl+C.
10. Type the command as ncvlog –mess and press
enter. The program is compiled.

11. Type the command as gedit filename_tb.sv. A

window appears type the test bench program and save it.
12. Compile it by typing the command nco filename_tb.sv
–mess and press enter. 13. To run the program type the
command as
i. ncelab filename(without extension) –access +rwc –mess
14. Similarly run the test bench program.
15. To simulate the test bench program, type the
command ncsim testbench file name(without
extension) –gui. A window appears.
16. Select the nco_output and select all the inputs and outputs.
17. Right click and select send to waveform window.
18. Click run/continue netlist button and after some
timeperiod stop it. 19. The digital domain output is
displayed.
20. In nco_output right click and select trace-> analog
sample and hold.
21. The analog domain output is displayed.

50
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
PROGRAM:

class eth_pkt;
rand bit [7:0] sof;
rand bit [15:0] len;
string count;

function new();
sof = 0;
len = 0;
count = "0";
endfunction

constraint len_c {
len < 40;
len > 20;
}

function void print();

$display("eth_pkt: sof = %0h, len = %0d, count = %s", sof, len, count);
endfunction

function void set();

sof = 10;
$display("Set method in eth_pkt: sof = %0h", sof);
endfunction
endclass

class good_pkt extends eth_pkt;

int good_count;

function new();
super.new();
good_count = 0;
endfunction

constraint len_c {
len > 60;
len < 80;
}

function void print();

super.print();

51
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 $display("good_pkt: good_count = %0d", good_count);
endfunction

function void set();

sof = 20;
$display("Set method in good_pkt: sof = %0h", sof);
endfunction
endclass

module top;
eth_pkt pkt;
good_pkt g_pkt;

initial begin
pkt = new();
if (!pkt.randomize()) begin
$display("Randomization of pkt failed.");
end
pkt.print();

g_pkt = new();
if (!g_pkt.randomize()) begin
$display("Randomization of g_pkt failed.");
end
g_pkt.print();

g_pkt.set();
g_pkt.set();
end
endmodule

OUTPUT:
eth_pkt: sof = b9, len = 24, count = 0
eth_pkt: sof = 7, len = 62, count = 0
good_pkt: good_count = 0
Set method in good_pkt: sof = 14
Set method in good_pkt: sof = 14

52
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 Aim & Execution (5) Viva Voce Output (5) Total Relevance to
Algorithm/ (5) (20) POs/PSOs
Apparatus
Required (5)

PO1,2,3,4,5,9,11,PSO1

RESULT:

Thus, the System Verilog code to explore inheritance, constraints, and

method overriding in object-oriented programming was written and executed
and hence the output was verified.

53
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 EXP NO: 09
Declare, initialize, and display elements of
multidimensional arrays.
DATE:

AIM:
To implement and declare the elements of multidimensional arrays using
system Verilog.

APPARATUS REQUIRED:

Sl. List of components Quantity

No.

1 Cadence software 1

2 Personal computer 1

PRECAUTIONS:

Make sure that there is no syntax and semantic error

PROCEDURE:

1. Double click the terminal shortcut from desktop.

2. The window appears with [root@ local host ~] # after this type the
following commands:

3. cd cadence_db
4. csh
5. source csh rc1
6. NCO/rclabs/rtl
7. gedit filename.sv

54
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 8. Press enter. A window appears type the program and save it.
9. Open the terminal window and press ctrl+C.
10. Type the command as ncvlog –mess and press
enter. The program is compiled.

11. Type the command as gedit filename_tb.sv. A

window appears type the test bench program and save it.
12. Compile it by typing the command nco filename_tb.sv
–mess and press enter. 13. To run the program type the
command as
i. ncelab filename(without extension) –access +rwc –mess
14. Similarly run the test bench program.
15. To simulate the test bench program, type the
command ncsim testbench file name(without
extension) –gui. A window appears.
16. Select the nco_output and select all the inputs and outputs.
17. Right click and select send to waveform window.
18. Click run/continue netlist button and after some
timeperiod stop it. 19. The digital domain output is
displayed.
20. In nco_output right click and select trace-> analog
sample and hold.
21. The analog domain output is displayed.

55
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
PROGRAM:

module tb;
bit [15:0] mem1 [63:0]; //Declaration sir
reg[7:0][9:0]mem2[8][6:0]; //Declared sir

initial begin
foreach(mem2[i, j, k])
mem2[i][j][k] = $urandom_range(1, 100);//Randomizing the elements sir

$display("Printing using single display: ",mem2); //single display

$display("/n <----------------Printing using for loop------------->");

for (int i = 0; i < 8; i++) begin
for (int j = 0; j < 7; j++) begin
for (int k = 0; k < 10; k++) begin
$display("mem2[%0d][%0d][%0d] = %0d", i, j, k, mem2[i][j][k]);
end
end
end

$display("mem2[6]= ",mem2[6]);//Printed the given element sir

$display("mem2[6][2]=%b",mem2[6][2]);//Printed the given element sir
$display("mem2[6][2][1]=%b",mem2[6][2][1]);//Printed the given element
sir
$display("mem2[6][2][1][4]=%b",mem2[6][2][1][4]);//Printed the given
element sir
end
endmodule

OUTPUT:

# KERNEL: Printing using single display: '{'{92186475360039213212709,

24892781205771646947408, 109878114448869212388354,
64961445517927147116557, 27165138803911893751876,
76843423018041811681361, 86247845414784632670251},
'{43713102182464235820105, 57872090736120248161306,
54413326164067414540384, 42605133390613482396689,
59104549158181829376040, 7190787233072315184132,
49595237953664459020336}, '{89782638619950084788246,
82723299086168863370256, 36670986701738445177950,

56
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
90996690773096766905362, 20117434365877584730167,
63841884475916007029807, 36677971788065512946752},
'{85045307813536876040202, 56730718689699145238624,
2376216328462517983319, 116920110548984950487118,
30717305724381768461408, 10636919141108775180340,
57885931419316703543332}, '{63840754104352258484268,
47294095599725620271180, 50811627552050088251433,
113406078994206819382316, 40210551492767043894277,
26060641139335554456622, 13000443172509766981713},
'{36644555103018549302310, 27199783844664036103242,
22457841355513734950961, 66156984589043015682061,
10648462957742284382249, 17718116881374905409551,
103974004530974998682678}, '{64949887077797543827465,
68526242855045024479290, 13063823375616569328668,
75643285820090292926469, 23641854616776454787085,
88628551801298987593813, 81520790652776241776668},
'{14174110437311488475234, 68583921532980204416088,
103997003356579315060745, 76816890103725633404945,
9466654340289366426685, 1193369474191999454307,
14259404152401294278744}}

# KERNEL: /n <----------------Printing using for loop------------->

# KERNEL: mem2[0][0][0] = 43

# KERNEL: mem2[0][0][1] = 50

# KERNEL: mem2[0][0][2] = 18

# KERNEL: mem2[0][0][3] = 79

# KERNEL: mem2[0][0][4] = 44

# KERNEL: mem2[0][0][5] = 83

# KERNEL: mem2[0][0][6] = 56

# KERNEL: mem2[0][0][7] = 73

57
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
# KERNEL: mem2[0][0][8] = x

# KERNEL: mem2[0][0][9] = x

# KERNEL: mem2[0][1][0] = 81

.# KERNEL: mem2[7][6][0] = 98

# KERNEL: mem2[7][6][1] = 16

# KERNEL: mem2[7][6][2] = 63

# KERNEL: mem2[7][6][3] = 81

# KERNEL: mem2[7][6][4] = 9

# KERNEL: mem2[7][6][5] = 83

# KERNEL: mem2[7][6][6] = 6

# KERNEL: mem2[7][6][7] = 12

# KERNEL: mem2[7][6][8] = x

# KERNEL: mem2[7][6][9] = x

# KERNEL: mem2[6]= '{64949887077797543827465,

68526242855045024479290, 13063823375616569328668,
75643285820090292926469, 23641854616776454787085,
88628551801298987593813, 81520790652776241776668}

# KERNEL:
mem2[6][2]=00000101000000011010000010100100010010100000101101000
101011100010101000000001101

58
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 # KERNEL: mem2[6][2][1]=0001010100

# KERNEL: mem2[6][2][1][4]=1

Aim & Execution Viva Voce Output (5) Total Relevance to

Algorithm/ (5) (5) (20) POs/PSOs
Apparatus
Required (5)

PO1,2,3,4,5,9,11,PS
O1

RESULT:

Thus the System Verilog code to declare the elements of multidimensional arrays
was written and executed and hence the output was verified.

59
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 EXP NO: 10
D Flip Flop complete implementation and
DATE: verification using system Verilog

AIM:
To implement and declare the elements of multidimensional arrays using
system Verilog.

APPARATUS REQUIRED:

Sl. List of components Quantity

No.

1 Cadence software 1

2 Personal computer 1

PRECAUTIONS:

Make sure that there is no syntax and semantic error

PROCEDURE:

1. Double click the terminal shortcut from desktop.

2. The window appears with [root@ local host ~] # after this type the
following commands:

3. cd cadence_db
4. csh
5. source csh rc1
6. NCO/rclabs/rtl
7. gedit filename.sv

60
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 8. Press enter. A window appears type the program and save it.
9. Open the terminal window and press ctrl+C.
10. Type the command as ncvlog –mess and press
enter. The program is compiled.

11. Type the command as gedit filename_tb.sv. A

window appears type the test bench program and save it.
12. Compile it by typing the command nco filename_tb.sv
–mess and press enter. 13. To run the program type the
command as
i. ncelab filename(without extension) –access +rwc –mess
14. Similarly run the test bench program.
15. To simulate the test bench program, type the
command ncsim testbench file name(without
extension) –gui. A window appears.
16. Select the nco_output and select all the inputs and outputs.
17. Right click and select send to waveform window.
18. Click run/continue netlist button and after some
timeperiod stop it. 19. The digital domain output is
displayed.
20. In nco_output right click and select trace-> analog
sample and hold.
21. The analog domain output is displayed.

61
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
PROGRAM:

`include "d_ff.v"
`include "dff_cfg.sv"
`include "dff_tx.sv"
`include "dff_ckr.sv"
`include "dff_cov.sv"
`include "dff_mon.sv"
`include "dff_bfm.sv"
`include "dff_gen.sv"
`include "dff_env.sv"
`include "dff_int.sv"
`include "dff_tb.sv"
module top;
logic clk,rst;
d_ff dut(.clk(inf.clk),.rst(inf.rst),.d(inf.d),.q(inf.q));
dff_int inf(clk,rst);
dff_tb tb();
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
rst=1;
repeat(2)@(posedge clk);
rst=0;
#100 $finish;
end
initial
begin
dff_cfg::vif=inf;
end
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule

//dff _int.sv

interface dff_int(input logic clk,rst);

62
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 logic d;
logic q;
clocking cb @(posedge clk);
//default input #0 output #9;
output d;
input q;
endclocking
endinterface

//dff_cfg.sv
class dff_cfg;
static virtual dff_int vif;
static mailbox gen2bfm=new();
static mailbox mon2ckr=new();
static mailbox mon2cov=new();
endclass

//dff_tb.sv
program dff_tb;
dff_env env=new();
initial
begin
env.run();
end
endprogram

//dff_env.sv
class dff_env;
dff_gen gen=new();
dff_bfm bfm=new();
dff_mon mon=new();
dff_ckr ckr=new();
dff_cov cov=new();
task run();
fork
gen.run();
bfm.run();
mon.run();
ckr.run();
cov.run();
join
endtask
endclass

63
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
//dff_tx.sv
class dff_tx;
rand bit d;
bit q;
endclass

//dff_gen.sv
class dff_gen;
dff_tx tx;
virtual dff_int vif;
task run();
begin
$display("GEN");
vif=dff_cfg::vif;
wait(vif.rst==0);
for(int i=0;i<10;i++)
begin
tx=new();
tx.randomize() with {d dist {1:=5,0:=5};};
dff_cfg::gen2bfm.put(tx);
end
end
endtask
endclass

//dff_bfm.sv
class dff_bfm;
virtual dff_int vif;
dff_tx tx;
task run();
begin
$display("BFM");
vif=dff_cfg::vif;
forever
begin
dff_cfg::gen2bfm.get(tx);
drive();
end
end
endtask
task drive();
begin
// @(posedge vif.clk)
@(vif.cb)

64
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 vif.d<=tx.d;
end
endtask
endclass

//dff_mon.sv
class dff_mon;
virtual dff_int vif;
dff_tx tx;//=new();
task run();
begin
$display("MON");
vif=dff_cfg::vif;
forever
begin
tx=new();
// @(posedge vif.clk)
@(vif.cb);
tx.d=vif.d;
tx.q=vif.q;
dff_cfg::mon2ckr.put(tx);
dff_cfg::mon2cov.put(tx);
end
end
endtask
endclass

//dff_ckr.sv
class dff_ckr;
dff_tx tx;
task run();
$display("CKR");
forever
begin
dff_cfg::mon2ckr.get(tx);
if(tx.d==tx.q)
$display("at %0tns data received correct d=%b, q=%b",$time,tx.d,tx.q);
else
$display("at %0tns ERROR:data received Wrongly d=%b,
q=%b",$time,tx.d,tx.q);
end
endtask
endclass

65
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
//dff_cov.sv
class dff_cov;
dff_tx tx;
covergroup dff_cg;
out: coverpoint tx.q{
bins one={1};
bins zero={0};
}
option.per_instance=1;
endgroup
function new();
dff_cg=new();
endfunction
task run();
$display("COV");
forever
begin
dff_cfg::mon2cov.get(tx);
dff_cg.sample();
end
endtask
endclass

//dff_run.do
vsim -c +access +r;
run -all;
acdb save;
acdb report -db fcover.acdb -txt -o cov.txt;
exec cat cov.txt;
exit
//use aldec riviera pro 2017.02 simulator

66
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
OUTPUT:

GEN

BFM

MON

CKR

COV

at 5ns data received correct d=0, q=0

at 15ns data received correct d=0, q=0

at 25ns data received correct d=0, q=0

at 35ns data received correct d=0, q=0

at 45ns data received correct d=1, q=1

at 55ns data received correct d=1, q=1

at 65ns data received correct d=0, q=0

at 75ns data received correct d=0, q=0

at 85ns data received correct d=1, q=1

at 95ns data received correct d=1, q=1

at 105ns data received correct d=0, q=1

67
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies
 Aim & Execution (5) Viva Voce Output (5) Total Relevance to
Algorithm/ (5) (20) POs/PSOs
Apparatus
Required (5)

PO1,2,3,4,5,9,11,PSO1

RESULT:
Thus, the implementation and verification of the D Flip Flop using
System Verilog was done successfully and hence verified.

68
PSVPEC/ECE/22EC592 RTL Design Verification Methodologies