ECE102: Semiconductor

Devices
Dr. Venkatnarayan Hariharan
Dept of Electrical Engg., Shiv Nadar Univ., Delhi NCR

ECE102 - VH - L19 0
 Agenda
• MOSCAP:
• Threshold voltage
• Nonidealities (ie. real effects) like unequal
workfunctions (𝜙𝑚 ≠ 𝜙𝑠 ) and oxide
charges
• CV characteristics
ECE102 - VH - L19 1
MOSCAP

Pic source: https://siliconvlsi.com/two-terminal-mos-structure/

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 Threshold Voltage 𝑉𝑡
• Deemed as the minimum (magnitude-wise) gate
voltage 𝑉𝑔 at which strong inversion sets in
• Is a characteristic of the MOS structure (viz. materials
used, oxide thickness and substrate doping and profile)
• MOSCAPs/MOSFETs with p-substrate (called n-channel
MOSCAP/MOSFET) usually have a 𝑉𝑡 > 0
• MOSCAPs/MOSFETs with n-substrate (called p-channel
MOSCAP/MOSFET) usually have a 𝑉𝑡 < 0
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 Steps to Derive 𝑉𝑡 Expression
1. Analogous to KVL, it can be seen that gate voltage 𝑉𝑔
splits up as voltage across oxide 𝑉𝑜𝑥 (text calls it 𝑉𝑖 )
and the total band bending in semicon. That is:
𝑉𝑔 = 𝑉𝑜𝑥 + 𝜙𝑠
2. In the oxide, we know that: 𝑉𝑜𝑥 = 𝐸𝑜𝑥 𝑡𝑜𝑥 where 𝐸𝑜𝑥
is the electric field in the oxide
3. We also know that: 𝜖𝑜𝑥 𝐸𝑜𝑥 = 𝜖𝑠 𝐸𝑠 (continuity of
normal component of electric displacement vector 𝑫)
4. Furthermore, Gauss Law says that 𝑄𝑠 = −𝜖𝑠 𝐸𝑠 where 𝑄𝑠 is the
areal charge density in the semicon Note: 𝜖 and 𝜖 are the permittivities of
𝑜𝑥 𝑠
the oxide and semiconductor respectively,
5. From #3 and #4, we have: 𝑄𝑠 = −𝜖𝑜𝑥 𝐸𝑜𝑥 whereas 𝑡 is the oxide thickness
𝑜𝑥
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 Steps to Derive 𝑉𝑡 Expression
6. Now, 𝑄𝑠 = 𝑄𝑑 + 𝑄𝑛 where 𝑄𝑑 is the depletion charge areal
charge density and 𝑄𝑛 is the inversion charge areal charge
density. But just at the onset of strong inversion, we can
approximate that 𝑄𝑑 ≫ 𝑄𝑛 (don’t confuse with “inversion layer is
as n-rich as substrate is p-rich in bulk”, which seems to contrast
with the suggested approximation. It doesn’t contrast, bcoz the
underlined requirement is in terms of volume density. When that
is integrated across the sheet thickness, we get areal density, and
therefore 𝑄𝑑 ≫ 𝑄𝑛 because the inversion layer sheet thickness is
much lesser). Hence 𝑄𝑠 ≅ 𝑄𝑑 just at the onset of strong inversion
7. From #5 and #6, it is clear that 𝑄𝑑 = −𝜖𝑜𝑥 𝐸𝑜𝑥 ⇒ 𝐸𝑜𝑥 = − 𝑄𝑑 Τ𝜖𝑜𝑥
𝑄𝑑 𝑡𝑜𝑥 𝑄𝑑
8. From #2 and #7, we have: 𝑉𝑜𝑥 = 𝐸𝑜𝑥 𝑡𝑜𝑥 = − ⇒ 𝑉𝑜𝑥 = −
𝜖𝑜𝑥 𝐶𝑜𝑥
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 Steps to Derive
𝝐
𝑉𝑡 Expression𝒐𝒙
9. Note that 𝑪𝒐𝒙 = is the oxide capacitance per unit area
𝒕𝒐𝒙
𝑄𝑑
10. From #1 and #8, we have: 𝑉𝑔 = − + 𝜙𝑠
𝐶𝑜𝑥
11. At inversion, 𝜙𝑠 = 2𝜙𝐹 and 𝑄𝑑 = 𝑄𝑑𝑚 , and hence, the 𝑉𝑔 at
that point (which is simply 𝑉𝑡 ) is:
𝑄𝑑𝑚
𝑉𝑔 𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 = 𝑉𝑡 = − + 2𝜙𝐹
𝐶𝑜𝑥
(where expressions for 𝑄𝑑𝑚 and 𝜙𝐹 were already discussed in the last class)
Note: The above expression for 𝑉𝑡 holds in the ideal case, viz.
when the metal and semicon workfunctions are equal. If that is
not the case, the expressions get modified, as we’ll soon see
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𝑉𝑡 and Non-idealities
• There are 2 common non-idealities (ie.
real-world effects):
1. So far we have assumed that 𝜙𝑚 = 𝜙𝑠 . This
is not true in general in the real case, where
we often have 𝜙𝑚 ≠ 𝜙𝑠 . Let us define 𝝓𝒎𝒔 =
𝝓𝒎 − 𝝓𝒔
2. Fixed/trapped charges within the oxide
• Both of these affect 𝑉𝑡
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 Unequal Workfunctions
• When 𝜙𝑚𝑠 ≠ 0, the equilibrium band diagrams look
different than what we discussed in L18.Slide3, viz. The
bands are not flat at 𝑉𝑔 = 0
• It turns out that an
additional gate voltage
of Δ𝑉𝑔1 = 𝜙𝑚𝑠 needs
to be applied, to make
the bands flat
• The pic alongside
shows the situation,
when 𝜙𝑚𝑠 < 0
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 Unequal Workfunctions
• In the band diagram (a) on the previous slide where
𝜙𝑚𝑠 ≠ 0, how do we figure out which way the bands bend
at equilibrium? Answer:
• Apply the principle: Electron affinity X remains unchanged within
a material. But work-function can change spatially within a
material
• If this principle is applied, and recognizing that vacuum level 𝐸0
(ie. near-surface vacuum energy level) can vary spatially (albeit
without discontinuity) so as to keep X unchanged, we can easily
infer how the bands will bend for the various cases (𝜙𝑚𝑠 < 0 as
well as 𝜙𝑚𝑠 > 0)
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 Oxide Charges
• The equilibrium MOS structure is affected by charges within the
oxide as well as at the oxide-semicon interface
• These charges are usually positive (for both substrate kinds),
created during oxide formation in device fabrication, and arise
from reasons like imperfections in the oxide, termination of the
semicon crystal lattice, etc
• For carefully treated Si-SiO2 interfaces, typical areal densities at
the interface are about 1010 +ve charges/cm2 when made on
{100} Si wafers, and about 10x higher when made on {111} Si
wafers. That is why MOS devices are generally made on {100} Si
wafer surfaces (recall Miller indices)
• If this total non-ideal oxide trapped charge is 𝑄𝑖 per unit area,
then an additional gate voltage of Δ𝑉𝑔2 = − 𝑄𝑖 Τ𝐶𝑜𝑥 needs to
be applied, to make the bands flat
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 Threshold Voltage 𝑉𝑡
• Thus, in the presence of both non-idealities an additional gate
voltage of Δ𝑉𝑔1 + Δ𝑉𝑔2 needs to be applied, to make the bands flat
at 𝑉𝑔 = 0. This additional amount is called flatband voltage 𝑽𝑭𝑩
𝑄𝑖
𝑉𝐹𝐵 = Δ𝑉𝑔1 + Δ𝑉𝑔2 = 𝜙𝑚𝑠 −
𝐶𝑜𝑥
• This is simply added to the ideal 𝑉𝑡 expression we developed earlier
• Thus, for realistic devices, the threshold voltage is:
𝑸𝒅𝒎 𝑸𝒊
𝑽𝒕 = 𝑽𝑭𝑩 − + 𝟐𝝓𝑭 where 𝑽𝑭𝑩 = 𝝓𝒎𝒔 −
𝑪𝒐𝒙 𝑪𝒐𝒙
where 𝑄𝑖 is the oxide trapped charge per unit area
• All charges are per unit area (areal charge density), and the oxide
capacitance 𝐶𝑜𝑥 too is per unit area (ie. 𝑪𝒐𝒙 = 𝝐𝒐𝒙 Τ𝒕𝒐𝒙 )
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 Capacitance-versus-Voltage (CV)
• The CV characteristics of this ideal MOS structure vary depending
on the bias regime (accumulation/depletion/inversion)
• The small-signal semiconductor capacitance 𝐶𝑠 is defined as: 𝐶𝑠 =
𝑑𝑄𝑠 Τ𝑑𝜙𝑠
• This can be evaluated, since the electrostatics analysis revealed to us the
dependency of 𝑄𝑠 on 𝜙𝑠 (see L18.Slide6 and L18.Slide7), from where it can
be seen that in depletion, 𝑪𝒅 = 𝝐𝒔 Τ𝑾, and therefore 𝑪𝒅 𝒎𝒊𝒏 = 𝝐𝒔 Τ𝑾𝒎
where 𝑊𝑚 is the maximum depletion width
𝝐𝒐𝒙
• The oxide capacitance is simply 𝑪𝒐𝒙 =
𝒕𝒐𝒙
• The total capacitance of the MOSCAP is a series combination of the
two, viz.:
𝐶 𝐶
𝐶 = 𝑜𝑥 𝑠 (plotted on the next slide)
𝐶𝑜𝑥 +𝐶𝑠
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 CV Characteristics
𝐶𝑜𝑥 =

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•
CV Characteristics
Accumulation: 𝐶 is very high because the slope of 𝑄 vs 𝜙𝑠 is very
𝑠 𝑠
steep in accumulation (ie. accumulation charge changes a lot with
small change in surface potential). Hence a large 𝐶𝑠 in series with a
fixed 𝐶𝑜𝑥 effectively results in net capacitance of 𝐶𝑜𝑥 , and the MOS
structure appears almost like a parallel-plate capacitor
• Depletion: As 𝑉𝑔 becomes less negative and starts to go to small
positive values, the semicon surface gets depleted. Thus 𝐶𝑠 here
consists of a depletion-layer capacitance 𝐶𝑑 = 𝜖𝑠 Τ𝑊, which is in
series with 𝐶𝑜𝑥 . As it goes further into depletion regime, 𝑊
increases, and so 𝐶𝑑 reduces, and so the series combination
reduces
• Inversion: Similar to accumulation, 𝐶𝑠 is very high in inversion
because the slope of 𝑄𝑠 vs 𝜙𝑠 is very steep. Hence a large 𝐶𝑠 in
series with a fixed 𝐶𝑜𝑥 effectively results in net capacitance of 𝐶𝑜𝑥
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 Solved Example
• The example shown here is
Example 6-1 from the text
• Towards the end, in the 𝑉𝑡
expression, there is a
typographical error. Instead
of ℎ𝐹 , read it as 𝜙𝐹

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END OF LECTURE

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