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Q1: Discuss Control Hazards in Pipelining?

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33 views2 pages

Q1: Discuss Control Hazards in Pipelining?

Uploaded by

aabilakim17
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© © All Rights Reserved
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Architecture and Organization of Computer System

Worksheet# 8
Abilakim Alisher

Q 1: Discuss Control Hazards in pipelining?

Q 2: What are the Solutions to Control Hazards?

Q 3: Describe in depth the branch prediction in control hazard?

Q4 Please provide an example of how to compare whether Destination matches the source.

Q 5: Explain Noop in RISC processor pipelining with an illustration?

Write the solutions to control hazards also branch prediction in detail.

Q1: Discuss Control Hazards in pipelining?


Control hazards, also known as branch hazards, occur in pipelining when the CPU needs to make
decisions about branching (e.g., jumps and loops) but does not know the outcome yet. This un-
certainty can stall the pipeline, waiting to decide which instructions to fetch next.

Q2: What are the Solutions to Control Hazards?

1. Stalling: Pause the pipeline until the branch decision is made.


2. Branch Prediction: Predict the outcome of a branch to continue pipeline execution.
3. Branch Delay Slots: Reorganize instructions to fill slots with useful instructions instead
of stalling.
4. Dynamic Branch Prediction: Use algorithms to predict branches based on historical be-
havior.

Q3: Describe in depth the branch prediction in control hazard?


Branch prediction is a technique used to guess the direction a branch will take to minimize stalls
in the pipeline. Predictors can be:

 Static Prediction: Simple methods, like always predicting "not taken."


 Dynamic Prediction: Uses hardware to track branch behavior over time with mecha-
nisms like the two-bit predictor, which adjusts based on whether previous predictions
were correct. This increases accuracy by adapting to patterns.

Q4: Provide an example of how to compare whether Destination matches the source.
In pipelining, a destination register of an earlier instruction might conflict with a source register
of a following one. Example:

 If Instruction 1 writes to register R1, and Instruction 2 reads from R1, we check if
Dest(Instruction 1) == Source(Instruction 2). If true, there’s a data hazard.

Q5: Explain Noop in RISC processor pipelining with an illustration?


A "Noop" (no operation) in RISC pipelining is an instruction that does nothing, often used to
avoid hazards. For example, if there’s a delay due to a control hazard, inserting Noop instruc-
tions stalls the pipeline without affecting the program logic, giving the pipeline time to resolve
the hazard.

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