1 .

trạng thái mealy

+ module mealy

module mealy(
input wire clkn, resetn, a, b,
output wire y0, y1,
output reg [1:0] tt_ht, tt_kt);
localparam [1:0] S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
always@(posedge clkn, negedge resetn)
if(resetn == 0) tt_ht <= S0;
else tt_ht <= tt_kt;
// next state logic
always@*
case(tt_ht)
S0: if(a) if(b) tt_kt = S1;
else tt_kt = S2;
else tt_kt = S0;
S1: if(a) tt_kt = S0;
else tt_kt = S2;
S2: if (b) tt_kt = S0;
else tt_kt = S2;
default: tt_kt = S0;
endcase
// Moore output logic
assign y1 = (tt_ht == S0);
// Mealy output logic
assign y0 = (tt_ht == S0)&a&b;
endmodule
+ chia xung 0,1 Hz:

module chiaxung_1hz(
clk_50m, clk_i
);
input clk_50m;
output reg clk_i;
reg [27:0] cnt;
initial
begin
cnt<=1;
clk_i <= 0;
end
always@(posedge clk_50m)
if (cnt==250000000)
begin
clk_i <= ~clk_i;
cnt<=1;
end
else
cnt<=cnt+1;
endmodule

+ board kết hợp

module board(
input clk_50m, reset, a, b,
output y0, y1, clk_1hz,
output [1:0] tt_ht);
wire clk_i;
chiaxung_1hz IC1(clk_50m, clk_i);
mealy IC2(clk_i, reset, a, b, y0, y1, tt_ht);
assign clk_1hz = clk_i;
endmodule

+ testbench

module test;

// Inputs
reg clkn;
reg resetn;
reg a;
reg b;

// Outputs
wire y0;
wire y1;
wire [1:0] tt_ht;
wire [1:0] tt_kt;

// Instantiate the Unit Under Test (UUT)

mealy uut (
.clkn(clkn),
.resetn(resetn),
.a(a),
.b(b),
.y0(y0),
.y1(y1),
.tt_ht(tt_ht),
 .tt_kt(tt_kt)
);

initial begin
clkn = 0;
#5;
clkn = 1;
#10;
clkn = 0;
#10;
clkn = 1;
forever#10 clkn =~ clkn;
end
initial begin
resetn = 0;
#20;
resetn = 1;
end
initial begin
a = 0;
#20;
a = 1;
#20;
a = 0;
#20;
a = 1;
#20;
a = 0;
#20;
end
 initial begin
b = 0;
#25;
b = 1;
#60;
b = 0;
end
endmodule

+ gán chân ucf

NET "clk_50m" LOC = C9;

NET "clk_50m" IOSTANDARD = LVCMOS33;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = L13;
NET "reset" IOSTANDARD = LVTTL;
NET "reset" PULLUP;
NET "a" LOC = L14;
NET "a" IOSTANDARD = LVTTL;
NET "a" PULLUP;
NET "b" LOC = H18;
NET "b" IOSTANDARD = LVTTL;
NET "b" PULLUP;
NET "clk_1hz" LOC = C11;
NET "clk_1hz" IOSTANDARD = LVTTL;
NET "clk_1hz" DRIVE = 8;
NET "y1" LOC = E12;
NET "y1" IOSTANDARD = LVTTL;
NET "y1" DRIVE = 8;
NET "y0" LOC = F12;
NET "y0" IOSTANDARD = LVTTL;
NET "y0" DRIVE = 8;
NET "tt_ht[1]" LOC = F9;
NET "tt_ht[1]" IOSTANDARD = LVTTL;
NET "tt_ht[1]" DRIVE = 8;
NET "tt_ht[0]" LOC = E9;
NET "tt_ht[0]" IOSTANDARD = LVTTL;
NET "tt_ht[0]" DRIVE = 8;

2 . trạng thái moore

+ module moore

module moore(
input clkn, resetn, w,
output z,
output reg [1:0] tt_ht, tt_kt);
parameter [1:0] A = 2'b00, B = 2'b01, C = 2'b10;
always@(w, tt_ht)
case(tt_ht)
A: if(w) tt_kt = B;
else tt_kt = A;
B: if(w) tt_kt = C;
else tt_kt = A;
C: if(w) tt_kt = A;
else tt_kt = C;
default: tt_kt = 2'bxx;
endcase
always@(negedge resetn, posedge clkn)
if(resetn == 0) tt_ht <= A;
else tt_ht <= tt_kt;
//define output
assign z = (tt_ht == B);
endmodule

+ chia xung 1hz

module chiaxung_1hz
#(parameter N = 26)
(input wire clk, output wire q);
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// bodt, register
always@(posedge clk)
r_reg <= r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q = r_reg[25];
endmodule

+ board kết hợp

module board(
input clk_50m, reset, w,
output z, clk_1hz,
output [1:0] tt_ht);
wire clk_i; chiaxung_1hz
IC1(clk_50m, clk_i); moore
IC2(clk_i, reset, w, z, tt_ht);
assign clk_1hz = clk_i;
endmodule

+ testbench

module test;

// Inputs
reg clkn;
reg resetn;
reg w;

// Outputs
wire z;
wire [1:0] tt_ht;
wire [1:0] tt_kt;

// Instantiate the Unit Under Test (UUT)

moore uut (
.clkn(clkn),
.resetn(resetn),
.w(w),
.z(z),
.tt_ht(tt_ht),
.tt_kt(tt_kt)
);

initial begin
// Initialize Inputs
 clkn = 0;
resetn = 0;
w = 0;
// Wait 10 ns for global reset to finish
#10;

resetn = 1;
w = 1;
// Wait 40 ns for global reset to finish
#40;

w = 0;
// Wait 20 ns for global reset to finish
#20;

w = 1;
// Wait 20 ns for global reset to finish
#20;

// Add stimulus here

end
always begin
#10; clkn =~ clkn;
end
endmodule

+ gán chân ucf

# PlanAhead Generated physical constraints

NET "clk_50m" LOC = C9;

NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = L13;
NET "w" LOC = L14;
NET "z" LOC = F12;

# PlanAhead Generated IO constraints

NET "clk_50m" IOSTANDARD = LVCMOS33;

NET "reset" IOSTANDARD = LVTTL;
NET "w" IOSTANDARD = LVTTL;
NET "reset" PULLUP;
NET "w" PULLUP;
NET "z" IOSTANDARD = LVTTL;
NET "z" DRIVE = 8;

# PlanAhead Generated physical constraints

NET "clk_1hz" LOC = F9;

# PlanAhead Generated IO constraints

NET "clk_1hz" IOSTANDARD = LVTTL;

NET "clk_1hz" DRIVE = 8;

# PlanAhead Generated physical constraints

NET "tt_ht[1]" LOC = F11;

NET "tt_ht[0]" LOC = E11;

# PlanAhead Generated IO constraints

NET "tt_ht[0]" IOSTANDARD = LVTTL;

NET "tt_ht[1]" IOSTANDARD = LVTTL;
NET "tt_ht[1]" DRIVE = 8;
NET "tt_ht[0]" DRIVE = 8;

3 . mode8
+ module mode8

module mod8(
input wire clk, reset, ud, st,
output wire [3:0] q,
output wire done);
reg [3:0] r_reg1=0;
reg r_reg2=0;
wire [3:0] r_next1;
wire r_next2;
always @(negedge clk, negedge reset, posedge st)
if (!reset)
begin
r_reg1 <= 0;
r_reg2 <= 0;
end
else
if ( st)
begin
 r_reg1 <= r_reg1;
r_reg2 <= r_reg2;
end
else
begin
r_reg1 <= r_next1;
r_reg2 <= r_next2;
end
// next state logic
assign r_next1 = (ud==0) ? (( r_reg1 ==7)? 0 : r_reg1+1 ): (( r_reg1 == 0)? 7 :
r_reg1-1);
assign r_next2 = (ud==0) ? (( r_reg1 ==6)? 1 : 0 ): (( r_reg1 == 1)? 1 :0);
// output logic
assign q=r_reg1;
assign done=r_reg2;
endmodule

+ chia xung 1hz

module chiaxung_1hz(
input clk_50m,
output reg clk_out);
reg [28:0] cnt;
initial
begin
cnt<=1;
clk_out <= 0;
end
always@(posedge clk_50m)
if (cnt==25000000)
 begin
clk_out<=~clk_out;
cnt <= 1;
end
else
cnt <= cnt+1;
endmodule

+board kết hợp

module board(
input clk_50m, reset, ud, st,
output clk_1hz,
output [3:0] q,
output done );
wire clk_i;
chiaxung_1hz IC1(clk_50m, clk_i);
mod8 IC2(clk_i, reset, ud, st , q, done);
assign clk_1hz= clk_i;
endmodule
+ testbench

module test;

// Inputs
reg clk;
reg reset;
reg ud;
reg st;

// Outputs
 wire [3:0] q;
wire done;

// Instantiate the Unit Under Test (UUT)

mod8 uut (
.clk(clk),
.reset(reset),
.ud(ud),
.st(st),
.q(q),
.done(done)
);

initial begin
st=0;
#40;
st=1;
#50;
st=0;
end
initial begin
clk = 0;
reset = 0;
ud = 0;
#10;
reset =1;
ud=0;
#200;
ud=1;
#250;
 ud=0;
#320;
ud=1;
#320;
end
always begin
#10;
clk=~clk;
end
endmodule

+ gán chân ucf

NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;

NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "ud" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "st" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "q<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "q<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "q<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "q<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "done" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;