COURSE HANDOUT

B. Tech – 5th Semester

Course Title : RTL Coding Techniques Date: 02-07-2023

Course Code : 21ECC11 Academic Year : 2023-24
Course Structure : 3-0-2-4
Course Coordinator : Dr. Govinda Rao Locharla
Instructor : Dr. Govinda Rao Locharla
Course description
This course deals with a quick review of the Verilog HDL coding, RTL design guidelines, RTL Coding practices for the
combinational & sequential digital circuits at fundamental circuits, and State machines. The course also focuses on the
design of basic architectures of Single-port and dual-port RAMs, the control path & data path of the digital circuits,
and its RTL coding.

Scope and Objective:

Students undergoing this course are expected to:
1. Comprehend the Verilog HDL modeling styles
2. Understand the guidelines of the RTL design
3. Be acquainted with the practices of RTL design coding
4. Develop the Verilog RTL for the implementation of state machines
5. Develop the RTL for basic architectures of Single port and dual port RAMs
6. Exemplify the control path and data path design for digital circuits

Text Books:
1. Vaibbhav Taraate, Advanced HDL Synthesis and SOC Prototyping (RTL Design Using Verilog),
Springer Nature Singapore Pte Ltd., 2019
2. Vaibbhav Taraate, Digital Logic Design Using Verilog Coding and RTL Synthesis, Springer Nature
Singapore Pte Ltd., 2016
3. J Bhasker, A Verilog HDL Primer, Star Galaxy Publishing, 3rd Edition, 2018

Reference Books:
1. Michael D. Ciletti, Advanced Digital Design with the Verilog, Prentice-Hall of India Private limited, 2nd
Edition, 2005

Syllabus
Unit I
RTL Coding Techniques-I
Introduction to Verilog & Modelling Styles, RTL Design Guidelines, Parallel Versus Priority Logic, Blocking
Assignments and Event Queue, Blocking Assignments and multiple “always” blocks, Blocking Assignments in the
same “always” block, ordering of non-blocking assignments, Continuous versus Procedural Assignments,
Combinational Loops in Design.

RTL code for Subtraction using 2’s complement, ALU

12 Hours
Unit II
RTL Coding Techniques-II

‘case’ with missing ‘default’, ‘if-else’ with missing ‘else’, Logical Equality versus Case Equality, Incomplete
Sensitivity List, Unintentional Latches in the Design, if-else versus case statements, Arithmetic Resource Sharing,
Asynchronous Reset D flip-flop, Synchronous Reset D flip-flops, Gated Clocks, Clock Enables

RTL code for 2 to 4 decoder using conditional statement, Synthesize the RTL for 4 to 1 Mux missing else

12 Hours

Unit III
RTL Coding Practice

State Machines and Optimization, Moore Machine, Mealy Machine, Sequence Detectors using FSM’s, Design
without Pipelining, Design with Pipelining, Synchronous Counters: Up-Down Counter, Ring Counter, Johnson
Counter, Asynchronous Counter: Ripple Counter; Structured design of nibble adder, Multiplexer, Decoder

RTL code for the encoder, decoder, shift registers

12 Hours

Unit IV
RTL Coding for Digital Architectures

Tri-State Bus, Bus Arbitration, Static Arbitration, Bidirectional Data Transfer, RTL design for, Single-Port RAM,
Dual-Port RAM, RTL design for Serial adder: Control path and Data path

SDRAM Memory Controller, DDR Memory Controller

12 Hours
Total: 48Hrs
Course Outcomes
After undergoing the course students will be able to:
1. Interpret the RTL design guidelines and synthesis of procedural blocks
2. Illustrate the Verilog RTL coding techniques
3. Use the RTL design techniques in HDL coding of digital circuits
4. Demonstrate the RTL design techniques for the implementation of sequential and combinational blocks
5. Perform the RTL coding at the block level for a digital system architecture
6. Interpret the control path and data path for complex digital circuits

Course plan
Chapter in the
Lecture no. Learning Objectives Topic to be covered Textbook/
Reference
Unit – I: Feedback Amplifier & Sinusoidal Oscillators
To understand the background and
Introduction to Verilog &
1 importance of the Verilog HDL and Ch2 of T1
Modeling Styles
its levels of abstraction
To understand the RTL design
2 RTL Design Guidelines, Ch3 of T1
guidelines
To understand the Parallel Versus
3 Parallel Versus Priority Logic Ch3 of T1
Priority Logic
 To exercise the HDL coding at the Exercise - the HDL coding at the
4 Behavior, Dataflow, and Gate level Behavior, Dataflow, and Gate
level
To understand the usage of
Blocking Assignments and Event
5 Blocking Assignments and Event Ch6 of T2
Queue
Queue
To understand the usage of
Blocking Assignments in the same
6 Blocking Assignments in the same Ch6 of T2
“always” block
“always” block
To understand the compilation of
Blocking Assignments and
Blocking Assignments & multiple
7 multiple “always” blocks, ordering Ch6 of T2
“always” blocks and ordering of
of Non-blocking assignments
non-blocking assignments
To exercise the usage of blocking Exercise - usage of blocking
8 T3, R1
assignments assignments
To understand the Continuous and Continuous versus Procedural
9 Ch4 of T2
Procedural Assignments Assignments
To exercise on the usage of
Exercise - usage of Continuous
10 Continuous and Procedural Ch4 of T2
and Procedural Assignments
Assignments
To understand the Combinational
11 Combinational Loops in Design Ch4 of T2
Loops in Design
To review the learning outcomes of Review
12 T1, T2, T3, R1
the Unit-I
Unit – II: RTL Coding Techniques-II
To understand the usage of the
13 ‘case’ statement and the ‘case’ with missing ‘default’ Ch4 of T2
importance of ‘default’
To understand the usage of the ‘if-
14 else’ statement and the importance ‘if-else’ with missing ‘else’ Ch4 of T2
of the ‘else’
To understand the difference
Logical Equality versus Case
15 between Logical Equality and Case Ch4 of T2
Equality
Equality
To understand the impact of an
16 Incomplete Sensitivity List Ch4 of T2
incomplete sensitivity list
To understand the reason and
Unintentional Latches in the
17 consequence of the Unintentional Ch4 of T2
Design
Latches infers in the Design
To understand the difference
18 between if-else versus case if-else versus case statements Ch6 of T2
statements
To understand the Arithmetic
19 Arithmetic Resource Sharing Ch4 of T2
Resource Sharing
To understand the Asynchronous
20 Asynchronous Reset D flip-flop Ch6 of T2
Reset D flip-flop
To understand the Synchronous
21 Synchronous Reset D flip-flops Ch6 of T2
Reset in D flip-flops
To understand the importance of Ch3 of T1
22 Gated Clocks, Clock Enables
Gated Clocks, Clock Enables Ch6 of T2
To review the learning outcomes of Review
23 T1, T2, T3, R1
the Unit-II
 Unit – III: RTL Coding Practice
To understand the State Machine
24 State Machine optimization Ch4 of T1
optimization
25 To understand the Mealy Machine Mealy Machine Ch4 of T1
26 To understand the Moore Machine Moore Machine Ch4 of T1
To practice the FSM design for FSM design for sequence
27 Ch8 of T1
sequence detectors detectors
To exercise the RTL design of
28 Sequence Detectors using FSM Ch4 of T1
Sequence Detectors using FSM’s
To differentiate between the
Synchronous and Asynchronous
29 Synchronous and Asynchronous Ch5 of T2
counters
counters
To perform the RTL coding for
pipelined and non-pipelined
30 pipelined and non-pipelined Ch6 of T2
designs
designs
To exercise on the Synchronous Up- Synchronous Counters - Up-
31 Ch5 of T2
Down Counters Down Counter
To exercise on the Ring Counter,
32 Ring Counter, Johnson Counter Ch5 of T2
Johnson Counter
33 To exercise the Ripple Counter Ripple Counter Ch5 of T2
To perform the structured design Structured design for a nibble
34 Ch5 of T2
for a nibble adder adder
To perform the structured design Structured design for Multiplexer,
35 Ch5 of T2
for Multiplexer, decoder Decoder
To review the learning outcomes of Review
36 T1, T2, T3, R1
the Unit-III
Unit – IV: RTL Coding for Digital Architectures
To introduce the basic digital
37 Introduction Ch6 of T1
architectures
To perform the RTL coding for Tri-
38 Tri-State Bus Ch6 of T1
State Bus
To perform the RTL coding for Bus
39 Bus Arbitration Ch6 of T1
Arbitration
To perform the RTL coding for Static
40 Static Arbitration Ch6 of T1
Arbitration
To perform the RTL coding for
41 Bidirectional Data Transfer Ch6 of T1
Bidirectional Data Transfer
To perform the RTL coding for
42 Single-Port RAM Ch7 of T1
Single-Port RAM
To perform the RTL coding for Dual-
43 Dual-Port RAM Ch7 of T1
Port RAM
To demonstrate the Serial adder Serial adder design: Control path
44 Ch7 of T1
design: Control path and Data path and Data path
To perform the FSM design for
FSM design & RTL Coding for the
45 Serial adder & RTL coding for its R2
Serial adder control path
control path
To perform the RTL coding for the Control path, data path of a Serial
46, 47 R2
Serial adder at top level adder
To review the learning outcomes of Review
48 T1, T2, T3, R1
the Unit-IV
Evaluation scheme:
Duration Date &
Component Marks % of weightage Venue
(minutes) Time
Sessional Test – 1 90 30 30 Block-6
(Average of 80% of first-
Sessional Test – 2 90 30 best marks and 20% of Block-6
second-best marks)
Will be Will be
Semester end exam 180 70 70
informed informed

Chamber consultation hour: 4 PM – 5 PM

Venue: Ground floor staff room (Block-6)
Notices: All notices regarding the course will be kept in the department notice board

Signatures of the Instructors Signature of the course-coordinator