Half Adder Structural

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Half Adder Structural

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pavanikaveesha9562

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INFOOP2R.WIX.

COM/OP2R

HALF SUBTRACTOR VHDL CODE USING STRUCTURAL MODELING

library IEEE; Library declaration

use IEEE.STD_LOGIC_1164.ALL; Std_logic_1164. package for std_logic (predefined data types).

--------------------------------------------

entity half_adder is Entity declaration….

Port ( a, b: in STD_LOGIC; a, b: - input port bits (bits to be

sum ,carry: out STD_LOGIC); added)
end half_adder; sum, carry: - output port bits
---------------------------------------------

architecture Behavioral of half_adder is

----------------------------------------------
component xor_1 is
Port ( o,p : in STD_LOGIC;
 Component (Ex-or, And, Not)
q : out STD_LOGIC);
declaration.
end component;  These components are describing the
component and_1 is structure view of half adder.
Port ( x,y : in STD_LOGIC;
z : out STD_LOGIC);
end component;
-----------------------------------------------
 Architecture statement’s part
begin (Architecture body).
X1: xor_1 port map (a, b, sum);  Components are port mapped to
x2: and_1 port map (a, b, carry); perform the circuit (adder) operation.
end Behavioral;
-----------------------------------------------

RTL VIEW:- OUT PUT WAVEFORMS:-

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Half Adder Structural

Uploaded by

Half Adder Structural

Uploaded by

INFOOP2R.WIX.

HALF SUBTRACTOR VHDL CODE USING STRUCTURAL MODELING

library IEEE; Library declaration

use IEEE.STD_LOGIC_1164.ALL; Std_logic_1164. package for std_logic (predefined data types).

entity half_adder is Entity declaration….

Port ( a, b: in STD_LOGIC; a, b: - input port bits (bits to be

architecture Behavioral of half_adder is

RTL VIEW:- OUT PUT WAVEFORMS:-

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