Memory

 Assuming that memory is byte organized.

 The total address space of 8086 is from 00000 to FFFFFH.

 The total address space of 1 MB is not obtained as a single chip of RAM –

also it is not entirely RAM.

 ROM is also part of memory and a number of RAM and ROM chips
together constitute the total memory i.e., the total address space.
Typical RAM with control pins
Why Active Low Control Signals?
 The stray capacitances of the control pins can get charged from noise
voltages, and this may cause the signals to cross the threshold of ‘high’
level as defined for TTL

 – thus if the control signals are active high, it may cause wrong triggering.

 On the other hand, an active low signal trigger will happen only when
the line is pulled low deliberately by the controller.
Example

 How many address and data lines are needed for the memory chips with
the following organization?
i) 256 × 4
ii) 512 × 8
iii) 1K × 16
iv) 32 K × 8
v) 128 K × 8
vi) 1M × 32
Memory Address Decoding
 i) Find out the range of addresses that the memory chip of 2K × 8 in Fig.1
 ii) Repeat the same when the logic of the NAND gate is changed as in
Fig.2

Fig.2

Fig.1
Solution.

The lower and upper range of the addresses in

the chip are seen as in the table. the address
range of the chip is FF800H to FFFFFH i.e., 2048
bytes i.e., 2 K bytes.
Example –contd’
Address Decoding Concepts
 The basic idea of address decoding is to decode the extra unused address
lines of the processor to specify the address range.

 When more chips are to be interfaced, decode the extra address lines to a
different range for each group.

 Any logic /logic gate can be used to perform address decoding.

Address decoding concepts
 In general, address decoders can be built using:

 – Random logic (simple gates)

 – Decoders (e.g. 2 × 4, 3 × 8 …)

 – Programmable logic (PLAs, CPLDs, FPGAs, …)

 Example

 Design an address decoder using OR logic for a 32 K × 8 RAM. Find the

address space of this memory chip.

solution

So, the total memory range from 00000H to 07FFFH is 32768 addresses (or 32 KB).
Solution – contd’
Example
 Find the address space of the following chips with the address decoding
circuitry as shown in the Fig a and b.

i) 8 K x 8 EPROM
ii) 8 K x 8 RAM
Example -solution
Address Decoding Using Block Decoders
 A very popular decoder is the 3 to 8 decoder (74LS138).

 The output lines are active low and depending on the selection inputs, one
output line alone will be active.
Functional block diagram of the 3 to 8 decoder 74LS138
Decoding table of 74LS138
Address decoding of a RAM using a block decoder
Example
 The figure shows a RAM and a ROM connected to an address decoder,
which is a 3 to 8 decoder. Find the address space of each of these chips.
Solution
 Only 4 lines of the address bus are to be used for address decoding, as the
remaining 16 lines are to be connected to each of the 64 K memory chips.
 For the ROM, A19 to A16 are to be 1001 (A19 = 1, CBA = 001).
 Thus, the address range of this chip is 90000H to 9FFFFH.
 Similarly, for the RAM, A19 to A16 are to be 1100 (A`9 = 1, CBA = 100). Th
us, the address range of this chip is C0000H to CFFFFH.
Partial Address Decoding
 We find that in all our discussions so far, the addresses generated are
unique and create no ambiguity. This is also called exhaustive decoding.

 However, sometimes to reduce the hardware used, only some of the upper
address lines are used for decoding and this is called partial address
decoding.

 The problem is that it creates foldback memory

Partial address decoding/Foldback memory
Example
 Draw a decoding circuit using partial decoding for a RAM and EPROM
each of size 8 K × 8. What is the size of its foldback memory?
Solution
 Memory Banks
 8086 has a 16-bit memory bus – which means that data transfer can occur
at a maximum rate of 16 bits (one word) per bus cycle.

 But byte transfer and word transfer must be possible.

 For a byte transfer, one byte locations must be accessed

 For a word transfer, two byte locations must be accessed

16-bit memory realized using two 8-bit memory chips
Upper and lower banks
• A 16-bit word is obtained as the concatenation of two bytes in two
‘memory banks’ i.e., memory is organized as two banks –

 One, the upper bank or high bank with the data corresponding to the
upper byte D8–D15, the other, the lower bank or low bank which has the
data lines D0–D7.

 The upper bank is also called the odd memory bank, because it has the
odd addresses mapped to it

 The lower bank is called the even bank.

Memory banks of 8086
Memory bank access
 For accessing a byte -

 If the address is odd ,the active low BHE signal will be activates

 If the address is even ,the A0 line of the address is low

For word access ,both the banks need to be activated

Memory banks with the respective bank enables signals, along with the decoder
I/O Address Decoding
 Only I/O mapped I/O or peripheral I/O or isolated I/O will be discussed.

 Even though our processor has 20 bits for address, I/O uses only 16 bits.

 Thus I/O port addresses can range from 0000 to FFFFH and the total I/O
space is only 64 K i.e., we can use 65,536 different I/O addresses.

 However, since the instructions for input (IN) and output (OUT) are
separate, we can have 64 K input ports and 64 K output ports.
Schemes of port addressing
Input Ports

 Input ports use the IN instruction to receive data into the processor in the
accumulator of the processor (AL or AX).

 An input port requires a tri-state buffer along with it to ensure that it is

isolated from the bus when it is not selected.
Requirements of an Input Port

 To identify/select the specific device, an address decoder should give a

select pulse.

 To read from the input device, the IORD signal must be active (low).

 When the above two conditions are true, the corresponding tri-state
buffer gets enabled and data is transferred to the processor.

 All the above activities occur during an I/O read cycle.

Basic input port
Functional pin diagram of the octal tri-state buffer 74LS244
Example
 Find the addresses of the two input devices shown in Figure and write a
program to read data from each of these ports and move it to some other
registers.
Example -solution
 i) Two sets of 8 switches S0 to S7 are connected to the data bus through
two tri-state buffers and this setup functions as two input ports.

 ii) The address of the ports are 8-bit, as only address lines A0 to A7 have
been considered for decoding. The address of the first port is 7EH and
that of the second is 3EH.

 iii) The address on the address bus decides which of the input ports get
selected. The tri-state buffer ensures that the port which is not selected, is
isolated from the bus.
Example –solution –contd’
 iv) The program for inputting data from each of these ports is
STRT: IN AL, 3EH
MOV BL, AL
IN AL, 7EH
MOV DL, AL
 Thus, after reading both ports, the switch settings are available in BL and
DL. This data can be used for processing and/or display.
 Output Ports

 Output ports use the instruction ‘OUT’ for writing into it.
 Data from the processor is sent to an output port during the I/O write
cycle.
 This data will be available on the data bus only until the end of a machine
cycle.
 For the output port to be able to use this data, it must be latched.
 Thus, a latch is mandatory for an output port set up.
Requirements of an Output Port

 To identify/select the specific device, an address decoder should give a

select pulse.
 To write into the output device, the IOWR signal must be active (low).
 When both the above two conditions are true, the data on the data bus is
latched.
 All the above activities occur during an I/O write cycle.
Basic output port setup
Example
 Design a system with 8 LEDs connected to the lower 8 bits of the data bus
of the 8086 data bus.
 The LEDs must switch ON and OFF with a delay of 1 second between each
switching action.

Fig shows the hardware setup.

 Example-solution
 The diagram with the address decoder, the select pulse and the IOWR
signal is shown. The address decoder gives a high select pulse.
 This is ANDed with the inverted IOWR pulse, and applied to the G pin
of the octal transparent latch 74LS373.
 The G pin needs a high level pulse to latch the data on its D inputs to its
Q outputs. OC must be strapped to ground to enable the output pins of
the latch.
 Current limiting resistors are connected to the cathodes of the LEDs
 The address decoder specifies an 8-bit address of F8H for the port.
Example-solution
 Th e program for switching the LEDs ON and OFF:
STRT: MOV AL, 0FFH ;data to light up all the LEDs
OUT 0F8H, AL ;transfer it to the output port
CALL DELAY_1SEC ;call the delay procedure
MOV AL, 00 ;data to switch off the LEDs
OUT 0F8H, AL ;transfer it to the output port
CALL DELAY_1SEC ;transfer it to the output port
JMP STRT
Decoding 16-Bit I/O Addresses

 Address lines A0 to A15 should be used by the address decoder to generate

the device select pulse.

 The other point to remember is to use ‘variable port addressing’ when

writing I/O instructions for ports with 16-bit addresses.
Ports with 16-Bit Data Bus
 However, 16-bit data bus is also possible for I/O ports.
 What becomes different then?
 The answer is that, the situation is similar to the case of memory banks.
 Recollect the concept of memory banks.
 If each of the 16-bit ports needed to be accessed as two 8-bit ports as well,
we have to have 8-bit I/O banks.
 So we can have I/O banks too, with 8 bits in the upper bank and 8 bits in
the lower bank.
I/O banks
Thank You