Microprocessor

System
Input output organization
Prepared by: Brent V Dita
Input - Output Interface
The Input / output organization of computer depends upon the size of comp
uter and the peripherals connected to it. The I/O Subsystem of the compute
r, provides an efficient mode of communication between the central system
and the outside environment

The most common input output devices are:

i) Monitor
ii) Keyboard
iii) Mouse
iv) Printer
v) Magnetic tapes
The devices that are under the direct control of the computer are said to
be connected online.
Input - Output Interface
Input Output Interface provides a method for transferring information betwe
en internal storage and external I/O devices.

Peripherals connected to a computer need special communication links for

interfacing them with the central processing unit.

The purpose of communication link is to resolve the differences that exist

between the central computer and each peripheral.
Input - Output Interface
The Major Differences are:-

1. Peripherals are electromechnical and electromagnetic devices and

CPU and memory are electronic devices. Therefore, a conversion of
signal values may be needed.

2. The data transfer rate of peripherals is usually slower than the transfer
rate of CPU and consequently, a synchronization mechanism may be
needed.

3. Data codes and formats in the peripherals differ from the word format in
the CPU and memory.
Input - Output Interface
4. The operating modes of peripherals are different from each other and
must be controlled so as not to disturb the operation of other peripherals
connected to the CPU.

To Resolve these differences, computer systems include special hardware

components between the CPU and Peripherals to supervises and
synchronizes all input and out transfers

These components are called Interface Units because they interface

between the processor bus and the peripheral devices.
I/O BUS and Interface Module
It defines the typical link between the processor and several peripherals.

The I/O Bus consists of data lines, address lines and control lines.

The I/O bus from the processor is attached to all peripherals interface.

To communicate with a particular device, the processor places a device ad

dress on address lines.

Each Interface decodes the address and control received from the I/O bus,
interprets them for peripherals and provides signals for the peripheral
controller.
I/O BUS and Interface Module
It is also synchronizes the data flow and supervises the transfer between pe
ripheral and processor.

Each peripheral has its own controller.

For example, the printer controller controls the paper motion, the print
timing
I/O BUS and Interface Module
The control lines are referred as I/O command. The commands are as follo
wing:
Control command- A control command is issued to activate the peripheral a
nd to inform it what to do.

Status command- A status command is used to test various status condition

s in the interface and the peripheral.

Data Output command- A data output command causes the interface to res
pond by transferring data from the bus into one of its registers.

Data Input command- The data input command is the opposite of the data
output.
I/O BUS and Interface Module
In this case the interface receives on item of data from the peripheral and p
laces it in its buffer register. I/O Versus Memory Bus
I/O BUS and Interface Module
In this case the interface
I/O BUS and Interface Module
To communicate with I/O, the processor must communicate with the memor
y unit. Like the I/O bus, the memory bus contains data, address and read/wr
ite control lines.
There are 3 ways that computer buses can be used to communicate with m
emory and I/O:
i. Use two Separate buses , one for memory and other for I/O.
ii. Use one common bus for both memory and I/O but separate control
lines for each.
iii. Use one common bus for memory and I/O with common control lines.
I/O BUS and Interface Module
I/O Processor
In the first method, the computer has independent sets of data, address a
nd control buses one for accessing memory and other for I/O. This is done i
n computers that provides a separate I/O processor (IOP). The purpose of I
OP is to provide an independent pathway for the transfer of information bet
ween external device and internal memory.
Asynchronous Data Transfer :
This Scheme is used when speed of I/O devices do not match with micropr
ocessor, and timing characteristics of I/O devices is not predictable. In this
method, process initiates the device and check its status. As a result, CPU
has to wait till I/O device is ready to transfer data. When device is ready CP
U issues instruction for I/O transfer. In this method two types of techniques
are used based on signals before data transfer.

i. Strobe Control
ii. Handshaking
Strobe Signal
The strobe control method of Asynchronous data transfer employs a single
control line to time each transfer. The strobe may be activated by either the
source or the destination unit.
Data Transfer Initiated by Source Unit:
Strobe Signal
In the block diagram fig. (a), the data bus carries the binary information from
source to destination unit. Typically, the bus has multiple lines to transfer an
entire byte or word. The strobe is a single line that informs the destination u
nit when a valid data word is available.
The timing diagram fig. (b) the source unit first places the data on the data
bus. The information on the data bus and strobe signal remain in the active
state to allow the destination unit to receive the data.
Strobe Signal
Data Transfer Initiated by Destination Unit:

In this method, the destination unit activates the strobe pulse, to informin
g the source to provide the data. The source will respond by placing the req
uested binary information on the data bus.

The data must be valid and remain in the bus long enough for the destina
tion unit to accept it. When accepted the destination unit then disables the s
trobe and the source unit removes the data from the bus.
Strobe Signal
Data Transfer
Strobe Signal
Disadvantage of Strobe Signal :

The disadvantage of the strobe method is that, the source unit initiates the
transfer has no way of knowing whether the destination unit has actually
received the data item that was places in the bus. Similarly, a destination
unit that initiates the transfer has no way of knowing whether the source unit
has actually placed the data on bus. The Handshaking method solves this
problem.
Handshaking:
The handshaking method solves the problem of strobe method by introduci
ng a second control signal that provides a reply to the unit that initiates the t
ransfer.
Principle of Handshaking:
The basic principle of the two-wire handshaking method of data transfer is a
s follow:
One control line is in the same direction as the data flows in the bus from
the source to destination. It is used by source unit to inform the destination
unit whether there a valid data in the bus. The other control line is in the oth
er direction from the destination to the source. It is used by the destination u
nit to inform the source whether it can accept the data. The sequence of co
ntrol during the transfer depends on the unit that initiates the transfer
Handshaking:
Source Initiated Transfer using Handshaking:

The sequence of events shows four possible states that the system can be
at any given time. The source unit initiates the transfer by placing the data
on the bus and enabling its data valid signal. The data accepted signal is
activated by the destination unit after it accepts the data from the bus. The
source unit then disables its data accepted signal and the system goes into
its initial state.
Handshaking:
Source Initiated Tr
Handshaking:
Destination Initiated Transfer Using Handshaking:

The name of the signal generated by the destination unit has been changed
to ready for data to reflects its new meaning. The source unit in this case do
es not place data on the bus until after it receives the ready for data signal fr
om the destination unit. From there on, the handshaking procedure follows t
he same pattern as in the source initiated case
Handshaking:
The only difference between the Source Initiated and the Destination Initiat
ed transfer is in their choice of Initial sate.
Handshaking:
Advantage of the Handshaking method:

The Handshaking scheme provides degree of flexibility and reliability

because the successful completion of data transfer relies on active
participation by both units.

If any of one unit is faulty, the data transfer will not be completed. Such
an error can be detected by means of a Timeout mechanism which provides
an alarm if the data is not completed within time.
Asynchronous Serial Transmission:
The transfer of data between two units is serial or parallel. In parallel data
transmission, n bit in the message must be transmitted through n separate
conductor path. In serial transmission, each bit in the message is sent in
sequence one at a time.

Parallel transmission is faster but it requires many wires. It is used for

short distances and where speed is important. Serial transmission is slower
but is less expensive.

In Asynchronous serial transfer, each bit of message is sent a sequence

at a time, and binary information is transferred only when it is available.
When there is no information to be transferred, line remains idle.
Asynchronous Serial Transmission:
In this technique each character consists of three points :
i. Start bit
ii. Character bit
iii. Stop bit
i. Start Bit- First bit, called start bit is always zero and used to indicate the b
eginning character.
ii. Stop Bit- Last bit, called stop bit is always one and used to indicate end
of characters. Stop bit is always in the 1- state and frame the end of the cha
racters to signify the idle or wait state.
iii. Character Bit- Bits in between the start bit and the stop bit are known as
character bits. The character bits always follow the start bit.
Asynchronous Serial Transmission:
In this
Asynchronous Serial Transmission:
Serial Transmission of Asynchronous is done by two ways:

a) Asynchronous Communication Interface

b) First In First out Buffer
Asynchronous Communication Inter
face:
It works as both a receiver and a transmitter. Its operation is initialized by
CPU by sending a byte to the control register.

The transmitter register accepts a data byte from CPU through the data
bus and transferred to a shift register for serial transmission.

The receive portion receives information into another shift register, and
when a complete data byte is received it is transferred to receiver register.

CPU can select the receiver register to read the byte through the data bus.
Data in the status register is used for input and output flags.
First In First Out Buffer (FIFO):
A First In First Out (FIFO) Buffer is a memory unit that stores information in
such a manner that the first item is in the item first out. A FIFO buffer comes
with separate input and output terminals. The important feature of this buffer
is that it can input data and output data at two different rates.

When placed between two units, the FIFO can accept data from the source
unit at one rate, rate of transfer and deliver the data to the destination unit a
t another rate.

If the source is faster than the destination, the FIFO is useful for source
data arrive in bursts that fills out the buffer. FIFO is useful in some applicatio
ns when data are transferred asynchronously.
Modes of Data Transfer :
Transfer of data is required between CPU and peripherals or memory or
sometimes between any two devices or units of your computer system. To
transfer a data from one unit to another one should be sure that both units
have proper connection and at the time of data transfer the receiving unit is
not busy. This data transfer with the computer is Internal Operation.

All the internal operations in a digital system are synchronized by means of

clock pulses supplied by a common clock pulse Generator. The data transfe
r can be
i. Synchronous or
ii. Asynchronous
Modes of Data Transfer :
When both the transmitting and receiving units use same clock pulse then s
uch a data transfer is called Synchronous process. On the other hand, if the
there is not concept of clock pulses and the sender operates at different mo
ment than the receiver then such a data transfer is called Asynchronous dat
a transfer.

The data transfer can be handled by various modes. some of the modes us
e CPU as an intermediate path, others transfer the data directly to and from
the memory unit and this can be handled by 3 following ways:
i. Programmed I/O
ii. Interrupt-Initiated I/O
iii. Direct Memory Access (DMA)
Programmed I/O Mode:
In this mode of data transfer the operations are the results in I/O
instructions which is a part of computer program. Each data transfer is
initiated by a instruction in the program. Normally the transfer is from a CPU
register to peripheral device or vice-versa.

Once the data is initiated the CPU starts monitoring the interface to see
when next transfer can made. The instructions of the program keep close
tabs on everything that takes place in the interface unit and the I/O devices.
Programmed I/O Mode:
In this mode
Programmed I/O Mode:
In this technique CPU is responsible for executing data from the memory fo
r output and storing data in memory for executing of Programmed I/O as sh
own in Flowchart-:
Programmed I/O Mode:
Drawback of the Programmed I/O :
The main drawback of the Program Initiated I/O was that the CPU has to
monitor the units all the times when the program is executing. Thus the
CPU stays in a program loop until the I/O unit indicates that it is ready for
data transfer. This is a time consuming process and the CPU time is wasted
a lot in keeping an eye to the executing of program.

To remove this problem an Interrupt facility and special commands are

used
Reference

A Notebook on Microprocessor System (With 8085 & 8086 Programming)

Prepared By Er. Shree Krishna Khadka teaching.official @gmail.com