Prepared by

Dr. Savitesh M. Sharma

Professor
Dept. of Electronics and Communication Engg.
DVR & DHS MIC College of Technology, Kanchikacherla
(A.P.)
04-10-2018 VLSI DESIGN ISSUES
Field Programmable Gate Array
FPGA are advanced version of CPLDs where PAL structure of the logic blocks is replaced by
Configurable logic blocks (CLBs). It can be reprogrammed only once or several times
depending on their technology used to manufacture.
Description:
A generic FPGA architecture consists of programmable logic elements (CLBs), programmable
interconnect and I/O programmable pads.
CLBs: Each CLBs consists of logic elements that can be used to realize the logic.
CLBs are two dimensional. FPGA can have more than 10000 CLBs
It contains two dimensional array of switching matrices to connect CLBs.
Programmable interconnect: They are used to establish connection between logic blocks.
I/O block : It contains resources such as:
Three state buffers
Registers
MUX
JTAG boundary scan circuitry
04-10-2018 VLSI DESIGN ISSUES
Field Programmable Gate Array Architecture

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FPGA Architecture description
In Xilinx routing, connections are made from logic block into the channel
through a connection block. As SRAM technology is used to implement Lookup
Tables, connection sites are large. A logic block is surrounded by connection
blocks on all four sides. They connect logic block pins to wire segments. Pass
transistors are used to implement connection for output pins, while use of
multiplexers for input pins saves the number of SRAM cells required per pin.
The logic block pins connecting to connection blocks can then be connected to
any number of wire segments through switching blocks. Four types of wire
segments are available:
1) general purpose segments, the ones that pass through switches in the
switch block.
2) Direct interconnect : ones which connect logic block pins to four
surrounding connecting blocks
3) long line : high fan out uniform delay connections
4) clock
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lines : clock signal providerVLSIwhich runs all over the chip.
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FPGA basic functional unit
LUT based logic blocks
The most common approach to implement the basic logic element is by using
2k-bit SRAM cell which represents a k-input one output Look up table (LUT).
The k-LUT is capable of implementing any Boolean function of k-variables.
The LUT based logic block consists of LUTs, flipflops, multiplexers and latches. FPGA can
contain more than one LUT e.g. CLBs in Xilinx Virtex-4 family contain 8 four-input LUTs.
Latch

1
1
MUX Output a
Input

4-input 0 1 out
LUT Flipflop
b
0

Clock 1

LUT based logic block Two input LUT realizing the function (a’+b)
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FPGA basic functional unit
MUX based logic blocks
The basic building block is Multiplexer to realize the Boolean function. A MUX
can be configured to implement different logic functions by connecting its
select and/or data lines to different signals.
e.g. implement function (wS1 + xS1’).(S3+S4)+(yS2+zS2’).(S3+S4)’
w
MUX1

1
x 0
MUX3

S1 1 Output
0
y
MUX2

1
0
z OR
S2
S3 S4
MUX based logic block
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Field Programmable Gate Array
FPGA are categorized into the following types:
Antifuse FPGA
Flash FPGA
Static Random Access Memory (SRAM) FPGA
Features:
✓None of the mask layers are customized
✓Basic logic cells and interconnect can be programmed at user sites
✓Core is a regular array of CLBs that can implement combinational as well as
sequential logic.
✓A matrix of prograammable interconnect surrounds the basic logic cells
✓Programmable I/O cells surround the core
✓Design turnaround time is a few hours
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Why do we need FPGA?
FPGAs were introduced as an alternative to custom ICs for implementing entire
system on one chip and to provide flexibility of reporogramability to the user.
Introduction of FPGAs resulted in improvement of density relative to discrete
SSI/MSI components (within around 10x of custom ICs). Another advantage of
FPGAs over CustomICs is that with the help of computer aided design (CAD)
tools circuits could be implemented in a short amount of time (no physical
layout process, no mask making, no IC manufacturing)

04-10-2018 FPGA comparative

VLSI DESIGN ISSUESanalysis
Field Programmable Gate Array
Advantages:
✓Design and Implementation are easier and faster
✓Size of the chip is small
✓Reliability is high
✓Due to reprogrammable feature, the component count is few
✓It provide remote hardware and field programming by end users
✓Risk and cost of development time is reduced
✓Non- recurring expenditure cost is low
✓Testing process is easier compared to PLDs
Disadvantages:
✓Power consumption is high and speed is slow
✓Production cost is higher than ASIC
✓There is overhead circuitry that is not available for programming

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Field Programmable Gate Array Applications
FPGA are extensively used for prototypes and production systems
➢In major research and development projects of
telecommunications, networking, process control to develop fast
prototypes
➢In pre-production systems where the product has to be
launched early to avoid competition
➢In production systems where the production volumes are not
high and the ASIC development cost is not justified

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FPGA Configuration
VHDL/ Verilog Design
Entry

Netlist (EDIF)

Implementation for a
specific device

Bit Stream (bit) file PROM file

Configure the FPGA

/Program the PROM

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FPGA Configuration Mode
➢JTAG: It is a mode which can be used to program FPGA, CPLD, PROM. It is
done using JTAG cable. It is serial programming mode in which data is loaded
one bit per test clock tick. It is also known as Boundary scan mode.
➢Master serial: It is a mode which is used to load configuration data from
serial PROM to an FPGA. It is a serial mode. FPGA provides the clock by using
its internal oscillator that drives the configuration clock.
➢Slave serial : It is a mode in which an external clock from a microprocessor or
another FPGA is used to load the configuration data onto an FPGA. It is serial
programming mode.
➢Slave Parallel: It is a mode in which external clock from another uP or FPGA is
required. The data transfer is done byte wise rather than bit wise and
therefore transfer is faster.
Generally JTAG and Master serial are used
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How to choose FPGA
FPGA are extensively used for prototypes and production systems
➢Identify the area of application
➢Check whether
➢Is the FPGA for general logic Implementation?
➢Is the FPGA for an embedded system implementation?
➢Is the FPGA for implementing signal processing functions?
➢ Identify the FPGA ‘s that meet customer needs in each of the families
➢Input voltage (5,3.3,2.5,1.8)
➢Number of gates
➢Macro Cells
➢Clock
➢Number of Pins
➢Package Type :
➢Plastic Leaded Chip Carrier (PLCC), Plastic Quad Flat Package (PQFP),
Very Thin Quad Flat Package (VTFQP), Thin Quad Flat Package (TQFP),
Ball grid array (BGA)
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FPGA basic cell (CLB) XC3000

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FPGA basic cell (CLB) XC3000
Xilinx CLB XC3000 has seven inputs for the combinational logic circuitry. The 5
logic inputs (A-E), the flipflop (QX and QY), a common clock input (K), an
asynchronous direct reset input (RD) and enable (EC). A 32-bit look up table
stored in 32-bits of SRAM, provides the ability to implement the combinational
logic.
There are two outputs from the LUT (F and G). Since 32-bit LUT requires only 5
variable to form a unique address, there are several ways to use the LUT:
1) 5 of the 7 inputs can be used . The CLB output F and G are then be identical.
2) 32-bit LUT can be split into half to implement tow functions of 4 variables each.
3) 32-bit LUT can be split into half , using one of the 7 variables as a select input to a 2:1
MUX that switches between F and G. SO 6 an 7 variables can be implemented.
The CLB propagation delay is fixed, equal to the LUT access time and
independent of the logic function implemented.
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Programmable Interconnection
How pass transistor are used to connect wire segment for the purpose of
FPGA Programming ? 1

M
1
20 6
M

20 6
16
Routing switches would exist for two purposes:
M
1) to connect the pins of the logic blocks to the wire segments
in the channels, and
2) 2) to connect one wire segment to another. Two examples
of how SRAM cells could be used to control the routing
switches in this type of FPGA are illustrated by Figure . M
SRAM
cell 16

Routing wire Routing wire

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Xilinx ISE Environment
Xilinx Integrated Software Environment (ISE) is an integrated simulation environment
tool for simulation and synthesis of design .
Step-by-step FPGA Design Implementation process on Xilinx
Environment
Step1: Creating a new Project using Xilinx Project Navigator
a) Open Xilinx Project Navigator by following steps:
Start -> Programs -> XilinxISE10.1i -> Project Navigator
b) Select File -> New Project
c) Type name of the Project
d) Select Project Location
e) Select an option from the Top Level source type list
(i) HDL
(ii) Schematics
(iii) EDIF : (Electronics Design Interchange format)
(iv) NGC/NGO
04-10-2018 Here we select HDL VLSI DESIGN ISSUES
Step-by-step FPGA Design Implementation
process on Xilinx Environment
Next set Device properties. Enter the values in the Device properties table as follows:
▪ Product Category : All
▪ Family : Virtex 4
▪ Device : XC4VFX12
▪ Package : SF363
▪ Speed : -10
▪ Top Level Source Type : HDL
▪ Synthesis tool : XST (VHDL/Verilog) (XST : Xilinx Synthesis Technology)
▪ Simulator : MODELSim-SE VHDL
g) Finish
Step2: Create VHDL/Verilog source code file. VHDL program structure is displayed in
the main GUI of Xilinix ISE. File generated will be “Filename.vhd”.
Step3: Write VHDL code in the file created in step2.
04-10-2018 VLSI DESIGN ISSUES
Step-by-step FPGA Design Implementation
process on Xilinx Environment
Step4: Do “Check Syntax” to check the syntax and semantics of code.
Step5: Do Synthesize XST -> Right click - > run
If synthesis completed successful go to next step
Step6: View synthesis report. It contains the detailed information about the Design hierarchy, HDL synthesis
report, low level synthesis , Device utilization summary and timing constraints.
Step7: DO Schematic XST → Generate Post Synthesis Simulation Mode -> Run
It will generate report called “filename.nif”
Step8 : Do Implement Design -> Translate → Run
On the Process table of Project Navigator
In this step the design is converter into technology dependent circuit. The Native Generic Database (NGD) file
generates the Native Circuit Description (NCD) file.
Step 9 : Select Implement Design -> Translate → FloorPlan Design -> Run
If user constraints file (.ucf) file is exist select it otherwise specify ports in Floorplanner window
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Step-by-step FPGA Design Implementation
process on Xilinx Environment
Step10: Implement Design → Map -> Run
See the map report, It will shows the mapping of design onto the configurable logic blocks (CLB) and I/O buffer
resources.
Step11: Select Implement Design -> Floorplan Post Map -> Run
This process will generate file “ filename.nlf” which contains the information version, device XC4vFX12,
package sf363 and speed -10 loading constraints from file “filename.pcf”.
Step12:. Do lmpement Design ->Placement and Routing → Run
After that do Post Placement and Routing static timing analysis
It will place the blocks and performs wiring and timing simulation and generate the PAR report. Th epad report
contains information about Pin Number, Pin Usage, Pin Name, IO standard, Drive (mA), Slew rate etc.
Step13: DO Implement Design → Place and Route ->Analyze Power (Xpower) ->Run
It will show information Voltage (V), Curret (mA), Power (mW), Data types etc.
Step14: In this step bit stream generation will be done. This step generates file “Filename.bit” for downloading
to a Target devices.
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Queue VHDL Implementation
Inputdata Library ieee;
Use ieee.std_logic_1164.all;
CLK
width Use ieee.std_logic_unsigned.all;
CS Use ieee.std_logic_arith.all;
width outdata Entity Queue is
RD Almostfull Generic (width : integer :=4; depth: integer:=4);
Queue
Port(clk,rst, wr,rd,cs : in std_logic;
WR Almostempty
Inputdata: inout std_logic_vector(width-1) downto 0);
empty Outtput : out std_logic_vector(width-1) downto 0);
RST
Almostempty, Almostfull, full, empty :out std_logic;);
full End Queue;

Architecture QueueArch of Queue is

Component Dpram
Generic (width : integer :=4; depth: integer:=4);

04-10-2018 VLSI DESIGN ISSUES

Queue VHDL Implementation
adda
ainoutdata Component Dpram
Generic (width : integer :=4; depth: integer:=4);
width
depth
addb Port (adda, addb: in std_logic_vector((depth-1) downto 0);
Ainout, binout: inout std_logic_vector((depth-1) downto 0);
depth
Dpram binoutdata
wra Wra, wrb, rst,clk, cs: in std_logic);
wrb
width
);
RST CS End component;
CLK

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Queue VHDL Implementation
Subtype ptrcount is integer range 0 to 2**depth -1;
Signal add1, add2 : std_logic_vector((depth-1) downto
add1 inputdata 0);
Signal outputdata : std_logic_vector((width-1) downto
adda ainoutdata 0);
depth width Signal ptr : ptrcount
add2 Signal wrrd : std_logic_vector(1 downto 0);
addb Rddpram : std_logic;
wr
depth wra
fulltemp AND
wrdpram Dpram outputdata Wrdpram : std_logic;
Begin
rd rddpram binoutdata Dulpram: Dpram generic map(width => width, depth =>
OR wrb width depth)
emptytemp
Port map(adda => add1, addb => add2,
RST CS Ainout => inputdata, binout => outputdata,
CLK Wra => wrdpram, wrb => rddpram, rst => rst, clk => clk,
cs => cs);
);
Wrrd <= wr & rd;
Wrdpram <= wr and not(fulltemp);
Rddpram <= rd or emptytemp;

04-10-2018 VLSI DESIGN ISSUES

Queue VHDL Implementation
% ------- controller--------------
% ------- Queue full----------------- Process(clk, rst) When “10” =>
Fulltemp <= ‘1’ when (ptr = 2**depth-1 Begin’ Add1 <= add1+’1’;
and wr=‘1’) Add2 <= add2+’1’;
If(rst = ‘1’) then
Else ‘0’; When “11” =>
Add1 <= (others=>’1’);
Almostfull<=‘1’ when (ptr = 2**depth-2 If (fulltemp = ‘0’) then
and wr=‘1’) Add2 <=(others => ‘1’);
Ptr <= 0; Add1 <=add1+’1’;
Else ‘0’;
Elsif (clk’event and clk=‘1’) Ptr <= ptr +1;
% ------- Queue empty-----------------
Case wrrd is Else add1 <= add1;
emptytemp <= ‘1’ when (ptr =0 and
rd=‘0’) When “00” => Ptr <= ptr;
Else ‘0’; If emptytemp = ‘0’ then When others=>
Almosempty <=‘1’ when (ptr = 1 and Add2 <= add2 + ’1’; End case;
rd=‘0’) End if;
Ptr <= ptr-1;
Else ‘0’; End process;
Else
Full <= Fulltemp; Output < = outputdata;
Add2 <= add2;
Empty < emptytemp; End QueueArch;
Ptr <=ptr;
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Shift Register VHDL Implementation
D Library ieee;
CLK
Use ieee.std_logic_1164.all;
width Use ieee.std_logic_unsigned.all;
width Use ieee.std_logic_arith.all;
load Entity ShiftReg is
ShiftReg Q Generic (width : integer :=5;);
Shiftlr
Port(clk,rst, load: in std_logic;
D: in std_logic_vector((width-1) downto 0);
RST
Shiftlr, dir : in std_logic;
Q : out std_logic_vector((width-1) downto 0));
Dir : is for the direction if dir =‘1’ i.e shift left End ShiftReg;
Shiftlr : is for shift
Architecture ShiftRegArch of ShiftReg is
D:D
Q: Dataout Variable Shifttemp : std_logic_vector((width-1)
downto 0)
04-10-2018 VLSI DESIGN ISSUES
Shift Register VHDL Implementation
Case dir is
% ------- controller--------------
When ‘0’ =>
Process(clk, rst)
Shifttemp := ‘0’ & Shifttemp(Shifttemp’LEFT downto 1);
Begin
When ‘1’ =>
If(rst = ‘1’) then
Shifttemp := Shifttemp(Shifttemp’LEFT - 1 downto 0)&’0’;
Shifttemp := (others =>‘0’);
End case;
Q <= Shifttemp;
Q := Shifttemp ;
Elsif (clk’event and clk=‘1’)
End if;
If load = ‘1’ then
End if;
Shifttemp := (others =>‘0’);
End process;
Shifttemp((width-1) downto 0) := D;
End ShiftRegArch;
Q <= Shifttemp;
Elsif shiftlr = ‘1’ then

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