Computer System Architecture

DR. Howida Youssry

Functions and Functional Blocks
▪ The functions considered are those found to be
very useful in design
▪ Corresponding to each of the functions is a
combinational circuit implementation called a
functional block.
 Binary Adder
 Half Adder x S
y HA
C
● Adds 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
───
x y C S C S
0 0 0 0
0 1 0 1 x S
1 0 0 1
1 1 1 0
y C
 Binary Adder
 Full Adder x S
y FA
z C
● Adds 1-bit plus 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
y + z
x y z C S ───
0 1 0 1
0 0 0 0 0 C S
0 0 1 0 1 x 1 0 1 0
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1
0 0 1 0
1 0 1 1 0
x 0 1 1 1
1 1 0 1 0
z
1 1 1 1 1 C = xy + xz + yz
 Binary Adder
 Full Adder S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C
z
z
y
z
 Binary Adder
 Full Adder
x S
y HA HA

z C

x
S

y
C

z
 Binary Adder
x3x2x1x0 y3y2y1y0
c3 c2 c 1 .
+ x3 x2 x1 x0
Carry + y3 y2 y1 y0
Cy Binary Adder C0 Propagate ────────
Addition Cy S3 S2 S1 S0
S3S2S1S0

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0
 Binary Adder
 Carry Propagate Adder

x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0

Cy CPA C0 Cy CPA C0 0

S3 S2 S1 S0 S3 S2 S1 S0

S7 S6 S5 S4 S 3 S2 S1 S0
Selecting
▪ Selecting of data or information is a critical
function in digital systems and computers
▪ Circuits that perform selecting have:
• A set of information inputs from which the selection
is made
• A single output
• A set of control lines for making the selection
▪ Logic circuits that perform selecting are called
multiplexers
▪ Selecting can also be done by three-state logic
or transmission gates
Multiplexers

S1 S0 Y I0
I1
0 0 I0 I2
MUX Y
0 1 I1 I3

1 0 I2 S1 S0
1 1 I3
Multiplexers
▪ 2-to-1 MUX
I0
I0 Y
I1 MUX Y
I1
S

▪ 4-to-1 MUX I0

I1
Y
I0 I2
I1
I2 I3
MUX Y
I3

S1 S0

S1 S0
Multiplexers
▪ A multiplexer selects information from an
input line and directs the information to
an output line
▪ A typical multiplexer has n control inputs
(Sn - 1, … S0) called selection inputs, 2n
information inputs (I2n - 1, … I0), and one
output Y
▪ A multiplexer can be designed to have m
information inputs with m < 2n as well as
n selection inputs
 DeMultiplexers
Y3
Y2
I DeMUX Y
1

S S Y0
1 0

Y3

Y2 S1 S0 Y3 Y2 Y1 Y0
I
Y1 0 0 0 0 0 I
Y0
0 1 0 0 I 0
1 0 0 I 0 0
S1 1 1 I 0 0 0
S0
Multiplexer / DeMultiplexer
Pairs
MUX DeMUX

I7 Y7
I6 Y6
I5 Y5
I4 Y4
Y I Y3
I3
I2 Y2
I1 Y1
I0 Y0

S2 S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y2 y1 y0
 Decoders
 Extract “Information” from the code Only one
lamp will
 Binary Decoder turn on
● Example: 2-bit Binary Number

0 1
x1 0
Binary
x0 0 Decoder 0
0
 Decoders
 2-to-4 Line Decoder
Y3

y3 Y2

Decoder
I1 Binary
y2
y1 Y1
I0 y0
Y0

I1 I0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3 = I1 I 0 Y2 = I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1 = I1 I 0 Y0 = I1 I 0
 Implementation Using Decoders
 Each output is a minterm
Binary
Decoder
 All minterms are produced
Y7
 Sum the required minterms Y6
Y5
Y4
x I2 Y3
y I1 Y2
Y1
Example: Full Adder z I0
Y0

S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)

S C
 Implementation Using Decoders
Binary Binary
Decoder Decoder

Y7 Y7
Y6 Y6
Y5 Y5
Y4 Y4
x I2 Y3 x I2 Y3
y I1 Y2 y I1 Y2
z I0 Y1 z I0 Y1
Y0 Y0

S C
S C
Decoding
▪ Decoding - the conversion of an n-bit input
code to an m-bit output code with
n  m  2n such that each valid code word
produces a unique output code
▪ Circuits that perform decoding are called
decoders
▪ Here, functional blocks for decoding are
• called n-to-m line decoders, where m  2n, and
• generate 2n (or fewer) minterms for the n input
variables
 Encoders
 Put “Information” into code Only one
switch
 Binary Encoder should be
● Example: 4-to-2 Binary Encoder activated
at a time

x1
x3 x2 x1 y1 y0
x2 y1 0 0 0 0 0
Binary
Encoder 0 0 1 0 1
y0 0 1 0 1 0
x3
1 0 0 1 1

Eastern Mediterranean University 20 / 65

 Encoders
 Octal-to-Binary Encoder (8-to-3)
I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
I5

Encoder
0 0 0 0 0 0 0 1 0 0 0 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0 I3 Y0
0 0 0 0 1 0 0 0 0 1 1 I2
0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
0 1 0 0 0 0 0 0 1 1 0 I7
1 0 0 0 0 0 0 0 1 1 1 I6 Y2
I5
Y2 = I 7 + I 6 + I 5 + I 4 I4
I3 Y1
Y1 = I 7 + I 6 + I 3 + I 2 I2
I1
Y0 = I 7 + I 5 + I 3 + I1 I0 Y0
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 Encoding
▪ Encoding - the opposite of decoding - the conversion
of an m-bit input code to a n-bit output code with n 
m  2n such that each valid code word produces a
unique output code
▪ Circuits that perform encoding are called encoders
▪ An encoder has 2n (or fewer) input lines and n output
lines which generate the binary code corresponding
to the input values
▪ Typically, an encoder converts a code containing
exactly one bit that is 1 to a binary code corres-
ponding to the position in which the 1 appears.
Encoder Example
▪ A decimal-to-BCD encoder
• Inputs: 10 bits corresponding to decimal
digits 0 through 9, (D0, …, D9)
• Outputs: 4 bits with BCD codes
• Function: If input bit Di is a 1, then the
output (A3, A2, A1, A0) is the BCD code for i,
▪ The truth table could be formed, but
alternatively, the equations for each of the
four outputs can be obtained directly.
Encoder / Decoder Pairs
Binary Binary
Encoder Decoder

I7 Y7
I6 Y6
I5 Y5
Y2 I2 Y4
I4 Y1 I1 Y3
I3 Y0 I0 Y2
I2
I1 Y1
I0 Y0

Eastern Mediterranean University 24 / 65

Seven-Segment Decoder
a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
? d g
0 0 1 0 1101101 y e
0 0 1 1 1111001 z f
g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111 1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...
Combinational Function Implementation
 Alternative implementation techniques:
● Decoders and OR gates
● Multiplexers (and inverter)
● ROMs
● PLAs
● PALs
● Lookup Tables
 Can be referred to as structured implementation
methods since a specific underlying structure is
assumed in each case