Lect 01
Lect 01
Computer Hardware(H/W)
CPU
Memory
Program Memory(ROM)
Memory
Data Memory(RAM)
I/O Device
Input Device: Keyboard, Mouse,
Scanner CPU
Output Device: Printer, Plotter, (control unit &
Display arithmetic unit)
Storage Device(I/O): FDD, HDD,
MOD
Input Interface Output
Device or IOP Device
Gate
The manipulation of binary information is done by logic circuit called
“gate”.
Blocks of H/W that produce signals of binary 1 or 0 when input logic
requirements are satisfied.
Digital Logic Gates : Fig. 1-2
AND, OR, INVERTER, BUFFER, NAND, NOR, XOR, XNOR
x xy x xy x
x
y y
Name
COMBINATIONAL
Symbol Function Truth Table
GATES
A B X
A X=A•B 0 0 0
AND X or 0 1 0
1 0 0
B X = AB 1 1 1
A A B X
OR X X=A+B 0 0 0
0 1 1
B 1 0 1
1 1 1
A X
I A X X=A 0 1
1 0
A X
Buffer A X X=A 0 0
1 1
A B X
A 0 0 1
NAND X X = (AB)’
0 1 1
1 0 1
B 1 1 0
A B X
A 0 0 1
NOR X X = (A + B)’ 0 1 0
1 0 0
B 1 1 0
A B X
XOR A X=AB 0 0 0
Exclusive OR X or 0 1 1
B X = A’B + AB’ 1 0 1
1 1 0
A B X
XNOR A X = (A B)’ 0 0 1
Exclusive NOR X or 0 1 0
or Equivalence B X = A’B’+ AB 1 0 0
1 1 1
Boolean Algebra
Boolean Algebra
Truth
* Algebra with Binary(Boolean) Variable and Logic Operations Table
* Boolean Algebra is useful in Analysis and Synthesis of
Digital Logic Circuits
Truth Table
x y z F
0 0 0 0 x
0 0 1 1
0 1 0 0 y F
2n Combination
0 1 1 0
Variable n = 3 1 0 0 1 z
1 0 1 1
1 1 0 1
1 1 1 1
Purpose of Boolean Algebra
To facilitate the analysis and design of digital circuit
Boolean function = Algebraic form = convenient tool
Truth table (relationship between binary variables : Fig 1-3a) Algebraic form
Logic diagram (input-output relationship : Fig. 1-3b) Algebraic form
Find simpler circuits for the same function : by using Boolean algebra rules
Boolean Algebra Rule : Tab. 1-1
[1] x + 0 = x [2] x • 0 = 0
[3] x + 1 = 1 [4] x • 1 = x
[5] x + x = x [6] x • x = x
[7] x + x’ = 1 [8] x • X’ = 0
[9] x + y = y + x [10] xy = yx
[11] x + (y + z) = (x + y) + z [12] x(yz) = (xy)z
[13] x(y + z) = xy +xz [14] x + yz = (x + y)(x + z)
[15] (x + y)’ = x’y’ [16] (xy)’ = x’ + y’
[17] (x’)’ = x
(2) A
B
F
C
(3) A
B
F
C
COMPLEMENT OF FUNCTIONS
A Boolean function of a digital logic circuit is represented by only using
logical variables and AND, OR, and Invert operators.
A,B,...,Z,a,b,...,z A’,B’,...,Z’,a’,b’,...,z’
(p + q) (p + q)’
AND OR
OR AND
Truth
Table
Simplified
Karnaugh Boolean
Map Function
Boolean
function
Map Simplification
Karnaugh Map(K-Map)
Map method for simplifying Boolean expressions
Minterm / Maxterm
Minterm : n variables product ( x=1, x’=0)
Maxterm : n variables sum (x=0, x’=1)
2 variables example
x y Minterm Maxterm
0 0 x'y' m0 x +y M0
0 1 x'y m1 x + y' M1
1 0 x y' m2 x'+ y M2
1 1 x y m3 x'+ y' M3
m0 + m1 + m2 + m3 M0 M1 M2 M3
F = x’y + xy
m1 m3
= ©(1,3) ( m1 + m3 )
= (0,2) (Complement = M0 M2 )
KARNAUGH MAP
Karnaugh Map for an n-input digital logic circuit (n-variable sum-of-products
form of Boolean Function, or Truth Table) is
- Rectangle divided into 2n cells
- Each cell is associated with a Minterm
- An output(function) value for each input value associated with a
mintern is written in the cell representing the minterm
--> 1-cell, 0-cell
1-cell
y 0 1
x y F x y 0 1
0 0 0 0 0 1 x
0 1 1 0 0 1
1 0 1 1 2 3
1 1 0
1 1 1
F(x,y) = (1,2)
KARNAUGH MAP
x y z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
u v w x F
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
F(u,v,w,x) = (1,3,6,8,9,11,14)
Ex) F= x + y’z
(1) Truth Table (2) F(x, y,z) = ©(1,4,5,6,7)
x y z F Minterm (3)
y
0 0 0 0 m0
0 0 1 1 m1 0 1 3 2
0 1 0 0 m2
4 5 7 6
0 1 1 0 m3 x
1 0 0 1 m4
1 0 1 1 z
m5
1 1 0 1 m6
1 1 1 1 m7 F= x + y’z
[ex.] F(A,B,C) = ©(3,4,6,7)
F=AC’ + BC
Product-of-Sums Simplification
F(A,B,C,D) = ©(0,1,2,5,8,9,10)
F=B’D’ + B’C’ + A’C’D Sum of product
i0 f0
i1 Combinational f1
Circuits
...
...
(Logic Gates)
in fm
A sequential circuit
is an interconnection of F/F and Gate
Clocked synchronous sequential circuit
Flip-Flops
Combinational Circuit = Gate
Flip-Flop Sequential Circuit = Gate + F/F
Clock
DA D
SET
x Q A