TDA1386T

INTEGRATED CIRCUITS
DATA SHEET
TDA1386T
Noise shaping filter DAC
Product specification 1998 Jan 06
Supersedes data of 1995 Dec 11
File under Integrated Circuits, IC01
Philips Semiconductors Product specification
Noise shaping filter DAC TDA1386T
FEATURES GENERAL DESCRIPTION

General The TDA1386T is a dual CMOS digital-to-analog converter
with up-sampling filter and noise shaper. The combination
• Double-speed mode
of oversampling up to 4fs, noise shaping and continuous
• Digital volume control calibration conversion ensures that only simple 1st order
• Soft mute function analog post filtering is required.
• 12 dB attenuation The TDA1386T supports the I2S-bus data input mode with
• Low power dissipation word lengths of up to 20 bits and the LSB fixed serial data
input format with word lengths of 16, 18 or 20 bits.
• Digital de-emphasis.
Two cascaded IIR filters increase the sampling rate
4 times.
Easy application
The DACs are of the continuous calibration type and
• Voltage output
incorporate a special data coding. This ensures a high
• Only 1st-order analog post-filtering required signal-to-noise ratio, wide dynamic range and immunity to
• Operational amplifiers and digital filter integrated process variation and component ageing.
• 256fs system clock (fsys) Two on-board operational amplifiers convert the
• I2S-bus or 16, 18 or 20 bits LSB fixed serial input format digital-to-analog current to an output voltage.
• Single rail supply.
High performance
• Superior signal-to-noise ratio
• Wide dynamic range
• No zero crossing distortion
• Inherently monotonic
• Continuous calibration digital-to-analog conversion
combined with noise shaping technique.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
TDA1386T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
1998 Jan 06 2
QUICK REFERENCE DATA

All power supply pins VDD and GND must be connected to the same external supply unit.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply
VDDD digital supply voltage 4.5 5.0 5.5 V
VDDA analog supply voltage 4.5 5.0 5.5 V
VDDO operational amplifier supply 4.5 5.0 5.5 V
voltage
IDDD digital supply current VDDD = 5 V; − 5 8 mA
at code 00000H
IDDA analog supply current VDDA = 5 V; − 3 5 mA
at code 00000H
IDDO operational amplifier supply VDDO = 5 V; − 2 4 mA
current at code 00000H
Analog signals
VFS(rms) full-scale output voltage VDDD = VDDA = VDDO = 5 V; 0.935 1.1 1.265 V
(RMS value) ROL > 5 kΩ
RL output load resistance 5 − − kΩ
DAC performance
(THD + N)/S total harmonic distortion at 0 dB signal level; − −70 − dB
plus noise-to-signal ratio fi = 1 kHz − 0.032 − %
at −60 dB signal level; − −42 −32 dB
fi = 1 kHz − 0.8 2.5 %
S/N signal-to-noise ratio no signal; A-weighted − −108 −96 dB
BR input bit rate at data input fs = 44.1 kHz; normal speed − − 2.822 bits
fs = 44.1 kHz; double speed − − 5.645 bits
fsys clock frequency 6.4 − 18.432 MHz
Tamb operating ambient −40 − +85 °C
temperature
1998 Jan 06 3
BLOCK DIAGRAM
Fig.1 Block diagram.
1998 Jan 06 4
PINNING
SYMBOL PIN DESCRIPTION

VDDA 1 analog supply voltage
AGND 2 analog ground
TEST1 3 test input 1; pin should be
connected to DGND
BCK 4 bit clock input
WS 5 word select input
DATA 6 data input
CKSL1 7 format selection 1
CKSL2 8 format selection 2
DGND 9 digital ground
VDDD 10 digital supply voltage
TEST2 11 test input 2; pin should be
connected to DGND
SYSCLK 12 system clock 256fs
APP3 13 application mode 3 input
APPL 14 application mode selection input
VOL 18 left channel output
FILTCL 19 capacitor for left channel 1st-order
filter function, should be connected
between pins 19 and 18
FILTCR 20 capacitor for right channel 1st-order
filter function, should be connected
between pins 20 and 21
VOR 21 right channel output
Vref 22 internal reference voltage for output
channels (0.5VDDO typ.)
OGND 23 operational amplifier ground
Fig.2 Pin configuration.
VDDO 24 operational amplifier supply voltage
1998 Jan 06 5
FUNCTIONAL DESCRIPTION The TDA1386T supports the following data input modes:
The TDA1386T CMOS DAC incorporates an up-sampling • I2S-bus with data word length of up to 20 bits.
filter, a noise shaper, continuous calibrated current • LSB fixed serial format with data word length of 16, 18
sources and operational amplifiers. or 20 bits. As this format idles on the MSB it is necessary
to know how many bits are being transmitted.
System clock and data input format
The data input formats are illustrated in Fig.7. Left and
The TDA1386T accommodates slave mode only right data-channel words are time multiplexed.
consequently, in all applications, the system devices must
provide the 256fs system clock.
Table 1 Data input format and system clock

SYSTEM CLOCK
CKSL1 CKSL2 DATA INPUT FORMAT
NORMAL SPEED DOUBLE SPEED
0 0 I2S-bus 256fs 128fs
0 1 LSB fixed 16 bits 256fs 128fs
Device operation In the pseudo-static application mode the TDA1386T is pin

compatible with the TDA1305T slave mode. The
When the APPL pin is held HIGH and APP3 is held LOW,
correspondence between TDA1386T pin number,
pins APP0, APP1 and APP2 form a microcontroller
TDA1386T pin name, TDA1305T pin name and a
interface. When the APPL pin is held LOW, pins APP0,
description of the effects is given in Table 2.
APP1, APP2 and APP3 form pseudo-static application
pins (TDA1305T pin compatible).
PSEUDO-STATIC APPLICATION MODE (APPL = LOGIC 0)

In this mode, the device operation is controlled by
pseudo-static application pins (APP0: attenuation mode
control; APP1: double-speed mode control; APP2: mute
mode control and APP3: de-emphasis mode control).
Table 2 Pseudo-static application mode

TDA1305T LOGIC
PIN NAME PIN NUMBER DESCRIPTION
FUNCTION VALUE
APP0 17 ATSB 0 12 dB attenuation (from full scale) activated
(only if MUSB = 1)
1 full scale (only if MUSB = 1)
APP1 16 DSMB 0 double-speed mode
1 normal-speed mode
APP2 15 MUSB 0 samples decrease to mute level
1 level in accordance with ATSB
APP3 13 DEEM1 0 de-emphasis OFF (44.1 kHz)
1 de-emphasis ON (44.1 kHz)
1998 Jan 06 6
MICROCONTROLLER APPLICATION MODE MICROCONTROLLER WRITE OPERATION SEQUENCE

(APPL = LOGIC 1, APP3 = LOGIC 0)
• APP2 is held LOW by the microcontroller.
In this mode, the device operation is controlled by a set of • Microprocessor data is clocked into the internal shift
flags in an 8-bit mode control register. The 8-bit mode register on the LOW-to-HIGH transition at pin APP1.
control register is written by a microprocessor interface
(pin APPL = 1, APP0 = Data, APP1 = Clock, APP2 = RAB • Data D(7 to 0) is latched into the appropriate control
and APP3 = 0). register on the LOW-to-HIGH transition of pin APP2
(with APP1 HIGH).
The correspondence between serial to parallel conversion,
• If more data is clocked into the TDA1386T before the
mode control flags and a summary of the effect of the
LOW-to-HIGH transition on pin APP2 then only the last
control flags is given in Table 3. Figures 3 and 4 illustrate
8 bits are used.
the mode set timing.
• If less data is clocked into the TDA1386T unpredictable
operation will result.
• If the LOW-to-HIGH transition of pin APP2 occurs with
APP1 LOW, the command will be disregarded.
Fig.3 Microcontroller timing.
1998 Jan 06 7
MICROCONTROLLER WRITE OPERATION SEQUENCE; It should be noted that APP1 must stay HIGH between
REPEAT MODE APP2 pulses. A minimum pause of 22 µs is necessary
between any two step-up or step-down commands.
The same command can be repeated several times
(e.g. for fade function) by applying APP2 pulses as shown
in Fig.4.
Fig.4 Microcontroller timing; repeat mode.
Table 3 Microcontroller mode control register

BIT POSITION FUNCTION DESCRIPTION ACTIVE LEVEL
D7 ATSB 12 dB attenuation (from full scale) LOW
D6 DSMB double speed LOW
D5 MUSB mute LOW
D4 DEEM de-emphasis HIGH
D3 FS full scale HIGH
D2 INCR increment HIGH
D1 DECR decrement HIGH
D0 − reserved −
1998 Jan 06 8
Volume control VOLUME CONTROL IN PSEUDO-STATIC APPLICATION MODE

A digital level control is incorporated on the TDA1386T In the pseudo-static application mode (APPL = logic 0) the
which performs the function of soft mute and attenuation digital audio output level is controlled by APP0
(pseudo-static application mode) or soft mute, attenuation, (attenuation) and APP2 (mute) so only the final volume
fade, increment and decrement (microcontroller levels full scale, 12 dB (attenuate) and mute (−infin dB)
application mode). The volume control of both channels can be selected. The mute function has priority over the
can be varied in small step changes, determined by the attenuation function. Accordingly, if MUSB is LOW, the
value of the internal fade counter according to: state of ATSB has no effect. An example of volume control
in this application mode is illustrated in Fig.5.
Audio level = counter × maximum level/120.
Where the counter is a 7-bit binary number between
0 and 120. The time taken for mute to vary from 120 to 0
is 120/fs. For example, when fs = 44.1 kHz, the time taken
is approximately 3 ms.
Fig.5 Volume control; pseudo-static application mode.
1998 Jan 06 9
VOLUME CONTROL IN MICROCONTROLLER APPLICATION MODE To control the fade counter in a continuous way, the
INCREMENT and DECREMENT commands are available
In the microcontroller application mode (APPL = logic 1,
(fade control registers D1 and D2). They will increment and
APP3 = logic 0) the audio output level is controlled by
decrement the counter by 1 for each register write
volume control bits ATSB, MUSB, FS, INCR and DECR.
operation. When issuing more than 1 step-up or
Mute is activated by sending the MUSB command to the step-down command in sequence, the write repeat mode
mode control register via the microcontroller interface. The may be used (see microprocessor application mode). An
audio output level will be reduced to zero in a maximum example of volume control in this application mode is
120 steps (depending on the current position of the fade illustrated in Fig.6.
counter) and taking a maximum of 3 ms. Mute, attenuation
and full scale are synchronized to prevent operation in the
middle of a word.
• The counter is preset to 120 by the full scale command.
• The counter is preset to 30 by the attenuate command
when its value is more then 30. If the value of the
counter is less than 30 dB the ATSB command has no
effect.
• The counter is preset to 0 by the mute command MUSB.
• Attenuation (−12 dB) is activated by sending the ATSB
command to the fade control register (D7).
• Attenuation and mute are cancelled by sending the full
scale command to the fade control register (D3).
(1) INCR and DECR in repeat mode.
Fig.6 Volume control; microcontroller application mode.
1998 Jan 06 10
There are two recommended application situations within Double-speed mode

the microcontroller mode:
The double-speed mode is controlled by the DSMB bit at
• The customer wants to use the microcontroller interface register D6 (microcontroller application mode) or by
without the volume setting facility. In this event the activating the APP1 pin (pseudo static application mode).
operation is as follows: When the control bit is active LOW the device operates in
– Mute ON; by sending the MUSB command the double-speed mode.
– Mute OFF; by sending the FS command
Oversampling filter and noise shaper
– Attenuation ON; by sending the ATSB command
The digital filter is a four times oversampling filter. It
– Attenuation OFF; by sending the FS command. consists of two sections which each increase the sample
It is possible to switch from ‘Attenuation ON’ to rate by 2. The noise-shaper operates on 4fs and reduces
‘Mute ON’ but not vice-versa. the in-band noise density.
• Incorporating the volume control feature operates as
follows: DAC and operational amplifiers
– Mute ON; by sending the MUSB command the In this noise shaping DAC a special data code and
microcontroller has to store the previous volume bidirectional current sources are used in order to achieve
setting. true low-noise performance. The special data code
– Mute OFF; by sending succeeding INCR commands guarantees that only small values of current flow to the
until the previous volume is reached. output during small signal passages while larger positive
or negative values are generated using the bidirectional
– Attenuation ON; by sending succeeding DECR
current sources. The noise shaping DAC uses the
commands until a relative downstep of −12 dB is
continuous calibration conversion technique. The DAC
reached. The microcontroller has to store the
currents are repeatedly generated from one single
previous volume.
reference current.
– Attenuation OFF; by sending the succeeding INCR
commands until the previous volume is reached. The operational amplifiers and the internal conversion
resistors RCONV1 and RCONV2 convert the DAC current to
– Volume UP; by sending successive INCR an output voltage available at VOL and VOR. Connecting
commands. an external capacitor between FILTCL and VOL, FILTCR
– Volume DOWN; by sending successive DECR and VOR respectively provides the required first-order
commands. post filtering.
De-emphasis
A digital de-emphasis is implemented in the TDA1386T.
By selecting the DEEM bit at register D4 (microcontroller
application mode) or activating the APP0 pin
(pseudo-static application mode), de-emphasis can be
applied by means of an IIR filter. De-emphasis is
synchronized to prevent operation in the middle of a word.
1998 Jan 06 11
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX UNIT
VDDD digital supply voltage note 1 − 7.0 V
VDDA analog supply voltage note 1 − 7.0 V
VDDO operational amplifiers supply voltage note 1 − 7.0 V
Txtal maximum crystal temperature − +150 °C
Tstg storage temperature −65 +125 °C
Tamb operating ambient temperature −40 +85 °C
Ves electrostatic handling note 2 −2000 +2000 V
note 3 −200 +200 V
Notes
1. All VDD and GND connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT

Rth j-a thermal resistance from junction to ambient in free air 69 K/W
QUALITY SPECIFICATION
In accordance with “UZW-BO/FQ-0601”.
1998 Jan 06 12
DC CHARACTERISTICS
VDDD = VDDA = VDDO = 5 V; Tamb = 5 °C; all voltages referenced to ground (pins 2, 9 and 23); unless otherwise
specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX UNIT
VDDD digital supply voltage (pin 10) note 1 4.5 5.0 5.5 V
VDDA analog supply voltage (pin 1) note 1 4.5 5.0 5.5 V
VDDO operational amplifier supply note 1 4.5 5.0 5.5 V
voltage (pin 24)
IDDD digital supply current fsys = 11.28 MHz − 5 8 mA
IDDA analog supply current at digital silence − 3 6 mA
IDDO operational amplifier supply no operational − 2 4 mA
current amplifier load resistor
Ptot total power dissipation fsys = 11.28 MHz; − 50 90 mW
digital silence;
no operational
amplifier load resistor
VIH HIGH level digital input voltage 0.7VDDD − VDDD + 0.5 V
(pins 3 to 8 and 11 to 17)
VIL LOW level digital input voltage −0.5 − 0.3VDDD V
(pins 3 to 8 and 11 to 17)
Rpd internal pull-down resistor to 17 − 134 kΩ
VSSD (pins 3 and 11)
ILI input leakage current − − 10 µA
CI input capacitance − − 10 pF
Vref reference voltage (pin 22) with respect to OGND 0.45VDDO 0.5VDDO 0.55VDDO V
RCONV current-to-voltage conversion 2.4 3.0 3.6 kΩ
resistor
VFS(rms) full scale output voltage RL > 5 kΩ; note 2 0.935 1.1 1.265 V
(RMS value)
RL output load resistance 5 − − kΩ
Notes
1. All power supply pins (VDD and GND) must be connected to the same external power supply unit.
2. RL is the AC impedance of the external circuitry connected to the audio outputs of the application circuit.
1998 Jan 06 13
AC CHARACTERISTICS (ANALOG)
VDDD = VDDA = VDDO = 5 V; Tamb = 25 °C; all voltages referenced to ground (pins 2, 9 and 23);
unless otherwise specified.
DACs
SVRR supply voltage ripple rejection fripple = 1 kHz; − 40 − dB
pins 9 and 16 Vripple(p-p) = 100 mV;
C22 = 10 µF
∆Vo(DAC) unbalance between the 2 DAC maximum volume − − 0.5 dB
voltage outputs (pins 18 and 21)
αDAC crosstalk between the 2 DAC one output digital silence − −110 −85 dB
voltage outputs (pins 18 and 21) the other maximum volume
(THD + N)/S total harmonic distortion plus at 0 dB signal; fi = 1 kHz − −70 − dB
noise as a function of signal − 0.032 − %
at −60 dB signal; fi = 1 kHz − −42 −32 dB
− 0.8 2.5 %
S/N signal-to-noise ratio fi = 20 Hz to 17 kHz; − −108 −96 dB
A-weighted; no signal
Operational amplifiers
Gv open-loop voltage gain − 85 − dB
PSRR power supply rejection ratio fripple = 3 kHz; − 90 − dB
Vripple(p-p) = 100 mV;
A-weighted
(THD + N)/S total harmonic distortion plus RL > 5 kΩ; − −100 − dB
noise as a function of signal Vo = 2.8 V (p-p);
fi = 1 kHz
fug unity gain frequency open loop − 4.5 − MHz
Zo AC output impedance RL > 5 kΩ − 1.5 150 Ω
1998 Jan 06 14
AC CHARACTERISTICS (DIGITAL)
VDDD = VDDA = VDDO = 4.5 to 5.5 V; Tamb = −40 to +85 °C; all voltages referenced to ground (pins 2, 9 and 23);
unless otherwise specified.
tW clock cycle fsys = 256fs; normal speed 81.3 88.6 156 ns
fsys = 128fs; double speed 81.3 88.6 156 ns
tCWL fsys LOW level pulse width 22 − − ns
tCWH fsys HIGH level pulse width 22 − − ns
Serial input data timing (see Fig.8)
fs word selection input audio sample normal speed 25 44.1 48 kHz
frequency double speed 50 88.2 96 kHz
fBCK clock input frequency (data input rate) fsys = 256fs; normal speed − − 64fs kHz
fsys = 128fs; double speed; − − 48fs kHz
note 1
tr rise time − − 20 ns
tf fall time − − 20 ns
tHB bit clock HIGH time 55 − − ns
tLB bit clock LOW time 55 − − ns
tSU;DAT data set-up time 20 − − ns
tHD;DAT data hold time 10 − − ns
tSU;WS word select set-up time 20 − − ns
tHD;WS word select hold time 10 − − ns
Microcontroller interface timing (see Fig.9)
tL input LOW time 2 − − µs
tH Input HIGH time 2 − − µs
tSU;DC set-up time DATA to CLOCK 1 − − µs
tHD;CD hold time CLOCK to DATA 1 − − µs
tSU;CR set-up time CLOCK to RAB 1 − − µs
Note
1. A clock frequency of up to 96fs is possible in the event that a rising edge of BCK occurs while SYSCLK is LOW.
1998 Jan 06 15
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1998 Jan 06
Philips Semiconductors
Noise shaping filter DAC
16
Product specification
TDA1386T
Fig.7 Data input formats.
Fig.8 Timing of input signals.
Fig.9 Microcontroller timing.
1998 Jan 06 17
TEST AND APPLICATION INFORMATION

Filter characteristics
Table 4 Digital filter specification, fs = 44.1 kHz
BAND ATTENUATION
0 to 19 kHz <0.001 dB
19 to 20 kHz <0.03 dB
24 kHz >25 dB
25 to 35 kHz >40 dB
35 to 64 kHz >50 dB
64 to 68 kHz >31 dB
68 kHz >35 dB
69 to 88 kHz >40 dB
Table 5 Digital filter phase distortion, fs = 44.1 kHz
BAND PHASE DISTORTION

0 to 16 kHz <±1 deg
1998 Jan 06 18
PACKAGE OUTLINE
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D E A
X
y HE v M A
24 13
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 12 detail X
e w M
bp
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)
θ
max.
0.30 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9
mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1
0.10 2.25 0.36 0.23 15.2 7.4 10.00 0.4 1.0 0.4 8o
0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0o
inches 0.10 0.01 0.050 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
95-01-24
SOT137-1 075E05 MS-013AD
97-05-22
1998 Jan 06 19
SOLDERING Wave soldering

Introduction Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when • A double-wave (a turbulent wave with high upward
through-hole and surface mounted components are mixed pressure followed by a smooth laminar wave) soldering
on one printed-circuit board. However, wave soldering is technique should be used.
not always suitable for surface mounted ICs, or for • The longitudinal axis of the package footprint must be
printed-circuits with high population densities. In these parallel to the solder flow.
situations reflow soldering is often used. • The package footprint must incorporate solder thieves at
This text gives a very brief insight to a complex technology. the downstream end.
A more in-depth account of soldering ICs can be found in During placement and before soldering, the package must
our “IC Package Databook” (order code 9398 652 90011). be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
Reflow soldering dispensing. The package can be soldered after the
Reflow soldering techniques are suitable for all SO adhesive is cured.
packages. Maximum permissible solder temperature is 260 °C, and
Reflow soldering requires solder paste (a suspension of maximum duration of package immersion in solder is
fine solder particles, flux and binding agent) to be applied 10 seconds, if cooled to less than 150 °C within
to the printed-circuit board by screen printing, stencilling or 6 seconds. Typical dwell time is 4 seconds at 250 °C.
pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal
Several techniques exist for reflowing; for example, of corrosive residues in most applications.
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating Repairing soldered joints
method. Typical reflow temperatures range from Fix the component by first soldering two diagonally-
215 to 250 °C. opposite end leads. Use only a low voltage soldering iron
Preheating is necessary to dry the paste and evaporate (less than 24 V) applied to the flat part of the lead. Contact
the binding agent. Preheating duration: 45 minutes at time must be limited to 10 seconds at up to 300 °C. When
45 °C. using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1998 Jan 06 20
DEFINITIONS
Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jan 06 21
NOTES
1998 Jan 06 22
NOTES
1998 Jan 06 23
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Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Tel. +46 8 632 2000, Fax. +46 8 632 2745
Hungary: see Austria Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 488 3263
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
Tel. +91 22 493 8541, Fax. +91 22 493 0966 TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Indonesia: see Singapore Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +66 2 745 4090, Fax. +66 2 398 0793
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, Tel. +90 212 279 2770, Fax. +90 212 282 6707
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +1 800 234 7381
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Uruguay: see South America
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880 Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +9-5 800 234 7381 Tel. +381 11 625 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998 SCA57

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 547027/1200/03/pp24 Date of release: 1998 Jan 06 Document order number: 9397 750 03169
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

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INTEGRATED CIRCUITS

Noise shaping filter DAC TDA1386T

FEATURES GENERAL DESCRIPTION

Noise shaping filter DAC TDA1386T

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Noise shaping filter DAC TDA1386T

Fig.1 Block diagram.

Noise shaping filter DAC TDA1386T

SYMBOL PIN DESCRIPTION

Noise shaping filter DAC TDA1386T

Table 1 Data input format and system clock

Device operation In the pseudo-static application mode the TDA1386T is pin

PSEUDO-STATIC APPLICATION MODE (APPL = LOGIC 0)

Table 2 Pseudo-static application mode

Noise shaping filter DAC TDA1386T

MICROCONTROLLER APPLICATION MODE MICROCONTROLLER WRITE OPERATION SEQUENCE

Fig.3 Microcontroller timing.

Noise shaping filter DAC TDA1386T

Fig.4 Microcontroller timing; repeat mode.

Table 3 Microcontroller mode control register

Noise shaping filter DAC TDA1386T

Volume control VOLUME CONTROL IN PSEUDO-STATIC APPLICATION MODE

Fig.5 Volume control; pseudo-static application mode.

Noise shaping filter DAC TDA1386T

(1) INCR and DECR in repeat mode.

Fig.6 Volume control; microcontroller application mode.

Noise shaping filter DAC TDA1386T

There are two recommended application situations within Double-speed mode

Noise shaping filter DAC TDA1386T

SYMBOL PARAMETER VALUE UNIT

Noise shaping filter DAC TDA1386T

Noise shaping filter DAC TDA1386T

Noise shaping filter DAC TDA1386T

Noise shaping filter DAC TDA1386T

Fig.8 Timing of input signals.

Fig.9 Microcontroller timing.

Noise shaping filter DAC TDA1386T

TEST AND APPLICATION INFORMATION

Table 5 Digital filter phase distortion, fs = 44.1 kHz

BAND PHASE DISTORTION

Noise shaping filter DAC TDA1386T

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE REFERENCES EUROPEAN

Noise shaping filter DAC TDA1386T

SOLDERING Wave soldering

Noise shaping filter DAC TDA1386T

Data sheet status

LIFE SUPPORT APPLICATIONS

Noise shaping filter DAC TDA1386T

Noise shaping filter DAC TDA1386T

© Philips Electronics N.V. 1998 SCA57

Datasheets for electronics components.

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