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2024 HPC Lesson PLAN (1) - 1

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12 views6 pages

2024 HPC Lesson PLAN (1) - 1

Hpc

Uploaded by

shubhuannu25
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SCHOOL OF COMPUTER ENGINEERING

KALINGA INSTITUTE OF INDUSTRIAL TECHNOLOGY

DEEMED TO BE UNIVERSITY

BHUBANESWAR

LESSON – PLAN
School : School of Computer Engineering

Program : B. Tech. CSE

Academic Session : Autumn Semester 2024 (July. - November)

Subject : High Performance Computing (HPC)

Course Credit : 3 (L-T-P) (3-0-0) (Weekly 3 Hours)

Semester : 5th Semester

Course Faculty : Dr. Bhabani Shankar Prasad Mishra

Mail_id : ([email protected])

Course Outcomes/Learning Objectives:

Upon completion of the course, the students will be able to:

CO1 : Choose performance metrics to find the performance of systems.

CO2 : Identify the program block that requires parallelism for any program.

CO3: Comprehend the concept of different types of hazards along with the structural
implementation and applications.

CO4: Elaborate the criteria to enhance the performance of the pipelined processors.

CO5: Design algorithms for memory management techniques for multiprocessor system.

CO6: Identify various parallel architecture like centralized and distributed memory architecture
require for real life application

Prerequisite: Computer Architecture (CS21002)


Teaching Pedagogy: Whiteboard/Marker, PowerPoint Presentations, Web Resources
Assessment Methodology: Mid Term: 20; End Term: 50
Distribution of Internal Marks:- Total 50 Marks
Mid Semester Examination = 20 Marks
Activity-based assessment=30 Marks
Activity-based assessment includes Problem Solving, Critical
Thinking, Creation along with Quiz.
LESSON – PLAN

Module No. & Topics/ Coverage Lecture serial Course No of


name / Section Number outcome classes
no. Name

Introduction To Lecture-1(1.1) CO 1
High performance
Unit-1
Architecture

Classes of Lecture-2(1.2) CO-1


Computers

Review of basic Lecture-3 CO-1


computer
(1.3)[Upto Page
architectures
no 14]
Introduction to
instruction Set
architecture 06
(ISA)

Measuring, Lecture 4 (1.8) CO-1


Reporting and
[ONLY Page no
Summarizing
39]
Performance

Quantitative Lecture -5-6(1.9) CO-1


Principles of
Computer Design:
Performance
Measurement
with respect to
the basic
performance
equation (concept
with numerical)
Amdahl’s law
(concept with
Exercises on
speedup and
overall speedup
calculation)

Activity -1 Problem CO1


Solving/Critical
Thinking/Quiz

Basic and Lecture 7-9 CO-2 13


Intermediate
pipelining
Concepts [Cover
Numericals on
Speedup,
Efficiency and
Throughput]

Introduction to Lecture 10-11 CO-2


MIPS [C3]
Architecture
with its data path
Registers in
MIPS
MIPS Instruction
Format(R type,I
Type and J type)

The Major Hurdle Lecture-12-18 CO-3


Unit II
of Pipelining- [C2]
Pipeline Hazards
A brief
Lecture 12
introduction to
Hazard and Types
of Hazards
(Concepts and
exercises)
Structural Lecture-13
Hazard
Data Hazard Lecture-14
(Inter-
instruction
dependency with
suitable
examples:)
Control Hazard

Pipeline Stall Lecture-15


Cycles and its
possible effects
on performance
(Concepts and
exercises)

A technique for CO-3


overcoming or
reducing the
effects of
Various hazards
(Solutions to
different Lecture-16
Hazards)
(concepts and
numericals)
Operand
Lecture -17
forwarding and
Instruction
scheduling
Flush pipeline,
Branch
Prediction, Delay
Slot Lecture -18

Implementation C4
issues that makes
Pipelining hard

Extending the C5 L-19


MIPS Pipeline to
Handle Multicycle
Operations

The MIPS R4000 C6


Pipeline.

Activity -2 CO-3

Unit - III Instruction, Level Lecture- 20 [3.1] CO-4


Parallelism:
Concepts and
Challenges

Basic Compiler Lecture-21-22 CO-4 08


[3.2]
Techniques for
Exposing ILP
(Loop unrolling
and scheduling
(concepts with
Numerical)

MIDSEM

Overcoming Data Lecture-23-25 CO-4


Hazards with
[3.4] & [3.5]
Dynamic
Scheduling
[Scoreboard and
Tomasulo
algorithm with
example

Exploiting ILP Lecture-26-27 CO-4


Using Multiple
[3.7]
Issue and Static
Scheduling.
(Super- scalar &
Super pipelined,
VLIW processor
architecture

Activity-3 CO-4

Unit - IV Vector Lecture-28 CO-6 06


Architecture,
Graphics
Processing Units

Centralized Lecture-29- CO-6


Shared-Memory 30[5.2] [Pg No
Architectures 377-388]

Distributed Lecture-31-32 CO-6


Shared Memory
[5.4]
Multicore Lecture-33 [5.8] CO-6
Processors

Activity-4 Problem CO-6


Solving/Critical
Thinking/Quiz

Unit- V Review of Memory Lecture-34 CO-5 07


Hierarchy Design

Cache Lecture-35- CO-5


Performance and 37[B1] and [B2]
Numericals

Basic Cache Lecture-38-40 CO-5


Optimizations [B3]
[Numericals]

Advanced [2.3] CO-5


Optimizations of
Cache
Performance

Activity 5 and Problem CO-5


Activity 6 Solving/Critical
Thinking/Quiz

Textbooks:

1. David. A. Patterson, John L. Hennessy, “Computer Architecture: A Quantitative approach”, Sixth


Edition, Morgan Kaufmann, 2012.
Reference Books:

1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer Organization and
Embedded Systems”, Sixth Edition, McGraw Hill Inc, 2022.

2. William Stallings “Computer Organization and Architecture”, Eleventh Edition, Pearson Education,
2006.

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