Ministry of Higher Education and

Scientific Research - Iraq

University of Technology
Computer Science Department
Software Branch

MODULE DESCRIPTOR FORM

‫ﺔ‬2‫ﻧﻤﻮذج وﺻﻒ اﻟﻤﺎدة اﻟﺪراﺳ‬
Module Information
‫ﻣ ﻌ ﻠﻮ ﻣ ﺎت اﻟﻤ ﺎد ة اﻟﺪر اﺳ ﯿﺔ‬
Module Title LOGIC DESIGN Module Delivery

Module Type CORE Theory

Lecture
Module Code LODE123 Lab
ECTS Credits 6 Tutorial
Practical
SWL (hr/sem) 150 Seminar

Module Level UGx11 1 Semester of Delivery 2

Administering Department Type Dept. Code College Type College Code
Module Leader Enas Tariq e-mail [email protected]
Module Leader’s
Module Leader’s Acad. Title Lecturer Msc
Qualification
Module Tutor None e-mail None
Peer Reviewer Name e-mail
Review Committee Approval 01/06/2023 Version Number 1.0

Relation With Other Modules

‫اﻟﻌ ﻼ ﻗﺔ ﻣ ﻊ اﻟﻤ ﻮ اد اﻟﺪ ر اﺳ ﯿﺔ اﻷ ﺧ ﺮ ى‬
Prerequisite module None Semester
Co-requisites module None Semester

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 Module Aims, Learning Outcomes and Indicative Contents
‫أ ھ ﺪ اف ا ﻟ ﻤ ﺎ د ة ا ﻟ ﺪ ر ا ﺳ ﯿ ﺔ و ﻧ ﺘ ﺎ ﺋ ﺞ ا ﻟ ﺘ ﻌ ﻠ ﻢ و ا ﻟ ﻤ ﺤ ﺘ ﻮ ﯾ ﺎ ت ا ﻹ ر ﺷ ﺎ د ﯾ ﺔ‬
1. To introduce students to the fundamental concepts and principles of logic
design.
Module Aims 2. To develop students' skills in designing and analyzing digital logic circuits.
‫أھﺪاف اﻟﻤﺎدة اﻟﺪراﺳﯿﺔ‬ 3. To enable students to apply logic design techniques to solve practical
engineering problems.
4. To enhance students' understanding of the relationship between logic
design and computer architecture.
By the end of this module, students should be able to:

1.Understand the basic principles of Boolean algebra and logic gates.

2.Design, analyze, and optimize combinational logic circuits.

Module Learning
3.Design, analyze, and optimize sequential logic circuits.
Outcomes
4.Utilize programmable logic devices (PLDs) and field-programmable gate
‫ﻣﺨﺮﺟﺎت اﻟﺘﻌﻠﻢ ﻟﻠﻤﺎدة اﻟﺪراﺳﯿﺔ‬ arrays (FPGAs) for logic design.
5.Apply simulation and verification techniques to validate the functionality
of logic circuits.

6.Understand the role of logic design in computer architecture and digital

systems.

1.Introduction to Logic Design

. Overview of digital systems and their components
. Binary number systems and codes
. Boolean algebra and logic operations

2.Logic Gates and Combinational Logic Circuits

. Basic logic gates (AND, OR, NOT, etc.) and their truth tables
. Simplification techniques (Boolean algebra, Karnaugh maps)
. Combinational logic circuits (adders, multiplexers, decoders, etc.)
Indicative Contents . Timing analysis and hazards in combinational circuits
‫اﻟﻤﺤﺘﻮﯾﺎت اﻹرﺷﺎدﯾﺔ‬
3.Sequential Logic Circuits
. Flip-flops, latches, and registers
. Analysis and design of sequential circuits (state machines)
. Synchronous and asynchronous sequential circuits
. Timing considerations and clocking methodologies

4.Programmable Logic Devices (PLDs) and FPGAs

. Introduction to PLDs and FPGAs

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 . Implementation of logic circuits using PLDs and FPGAs
. Configuration programming and hardware description languages (HDLs)

5.Simulation and Verification

. Simulation tools for logic design (e.g., VHDL, Verilog)
. Functional and timing simulation
. Verification techniques (testbenches, formal verification)

6. Logic Design and Computer Architecture

. Relationship between logic design and computer architecture
. Introduction to processor design and memory systems
. Logic design considerations for high-performance systems

Learning and Teaching Strategies

‫اﺳ ﺘﺮ اﺗﯿﺠ ﯿ ﺎ ت اﻟﺘﻌ ﻠﻢ و اﻟﺘﻌ ﻠﯿﻢ‬

1.Conceptual Understanding: Focus on explaining fundamental concepts

and principles of logic design, such as Boolean algebra, logic gates, and truth
tables.
2.Visual Representations: Utilize diagrams and flowcharts to visually
illustrate the structure and behavior of logic circuits.
3.Hands-on Activities: Provide opportunities for students to design and
implement logic circuits using simulation software, breadboards, or
hardware platforms.
4.Problem Solving: Assign problem-solving exercises and assignments that
require students to analyze, design, and optimize logic circuits.
5.Real-World Applications: Relate logic design concepts to practical
Strategies applications in computer processors, digital systems, and electronic devices.
6.Group Collaboration: Encourage collaborative learning through group
projects and activities to foster teamwork and communication skills.
7.Simulation and Verification: Use logic simulation software or hardware
description languages to simulate and verify logic circuits' functionality.
8.Error Analysis: Discuss common errors in logic design and guide students
in identifying and rectifying mistakes in their designs.
9.Industry Practices: Introduce students to industry-standard design
practices, tools, and methodologies used in logic design.
10.Assessment and Feedback: Regularly assess students' understanding
through quizzes and provide constructive feedback to guide their learning
and improvement..

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 Student Workload (SWL)
‫اﻟﺤ ﻤ ﻞ اﻟﺪ ر اﺳ ﻲ ﻟﻠﻄ ﺎﻟﺐ‬
Structured SWL (h/sem) Structured SWL (h/w)
88 6
‫اﻟﺤﻤﻞ اﻟﺪراﺳﻲ اﻟﻤﻨﺘﻈﻢ ﻟﻠﻄﺎﻟﺐ ﺧﻼل اﻟﻔﺼﻞ‬ ‫اﻟﺤﻤﻞ اﻟﺪراﺳﻲ اﻟﻤﻨﺘﻈﻢ ﻟﻠﻄﺎﻟﺐ أﺳﺒﻮﻋﯿﺎ‬
Unstructured SWL (h/sem) Unstructured SWL (h/w)
62 4.4
‫اﻟﺤﻤﻞ اﻟﺪراﺳﻲ ﻏﯿﺮ اﻟﻤﻨﺘﻈﻢ ﻟﻠﻄﺎﻟﺐ ﺧﻼل اﻟﻔﺼﻞ‬ ‫اﻟﺤﻤﻞ اﻟﺪراﺳﻲ ﻏﯿﺮ اﻟﻤﻨﺘﻈﻢ ﻟﻠﻄﺎﻟﺐ أﺳﺒﻮﻋﯿﺎ‬
Total SWL (h/sem)
150
‫اﻟﺤﻤﻞ اﻟﺪراﺳﻲ اﻟﻜﻠﻲ ﻟﻠﻄﺎﻟﺐ ﺧﻼل اﻟﻔﺼﻞ‬

Module Evaluation
‫ﺗﻘﯿﯿﻢ اﻟﻤﺎدة اﻟﺪراﺳﯿﺔ‬
Time/Nu Relevant Learning
Weight (Marks) Week Due
As mber Outcome
Quizzes 2 10% (10) 5, 10 LO #1, 2, 3,4,5 and 6
Formative Assignments 2 10% (10) 2, 12 LO #1, 2, 3,4,5 and 6
assessment Projects / Lab. 1 10% (10) Continuous
Report 1 10% (10) 13 LO #1, 2, 3,4,5 and 6
Summative Midterm Exam 2 hr 10% (10) 7 LO #1, 2, 3,4,5 and 6
assessment Final Exam 2hr 50% (50) 16 All
Total assessment 100% (100 Marks)

Delivery Plan (Weekly Syllabus)

‫اﻟﻤ ﻨﮭ ﺎج اﻻ ﺳ ﺒﻮ ﻋ ﻲ اﻟﻨﻈ ﺮ ي‬
Week Material Covered
Ø Number system
Week 1 • Decimal.
• Binary
Week 2
• Octal.
• Hexadecimal
Ø Addition and subtraction
Week 3
• binary
• octal
• Hexadecimal.
Week 4 Ø Logic gates.

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 Week 5 Ø Boolean algebra and simplification and demorgan’s.
Week 6 Ø K-map.
Week 7 Ø Combinational universal NAND and NOR logic.
Week 8
Ø Half-adder
Ø full-adder
Week 9 Ø 4- bit parallel adder, and Subtract adder.
Week 10 Ø Decoder, encoder
Week 11 Ø multiplexer, and demultiplexer.
Week 12 Ø Sequential logic circuits and Flip-flop, SR, D, and JK flip-flop.
Week 13 Ø Shift register 3-bit and 4-bit.
Week 14 Ø Binary counter 3-bit and 4-bit.
Week 15 Preparatory Week
Week 16 Final Exam

Delivery Plan (Weekly Lab. Syllabus)

‫اﻟﻤ ﻨﮭ ﺎج اﻻ ﺳ ﺒﻮ ﻋ ﻲ ﻟﻠﻤ ﺨ ﺘﺒﺮ‬
Week Material Covered
Week 1 Lab 1: Logic gates.
Week 2 Lab 2: Boolean algebra and simplification and demorgan’s
Week 3 Lab 3: K-map, Half-adder, full-adder
Week 4 Lab 4: 4-bit parallel adder, and Subtract adder
Week 5 Lab 5: Decoder, encoder, multiplexer, and demultiplexer
Week 6 Lab 6: Sequential logic circuits and Flip-flop, SR, D, and JK flip-flop
Week 7 Lab 7: Shift register 3-bit and 4-bit, Binary counter 3-bit and 4-bit.

Learning and Teaching Resources

‫ﻣ ﺼ ﺎدر اﻟﺘﻌ ﻠﻢ و اﻟﺘﺪر ﯾﺲ‬
Available in the
Text
Library?

Required Texts Yes

1. Computer System Architecture M.Morris Mano
Recommended
No
Texts

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 2. Digital fundamentals by Floyd, 2009

Websites 3. Fundamental of digital logic and Microcomputer design, fifth addition.

APPENDIX:

GRADING SCHEME
‫ﻣ ﺨ ﻄ ﻂ اﻟ ﺪ ر ﺟ ﺎ ت‬
Group Grade ‫اﻟﺘﻘﺪﯾﺮ‬ Marks (%) Definition
A - Excellent ‫اﻣﺘﯿﺎز‬ 90 - 100 Outstanding Performance
B - Very Good ‫ﺟﯿﺪ ﺟﺪا‬ 80 - 89 Above average with some errors
Success Group
C - Good ‫ﺟﯿﺪ‬ 70 - 79 Sound work with notable errors
(50 - 100)
D - Satisfactory ‫ﻣﺘﻮﺳﻂ‬ 60 - 69 Fair but with major shortcomings
E - Sufficient ‫ﻣﻘﺒﻮل‬ 50 - 59 Work meets minimum criteria
Fail Group FX – Fail ‫ﻣﻘﺒﻮل ﺑﻘﺮار‬ (45-49) More work required but credit awarded
(0 – 49) F – Fail ‫راﺳﺐ‬ (0-44) Considerable amount of work required

Note:
NB Decimal places above or below 0.5 will be rounded to the higher or lower full mark (for example a mark of 54.5
will be rounded to 55, whereas a mark of 54.4 will be rounded to 54. The University has a policy NOT to condone
"near-pass fails" so the only adjustment to marks awarded by the original marker(s) will be the automatic rounding
outlined above.

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