Ch4
Computer Memory System
Manal Abdulelah Areqi
[email protected] Memory Systems
• Type of memory :
➢ Internal memory, directly accessible by
the processor.
➢ External memory, accessible by the
processor via an I/O module.
Characteristics of Memory Systems
Characteristics of Memory Systems
Characteristics of Memory Systems
Location
• Refers to whether memory is internal and
external to the computer
• Internal memory
❖ main memory
❖ registers
❖ Cache
External memory consists of peripheral
storage devices that are accessible to the
processor via I/O controllers.
Characteristics of Memory Systems
Capacity
• Memory is typically expressed in
terms of the number of words or
Bytes.
• Word size
➢ Common word size: 8, 16, 32 bits.
Characteristics of Memory Systems
Unit of transfer
• Internal memory
➢ The number of bits read out of or written into
memory at a time.
➢ Usually governed by data bus width.
• External memory
➢ Usually, a block that is much larger than a word
• Addressable unit
➢ The smallest location that can be uniquely
addressed
Characteristics of Memory Systems
Access Method
Sequential Direct Random
Associative
access access access
Memory is Involves a shared Individual addresses A word is retrieved
organized into read-write identify locations based on a portion of
units of data mechanism exactly its contents rather
called records. than its address
Individual blocks or The time to access a
Access must be records have a unique given location is Each location has its
made in a address based on independent of the own addressing
specific linear physical location sequence of prior mechanism and
sequence. accesses and is retrieval time is
Access time Access time depends constant constant independent
depends on the on location and the of location or prior
location of data previous location, Any location can be access patterns
and previous access time is selected at random
location, access variable and directly e.g. Cache
time is variable addressed and
accessed
e.g. disk
e.g. tape
e.g. some cache
systems and RAM
Characteristics of Memory Systems
Capacity and Performance
Three performance parameters are used:
Access time Memory cycle Transfer rate
(latency) time
• The rate at which
• Access time plus any data can be
• For random-access additional time required
memory it is the transferred into or
before second access out of a memory
time it takes to can commence (Start
perform a read or To End).
unit
write operation • For random-access
• For non-random- memory it is equal
access memory it is to 1/(cycle time)
the time it takes to
position the read-
write mechanism at
the desired location
Characteristics of Memory Systems
Physical Type
The most common forms are:
• Semiconductor memory
➢ RAM & ROM
• Magnetic surface memory
➢ Disk & Tape
Optical
➢ CD & DVD
• Magneto
Characteristics of Memory Systems
Physical Characteristics
◦Volatile memory
◦Information decays naturally or is lost when electrical
power is switched off
◦Nonvolatile memory
◦Once recorded, information remains without
deterioration until deliberately changed
◦No electrical power is needed to retain information
◦Magnetic-surface memories: Are nonvolatile
◦Semiconductor memory: May be either volatile or
nonvolatile
Characteristics of Memory Systems
Physical Characteristics
Nonerasable memory
◦Cannot be altered, except by destroying the
storage unit
◦Semiconductor memory of this type is known as
(ROM)
Memory Hierarchy
• The way out of the memory dilemma is not to rely on a single
memory component or technology, but to employ a memory
hierarchy.
Characteristics of Memory Systems
Memory Hierarchy
• Some fundamental and enduring properties of hardware and
software:
➢ Fast storage technologies cost more per byte and have less
capacity
➢ Gap between CPU and main memory speed is widening
• They suggest an approach for organizing memory and storage
systems known as a memory hierarchy
• The goal of a memory hierarchy
➢ to keep the data that is accessed most high up the hierarchy, so it
can be accessed quickly
➢ the least used at the bottom of the hierarchy.
Smaller,
faster,
and
costlier
(per byte)
storage
devices
Larger,
slower,
and
cheaper
(per byte)
storage
devices
Characteristics of Memory Systems
CPU registers hold words
Smaller, retrieved from L1 cache
faster, L0: registers
and L1 cache holds cache lines
on-chip L1 retrieved from the L2 cache
costlier L1:
memory
cache (SRAM)
(per byte)
storage L2: off-chip L2 L2 cache holds cache lines
devices cache (SRAM) retrieved from main memory
L3: main memory Main memory holds disk
Larger, (DRAM) blocks retrieved from local
slower, disks
and
cheaper L4: local secondary storage
(per byte) (local disks) Local disks hold
files retrieved from
storage disks on remote
devices network servers
L5: remote secondary storage
(distributed file systems, Web servers)
Memory Hierarchy
Cache/Main Memory Structure
Cache Read Operation
Miss
Hit
Caching in a Memory Hierarchy
Smaller, faster, more expensive
device at level k caches a
Level k: 48 9 14
10 3
subset of the blocks from level k+1
Data is copied between
10
4 levels in block-sized transfer units
0 1 2 3
4 5 6 7 Larger, slower, cheaper storage
Level k+1:
device at level k+1 is partitioned
8 9 10 11 into blocks.
12 13 14 15
General Caching Concepts
Program needs object d, which is
14
12 Request stored in some block b
12
14
0 1 2 3
Cache hit
Level 4*
12 9 14 3
◦ Program finds b in the cache at level k.
k: E.g., block 14
Request
Cache miss
12
4*
12 ◦ b is not at level k, so level k cache must
fetch it from level k+1. E.g., block
12
0 1 2 3 ◦ If level k cache is full, then some current
block must be replaced (evicted). Which
Level 44* 5 6 7
one is the “victim”?
k+1: 8 9 10 11 ◦ Placement policy: where can the new block go?
12 13 14 15 E.g., b mod 4
◦ Replacement policy: which block should be
evicted? E.g., LRU
ELEMENTS OF CACHE DESIGN
Elements of Cache Design
Cache Addresses Write Policy
Logical Write through
Physical Write back
Cache Size Line Size
Mapping Function Number of caches
Direct Single or two level
Associative Unified or split
Set Associative
Replacement Algorithm
Least recently used (LRU)
First in first out (FIFO)
Least frequently used (LFU)
Random
ELEMENTS OF CACHE DESIGN
Cache Addresses
Virtual memory
• A computer can address more memory than the
amount physically installed on the system.
• This extra memory is actually called virtual
memory and it is a section of a hard disk that's
set up to emulate the computer's RAM.
• When used, the address fields of machine
instructions contain virtual addresses.
A System with Virtual Memory
Address Translation: The hardware converts virtual addresses into physical
addresses via an OS-managed lookup table (page table)
For reads to and writes from main memory, a hardware memory management unit
(MMU) translates each virtual address into a physical address in main memory.
ELEMENTS OF CACHE DESIGN
Mapping Function
Direct Associative Set Associative
• Permits each main
memory block to be • A compromise
• Maps each loaded into any line of the that exhibits the
cache
block of main strengths of both
• To determine whether a
memory into block is in the cache, the the direct and
only one cache control logic must associative
simultaneously examine
possible cache every line’s Tag for a approaches
line match . while reducing
• any to any their
• Many to one. disadvantages
Direct Mapping
• The simplest technique
• Maps each block of main memory into only one possible cache line
• Many to one.
Associative Mapping
• Permits each main memory block to be loaded into any line of the cache
• The cache control logic interprets a memory address simply as a Tag and a Word field
• To determine whether a block is in the cache, the cache control logic must
simultaneously examine every line’s Tag for a match .
• any to any
Set Associative
Direct Mapping Associative Mapping
The most common replacement
algorithms are:
Least recently used (LRU)
• Most effective
• Replace that block in the set that has been in the cache longest with no
reference to it
• Because of its simplicity of implementation, LRU is the most popular
replacement algorithm
First-in-first-out (FIFO)
• Replace that block in the set that has been in the cache longest.
• Easily implemented as a round-robin or circular buffer technique
Least frequently used (LFU)
• Replace that block in the set that has experienced the fewest
references
• Could be implemented by associating a counter with each line.
ELEMENTS OF CACHE DESIGN
Write Policy
When a block that is resident in the cache is to be replaced
there are two cases to consider:
If the old block in the cache has not been altered (changed)
then it may be overwritten with a new block without first
writing out the old block
If at least one write operation has been performed on a
word in that line of the cache then main memory must be
updated by writing the line of cache out to the block of
memory before bringing in the new block
ELEMENTS OF CACHE DESIGN
Write Policy
There are two problems to contend with:
More than one device may have access to main memory
A more complex problem occurs when multiple
processors are attached to the same bus and each processor
has its own local cache - if a word is altered(changed) in
one cache it could conceivably invalidate a word in other
caches
Write Through Write back
◦All write operations ◦Updates are made only in
are made to main the cache
memory as well as to ◦Portions of main memory
the cache are invalid and hence
◦The main accesses by I/O modules
disadvantage of this can be allowed only
technique is that it through the cache
generates substantial ◦This makes for complex
(large) memory traffic. circuitry.
ELEMENTS OF CACHE DESIGN
Number of Caches
• Two-level cache:
➢ Internal cache designated as level 1 (L1)
➢ External cache designated as level 2 (L2)
• The use of multilevel caches
complicates all of the design issues
related to caches, including size,
replacement algorithm, and write
policy
Unified Versus Split Caches
• Has become common to split cache:
➢ One dedicated to instructions
➢ One dedicated to data
➢ Trend is toward split caches at the L1 and
unified caches for higher levels.
