EEE 213 - v8
EEE 213 - v8
• Additional Resource:
• Logic Simulator (hneemann/Digital: A digital logic
designer and circuit simulator. (github.com))
• Tinkercad (https://www.tinkercad.com/)
WHY
• Electronics
• Analog: RLC, Transistors, Amplifiers, Filters, Electromagnetic, Antenna etc.
• Digital: Logic Gates, Logic IC’s, Microcontrollers, FPGA etc.
HISTORY OF LOGIC
• ‘Logic’ originates from Greek word ‘logos’, means ‘reason’
1. Categories
2. On Interpretation
3. Prior Analytics
4. Posterior Analytics
5. Topics
6. On Sophistical Refutations
EXAMPLES OF ARISTOTELES LOGIC
Aristotle’s central observation was to check validity of arguments based on their logical
structure. Aristotle, in his work "Sophistical Refutations," aimed to expose and
demonstrate the invalidity of various fallacies used by sophists.
Claude Shannon introduced the use of Boolean algebra in the analysis and design of
switching circuits in 1936 (Master Thesis).
SHANON APPLICATION OF BOOLEAN ALGEBRA
Open=1, Close=0 : X.Y
Open=1, Close=0 : X + Y
Cahit ARF: Can a machine think?
• Using only relays Boolean
algebra can be implemented
completely
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DECIMAL to BINARY
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Converting integer numbers to binary
• divide to 2 till 1 or 0, write remainders in REVERSE order
• LEFTMOST BIT is the MOST SIGNIFICANT BIT of the number
BINARY to DECIMAL
• While converting from binary to decimal: multiply and add binary value of bit and decimal value of
the bit position
32 16 8 4 2 1 2^x
1 0 1 0 0 1 Binary
32 0 8 0 0 1 =41
LOGIC GATES to COMPUTERS
While Claude Shannon showed how to map logic onto the physical world, Alan Turing showed how
to design computers in the language of mathematical logic. In 1945, he wrote the specification of the
EDVAC—the first stored program, logic-based computer—which is generally considered the
definitive source guide for modern computer design.
Two-Valued Boolean Algebra
One can formulate many Boolean algebras, depending on the choice of elements of
B and the rules of operation. In our subsequent work, we deal only with a two-valued
Boolean algebra (i.e., a Boolean algebra with only two elements).
two binary operators + and . as shown in the following operator tables (the rule
for the complement operator is for verification of postulate 5)
AND OR NOT
Huntington Postulates
Huntington introduced a set of postulates known as "Huntington's Postulates" that describe the
fundamental properties of Boolean algebra in 1904. These postulates provide a basis for
manipulating logical expressions and establishing the laws of Boolean algebra
Huntington postulates are valid for the set B = {0, 1} and the two binary operators + and .
Huntington Postulates
1. That the structure is CLOSED with respect to the two operators is obvious from the
tables, since the result of each operation is either 1 or 0 and 1, 0 ∈ B.
5. For every element x ∈ B, there exists an element x′ ∈ B called the complement of x such that
(a) x + x′ = 1
(b) x . x′ = 0
6. There exist at least two elements x, y ∈ B such that x ≠ y, x=1, y=0 and 1 ≠0
Huntington Postulates
• Table 2.1 lists six theorems of Boolean algebra and four of its postulates.
• The notation is simplified by omitting ‘.’
• The theorems and postulates listed are the most basic relationships in Boolean algebra.
• The theorems, like the postulates, are listed in pairs; each relation is the dual of the one paired with it.
• The postulates are basic axioms of the algebraic structure and need no proof.
• The theorems must be proven from the postulates.
Postulates and Theorems of Boolean Algebra
The theorems of Boolean algebra can be proven by means of
truth tables
• THEOREM 1(a): x + x = x
• THEOREM 1(b): x . x = x
• THEOREM 2(a): x + 1 = 1
• THEOREM 2(b): x . 0 = 0
F1 = x + y′z
X’ i called as :
• X’s complement,
• X prime
• not X
Truth Table to Algebraic Expression (Minterms)
• Given the truth table of F2, Find logical expression of F2
x y z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Truth Table to Algebraic Expression (catcheven)
• design a logic which catches even numbers, 3-bit input
x y z F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
ANALOG to DIGITAL Converters (ADC)
x y z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0 F=xy’z + xyz’ + xyz
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
2.7. Other Logical Operations
• We are not limited to AND OR NOT Gates, other Gates are also may help to reduce
number of gates
• Let us evaluate all possible truth table combinations of two variable functions
• This task is well understood, but is difficult to execute by manual methods when the logic has more
than a few inputs.
• Fortunately, this dilemma has been solved by computer-based logic synthesis tools that minimize a
large set of Boolean equations efficiently and quickly.
x y z F
0 0 0 0
0 0 1 0 y’ y
0 1 0 0 F y’z’ y’z yz yz’
0 1 1 0 x/yz 00 01 11 10
1 0 0 1 x’ 0
1 0 1 1 x 1 1 1 1 1
1 1 0 1
1 1 1 1
Three Variable Karnaugh Map
• FIND THE COMMON VARIABLE(S) OF ADJACENT SQUARES
• F1=x
• F2=x’
y’ y y’ y
x/yz 00 01 11 10 x/yz 00 01 11 10
x’ 0 x’ 0 1 1 1 1
x 1 1 1 1 1 x 1
Three Variable Karnaugh Map
• FIND THE COMMON VARIABLE(S) OF ADJACENT SQUARES
• F1=y
• F2=y’
y’ y y’ y
F1 y’z’ y’z yz yz’ F2 y’z’ y’z yz yz’
x/yz 00 01 11 10 x/yz 00 01 11 10
x’ 0 1 1 x’ 0 1 1
x 1 1 1 x 1 1 1
Three Variable Karnaugh Map
• FIND THE COMMON VARIABLE(S) OF ADJACENT SQUARES
• F1=z
• F2=z’
y’ y y’ y
F1 y’z’ y’z yz yz’ F2 y’z’ y’z yz yz’
x/yz 00 01 11 10 x/yz 00 01 11 10
x’ 0 1 1 x’ 0 1 1
x 1 1 1 x 1 1 1
Three Variable Karnaugh Map
• FIND THE COMMON VARIABLE(S) OF ADJACENT SQUARES
• F1=x’y’
• F2=xy
y’ y y’ y
F1 y’z’ y’z yz yz’ F2 y’z’ y’z yz yz’
x/yz 00 01 11 10 x/yz 00 01 11 10
x’ 0 1 1 x’ 0
x 1 x 1 1 1
Three Variable Karnaugh Map
• FIND THE COMMON VARIABLE(S) OF ADJACENT SQUARES
• F1=y’z’
• F2=yz
y’ y y’ y
F1 y’z’ y’z yz yz’ F2 y’z’ y’z yz yz’
x/yz 00 01 11 10 x/yz 00 01 11 10
x’ 0 1 x’ 0 1
x 1 1 x 1 1
Three Variable Karnaugh Map
• Simplify the Boolean function F =x’yz’ + x’yz + xy’z’ + xy’z
• Focus on only 1’s
x y z F
F = x’y’z’ + x’yz’ + xy’z’ + xy’z +xyz’ F=z’ + xy’
0 0 0 1
0 0 1 y’ y
0 1 0 1 y’z’ y’z yz yz’
0 1 1 x/yz 00 01 11 10
1 0 0 1 x’ 0 1 1
1 0 1 1 x 1 1 1 1
1 1 0 1
1 1 1
Three Variable Karnaugh Map
if expression is given we dont need to create to the truth table we can fill Karnaugh Map
F = x’z + x’y + xy’z +yz F=z + x’y
y’ y
y’z’ y’z yz yz’
x/yz 00 01 11 10
x’ 0 1 1 1
x 1 1 1
Dont Care Conditions
• In practice, in some applications the function is not specified for certain combinations of the
variables
• These don’t-care conditions can be used on a map to provide further simplification of the Boolean
expression. So you can assume 1 or 0 as you like for further simplification
• Consider following example
x y z F
if X=0 F=xy’+x’y but if Xdontcare=1 we
0 0 0 X can further sımplify to
0 0 1 X y’ y
F=y’+x’y
0 1 0 1 y’z’ y’z yz yz’
0 1 1 1 x/yz 00 01 11 10
1 0 0 1 x’ 0 X X 1 1
1 0 1 1 x 1 1 1
1 1 0 0
1 1 1 0
Four Variable Karnaugh Map
• Maps for more than three variables are difficult to use and will not be considered in the lecture.
NAND Gate
• The NAND gate is said to be a universal gate because any logic circuit can be implemented with it.
To show that any Boolean function can be implemented with NAND gates, we need only to show
that the logical operations of AND, OR, and complement can be obtained with NAND gates alone
NAND Gate: Implementation
• The implementation of two-level Boolean
functions with NAND gates requires that
the functions be in sum-of-products form
• F=AB + CD
F = xz + xy
4.2. Combinational Logic Circuits
• A combinational circuit consists of an interconnection of logic gates. Combinational logic gates react
to the values of the signals at their inputs and produce the value of the output signal, transforming
binary information from the given input data to a required output data
• The logic diagram of a combinational circuit has logic gates with no feedback paths or memory
elements.
Logic Diagram to Expression
Starting from input to output, construct the expression
F = ABC + (A+B+C)(AB+AC+BC)’
ABC
A+B+C
AB (AB+AC+BC)’
AC AB+AC+BC
BC
Logic Diagram to Expression
DESIGN GUIDE
1. Description of function
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DECIMAL to BINARY
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Converting integer numbers to binary
• divide to 2 till 1 or 0, write remainders in REVERSE order
• LEFTMOST BIT is the MOST SIGNIFICANT BIT of the number
BINARY to DECIMAL
• Convert binary number to decimal
• MULTIPLY by 2^n and SUM
• LEFTMOST BIT is the MOST SIGNIFICANT BIT of the number
2^n 32 16 8 4 2 1
BINARY 1 0 1 0 0 1
MULTIPLY 32 8 1
SUM 41
HALF ADDER = 2bit adder
• A combinational circuit that performs the addition of two bits is called a half adder
DEC
0
1
1
2
Full Adder = 3bit adder
• A full adder is a combinational circuit that forms the arithmetic sum of three bits.
• It consists of three inputs and two outputs.
• Two of the input variables, denoted by x and y, represent the two significant bits to be added.
• The third input, z, represents the carry from the previous lower significant position.
• The two outputs are designated by the symbols S for sum and C for carry.
• In order to go step by step let us develop 2 bit adder (Half Adder) first
• As it is seen, ,n order to perform full adding operation we need 3-bit adder. 2bit adder (half adder)
is not enough
Electric Adder to the Base Two
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Idea has been presented in Shannon 1938 thesis
Full Adder (three bits adder)
• A full adder is a combinational circuit that forms the arithmetic sum of three bits.
• It consists of three inputs and two outputs.
• Two of the input variables, denoted by x and y, represent the two significant bits to be added.
• The third input, z, represents the carry from the previous lower significant position.
• The two outputs are designated by the symbols S for sum and C for carry.
DEC
0
1
1
2
1
2
2
3
FULL ADDER
• One that performs the addition of three
bits (two significant bits and a previous
carry) is a full-adder.
BINARY ARITHMETIC
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Converting integer numbers to binary
• Arithmetic operations with numbers in base 2 follow the same rules as for decimal numbers.
• full adder with carry, augend and addend
carry 1 0 1 1 1 1 𝑐𝑘+1 𝑐𝑘 … 𝑐3 𝑐2 𝑐1
𝑎𝑘 … 𝑎3 𝑎2 𝑎1 𝑎0
augend 1 0 1 1 0 1 𝑏𝑘 … 𝑏3 𝑏2 𝑏1 𝑏0
addend 1 0 0 1 1 1 +______________________
sum 1 0 1 0 1 0 0 𝑐𝑘+1 𝑠𝑘 … 𝑠3 𝑠2 𝑠1 𝑠0
BINARY ARITHMETIC
BINARY 1 0 1 1 0 1
2^n 32 16 8 4 2 1 45
MULTIPLY 32 8 4 1
39 𝑐𝑘+1 𝑐𝑘 … 𝑐3 𝑐2 𝑐1
SUM 45
+____ 𝑎𝑘 … 𝑎3 𝑎2 𝑎1 𝑎0
BINARY 1 0 0 1 1 1 𝑏𝑘 … 𝑏3 𝑏2 𝑏1 𝑏0
2^n 32 16 8 4 2 1
84 +______________________
𝑐𝑘+1 𝑠𝑘 … 𝑠3 𝑠2 𝑠1 𝑠0
MULTIPLY 32 4 2 1
SUM 39
carry 1 0 1 1 1 1
BINARY 1 0 1 0 1 0 0 augend 1 0 1 1 0 1
2^n 64 32 16 8 4 2 1 addend 1 0 0 1 1 1
MULTIPLY 64 16 4 sum 1 0 1 0 1 0 0
SUM 84
BINARY ARITHMETIC
55+44=99
BINARY 1 0 1 1 0 0 carry 1 1 1 1 0 0
n r n r
2^n 32 16 8 4 2 1 augend 1 0 1 1 0 0
55 44
MULTIPLY 32 8 4 addend 1 1 0 1 1 1
27 1 22 0
SUM 44 sum 1 1 0 0 0 1 1
13 1 11 0
6 1 5 1 BINARY 1 1 0 1 1 1 BINARY 1 1 0 0 0 1 1
3 0 2 1 2^n 32 16 8 4 2 1 2^n 64 32 16 8 4 2 1
1 1 1 0 MULTIPLY 32 16 4 2 1 MULTIPLY 64 32 2 1
1 1 SUM 55 SUM 99
BINARY ARITHMETIC
35+11=46
BINARY 1 0 0 0 1 1 carry 0 0 0 0 1 1
n r n r
2^n 32 16 8 4 2 1 augend 1 0 0 0 1 1
35 11
MULTIPLY 32 2 1 addend 1 0 1 1
17 1 5 1
SUM 35 sum 1 0 1 1 1 0
8 1 2 1
4 0 1 0 BINARY 1 0 1 1 BINARY 1 0 1 1 1 0
2 0 1 2^n 32 16 8 4 2 1 2^n 64 32 16 8 4 2 1
1 0 MULTIPLY 8 2 1 MULTIPLY 32 8 4 2
1 SUM 11 SUM 46
Half Adder → Full Adder
• It can also be implemented with two half adders and one OR gate, as shown in Fig. 4.8.
4-bit Binary Adder
• 4-bit binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.
• It can be constructed with full adders connected in cascade, with the output carry from each full
adder connected to the input carry of the next full adder in the chain
𝑐𝑘+1 𝑐𝑘 … 𝑐3 𝑐2 𝑐1
𝑎𝑘 … 𝑎3 𝑎2 𝑎1 𝑎0
𝑏𝑘 … 𝑏3 𝑏2 𝑏1 𝑏0
+______________________
𝑐𝑘+1 𝑠𝑘 … 𝑠3 𝑠2 𝑠1 𝑠0
4-bit Binary Adder
• To demonstrate with a specific example, consider the two binary numbers A = 1011 and B = 0011.
Their sum S = 1110 is formed with the four-bit adder as follows:
• Co=0
carry 0 0 1 1 0
augend 1 0 1 1
addend 0 0 1 1
sum 1 1 1 0
Full Adder
• Full adder implementation
carry 0 0 1 1 0
augend 1 0 1 1
addend 0 0 1 1
sum 1 1 1 0
Carry Propagation
• C2 waits for C1, C3 waits for C2, C4 waits for C3, this causes a propagation delay which directly
defines performance of the adder.
• The most widely used technique employs the principle of carry lookahead logic.
• C3 does not have to wait for C2 and C1 to propagate;
Carry Propagation
Gi is called a carry generate.
Pi is called a carry propagate
• first number input A1,A2,A3,A4
• second number input B1,B2,B3,B4
• C0 is carry input
• S1,S2,S3,S4 are output
• C4 is resultant carry output
• NOTE: Input conditions at A1, B1, A2, B2, and C0 are used to
determine outputs Σ1and Σ2 and the value of the internal carry C2.
• The values at C2, A3, B3, A4, and B4 are then used to determine
outputs Σ3, Σ4, and C4
• Can be connected cascade to create higher bit adders (8,16,32)
• Fast Carry means carry lookahead. We can observe ‘carry lookahead’ part in
the datasheet
For example, let's say you have a shift register that has a chip enable pin, CE. If you see the CE pin anywhere
in the datasheet with a line over it like this, CE, then that pin is active-low. The CE pin would need to be
pulled to GND in order for the chip to become enabled. If, however, the CE pin doesn't have a line over it,
then it is active high, and it needs to be pulled HIGH in order to enable the pin.
Many ICs will have both active-low and active-high pins intermingled. Just be sure to double check for pin
names that have a line over them. The line is used to represent NOT (also known as bar). When something
is NOTTED, it changes to the opposite state. So if an active-high input is NOTTED, then it is now active-low.
Simple as that!
• Second way of 2’s complement: start from left to the first 1. copy/paste. invert other numbers to the
right
6 0 1 1 0
10 Co 1 0 1 0
1’s comp 1 0 0 1
10-6=4 -6 1 0 1 0
add 1 1
4 1 0 1 0 0
2’s comp 1 0 1 0
Binary Subtractor (2’s Complement)
• The subtraction of unsigned binary numbers can be done most conveniently by means of
complements
• subtraction A - B can be done by taking the 2’s complement of B and adding it to A
• The 2’s complement can be obtained by taking the 1’s complement and adding 1.
• Second way of 2’s complement: start from left to the first 1. copy/paste. invert other numbers to
the right
9 1 0 0 1
12 Co 1 1 0 0
1’s comp 0 1 1 0
12-9=3 -9 0 1 1 1
add 1 1
3 1 0 0 1 1
2’s comp 0 1 1 1
Binary Subtractor (2’s Complement)
• The subtraction of unsigned binary numbers can be done most conveniently by means of
complements
• subtraction A - B can be done by taking the 2’s complement of B and adding it to A
• The 2’s complement can be obtained by taking the 1’s complement and adding 1.
• Second way of 2’s complement: start from left to the first 1. copy/paste. invert other numbers to the
right
9 1 0 0 1
2 Co 0 0 1 0
1’s comp 0 1 1 0
2-9=-7 -9 0 1 1 1
add 1 1
-7 1 0 0 1
2’s comp 0 1 1 1
Overflow
• When two numbers with n digits each are added and the sum is a number occupying n + 1 digits, we
say that an overflow occurred.
• When two unsigned numbers are added, an overflow is detected from the end carry out of the most
significant position
9 1 0 0 1
12 Co 1 1 0 0
1’s comp 0 1 1 0
12-9=3 -9 0 1 1 1
add 1 1
3 1 0 0 1 1
2’s comp 0 1 1 1
Overflow Example
4-bit Binary Subtractor
• The circuit for subtracting A - B consists of an adder with inverters placed between each data input B
and the corresponding input of the full adder.
• The input carry Co must be equal to 1 when subtraction is performed. (add 1)
• The addition and subtraction operations can be combined into one circuit with one common binary
adder by including an exclusive-OR gate with each full adder
• When M = 0, the circuit is an adder, and when M = 1, the circuit becomes a subtractor
• notice that:
• M=0; B XOR 0=B
• M=1; B XOR 1=B’ (1’s complement, add 1=C0=M)
• A-B=A + (B XOR 1) +1
4-bit Binary Subtractor
• The input carry C0 must be equal to 1 when subtraction is performed.
• The addition and subtraction operations can be combined into one circuit with one common binary
adder by including an exclusive-OR gate with each full adder
• When M = 0, the circuit is an adder, and when M = 1, the circuit becomes a subtractor
• notice that:
• M=0; B XOR 0=B
• M=1; B XOR 1=B’ (1’s complement, add 1=C0=M)
• A-B=A + (B XOR 1) +1
4.7. Binary Multiplier
• Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers.
• The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit.
• Each such multiplication forms a partial product.
• Successive partial products are shifted one position to the left.
• The final product is obtained from the sum of the partial products.
• The multiplication of two bits such as A0 and B0 produces a 1 if both bits are 1; otherwise, it produces
a 0. This is identical to an AND operation.
X 1 1 0 1
Y 1 1 0
multiply 0 0 0 0
1 1 0 1
1 1 0 1
sum 1 0 0 1 1 1 0
4.7. Binary Multiplier A0 x B3B2B1B0
A1 x B3B2B1B0
• The multiplicand is multiplied by each bit of the
multiplier, starting from the least significant bit.
• Each such multiplication forms a partial product.
• Successive partial products are shifted one position to
the left.
• The final product is obtained from the sum of the partial
products.
A2 x B3B2B1B0
B3B2B1B0 1 1 0 1
A2A1A0 1 1 0
A0x 0 0 0 0
A1x 1 1 0 1
A2x 1 1 0 1
sum 1 0 0 1 1 1 0
ARITHMETIC LOGIC UNIT
ARITHMETIC LOGIC UNIT
• Provides 16 arithmetic operations: add, subtract, compare, double, plus
twelve other arithmetic operations
• Provides all 16 logic operations of two variables: exclusive-OR, compare,
AND, NAND, OR, NOR, plus ten other logic operations
• Full lookahead for high speed arithmetic operation on long words
ARITHMETIC LOGIC UNIT
• M=L for Arithmetic, Cn=1 for HIGH operands
• S0=1, S3=1 for A+B
• We will dig into ALU at the end of combinatorial logic
Arithmetic Logic Unit (ALU)
• ALU is the core of a microcontroller
• inputs: two numbers, carry input
• outputs: function outputs
• selection of operation, adder, subtrator, negate
ALU_EEE207
• Lets develop an 16-bit ALU_EEE207 with 4 functions: add, sub, increment, decrement
• SEL is 2-bits. the first bit is Carry inputs of add or sub
• SEL second bit is selection of add or sub functions 0=add, 1=sub
• if SEL=10 add=A+B+1 if SEL=11, sub=A-B-1, increment, decrement
• Cout is carry of add or sub functions
• MUX select results of add or sub according to the first bit of SEL 0=add, 1=sub
• x2=(A2’B2+A2B2’)’=(A2+B2’)(A2’+B2)=A2A2’+A2B2+B2’A2’+B2’B2=A2B2+A2’B2’
• YES
Two-bit Comparator using digital sw
• design using Digital sw, starting from truth map
Two-bit Comparator using digital sw
• design using Digital sw, starting from truth map
DECODER
• Decoder is a combinational circuit that converts
binary information from n input lines to a
maximum of 2^n unique output lines.
• As an example, consider the three-to-eight-line
decoder circuit of Fig. 4.18
DECODER/DEMULTIPLEXER
• A decoder with enable input can function as a
demultiplexer—a circuit that receives information
from a single line and directs it to one of 2^n
possible output lines.
• The selection of a specific output is controlled by the
bit combination of n selection lines.
• The decoder of Fig. 4.19 can function as a one-to-
four-line demultiplexer when E is taken as a data
input line and A and B are taken as the selection
inputs.
• For example, if the selection lines AB = 10, output D2
will FOLLOW the input value E, while all other
outputs are maintained at 1
ALU+COMPARATOR+DECODER/DEMUX
• decoder inside MCU takes the instruction bits,
decode it and route to control lines
DECODER APPLICATIONS
DECODER/DEMULTIPLEXER
4.10 Encoders
• encoder is a digital circuit that performs the inverse operation of a decoder.
• encoder has 2^n (or fewer) input lines and n output lines.
• An example of an encoder is the octal-to-binary (8 to 3) encoder whose truth table is given in Table 4.7.
• It has eight inputs (one for each of the octal digits) and three outputs that generate the corresponding binary
number.
• It is assumed that only one input has a value of 1 at any given time. WHAT WILL HAPPEN IF NOT ?
4.10 Encoders
• The encoder defined in Table 4.7 has the limitation that only one input can be active at any given time.
• If two inputs are active simultaneously, the output produces an undefined combination.
• For example, if D3 and D4 are 1 simultaneously, the output of the encoder will be 111 because all three
outputs are equal to 1. The output 111 does not represent either binary 3 or binary 4.
• To resolve this ambiguity, encoder circuits must establish an input priority to ensure that only one input is
encoded
• CD4532B encodes the highest priority inputs D7 to D0.
D7 has the highest priority, D0 lowest
• enable input (EI) and enable output (EO) signals allow
for cascading multiple stages without added external
circuitry
• (GS) group select all inputs are H
Schmitt Triggers
• It is important to remember (Vt+ max) = Vih and
(VT– min) = Vil. In the specs, multiple limits are
related to the Schmitt trigger inputs. All of the limits
are important for different reasons.
• On the input rising edge, the part will switch
between (Vt+ min) and (Vt+ max).
• On the falling edge, the part will switch between
(Vt– max) and (Vt– min).
• The part will not switch between (Vt– max) and
(Vt+ min). This is important for noise rejection.
5.2. Sequential Circuits
• Combinational circuits are ONE WAY, no loop
• It consists of a combinational circuit to which memory elements are connected to form a feedback path
• The memory elements are devices capable of storing binary information
• The block diagram demonstrates that the outputs in a sequential circuit are a function not only of the inputs
but also of the present state of the storage elements.
• The next state of the storage elements is also a function of external inputs and the present state.
• Thus, a sequential circuit is specified by a time sequence of inputs, outputs, and internal states.
• In contrast, the outputs of combinational logic depend on only the present values of the inputs
5.3. Storage Elements: Latches
• A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is delivered to
the circuit), until directed by an input signal to switch states.
• Storage elements that operate with signal levels (rather than signal transitions) are referred to as latches;
those controlled by a clock transition are flip-flops.
• Latches are said to be level-sensitive devices; flip-flops are edge-sensitive devices.
• The two types of storage elements are related because latches are the basic circuits from which all flip-flops
are constructed.
SR NAND Latch (74LS279A)
• The SR latch with two cross-coupled NAND gates
• S’R’=00 forbidden, non-stable state, Q may take random
• S’R’=11 keeps previous state of Q
• S’R’=10 makes Q=0
• S’R’=01 makes Q=1
• Mainly Three Functions: SET, RESET, KEEP
• Due to forbidden state SR latches are not so much used
D Latch (Transparent Latch)
• One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that
inputs S and R are never equal to 1, S’R’=00 at the same time. This is done in the D latch, shown in Fig. 5.6.
• The binary information present at the data input of the D latch is transferred to the Q output when the enable
input is asserted.
• The output follows changes in the data input as long as the enable input is asserted. This situation provides a
path from input D to the output, and for this reason, the circuit is often called a transparent latch
D Latch
• D latch is a 1-bit register
• First EN=1, then write D-data to register, either 1 or 0
• then EN=0, keeps the value in Q like write protection
Problems of Latches
• Clock signal used for Enable
• While clock is ON if D changes then Y output will be changed which is NOT something we want
• Because of this unreliable operation, the output of a latch cannot be applied directly or through combinational
logic to the input of the same or another latch when all the latches are triggered by a common clock source.
D Flip Flops
• Flip-flop circuits are constructed in such a way as to make them operate properly when they are part of a
sequential circuit that employs a common clock
• The construction of a D flip-flop with two D latches and an inverter is shown in Fig. 5.9.
• a change in the output of the flip-flop can be triggered only by and during the transition of the clock from 1 to
0 (Falling Edge)
• The slave latch is enabled, and its output Q is equal to the master output Y. The master latch is disabled
because Clk = 0.
• When the input (Clk) pulse changes to the logic-1 level, the data from the external D input are transferred to
the master. The slave, however, is disabled
• like two doors entrance, only one person=D can pass, if you are inside the first door is closed
D Flip Flops: Applications
• to the Q output on the low to high transition, Rising Edge of the CLOCK input (CP).
• The MR=‘Master Reset’ input, when low, sets all outputs to a low state.
JK Flip Flops
• With only a single input, the D flip-flop can set or reset the output,
• the JK flip-flop has two inputs and performs three functions : Set it to 1, reset it to 0, or complement its
output
• The J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are enabled, the output is
complemented.
• This can be verified by investigating the circuit applied to the D input:
• D = JQ′ + K′Q
T Flip Flops
• The T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs J and K
are tied together. This is shown in Fig. 5.13(a).
• When T = 0 (J = K = 0), a clock edge does not change the output. When T = 1 (J = K = 1), a clock edge
complements the output. The complementing flip-flop is useful for designing binary counters.
6.1. Registers
• A register is a group of flip-flops, each one of which shares a common clock and is capable of storing
one bit of information
• Registers with parallel load are a fundamental building block in digital systems
• If all the bits of the register are loaded simultaneously with a common clock pulse, we say that the
loading is done in parallel
• Performing logic with clock pulses inserts variable delays and may cause the system to go out of
synchronism
6.1. Registers
• A four-bit data-storage register with a load control
input that is directed through gates and into the D
inputs of the flip-flops is shown in Fig. 6.2.
• The additional gates implement a two-channel mux
whose output drives the input to the register with
either the data bus or the output of the register
• The load input to the register determines the
action to be taken with each clock pulse. When the
load input is 1, the data at the four external inputs
are transferred into the register with the next
positive edge of the clock. When the load input is
0, the outputs of the flip-flops are connected to
their respective inputs
• The feedback connection from output to input is
necessary because a D flip-flop does not have a “no
change” condition
• The MC14076B 4−Bit Register consists of four D−type flip−flops
operating synchronously from a common clock.
• OR gated output−disable inputs force the outputs into a
high−impedance state for use in bus organized systems.
• OR gated data−disable inputs cause the Q outputs to be fed back
to the D inputs of the flip−flops.
• Thus they are inhibited from changing state while the clocking
process remains undisturbed
6.2. Shift Registers
• A register capable of shifting the binary information held in each cell to its neighboring cell, in a selected
direction, is called a shift register
• The logical configuration of a shift register consists of a chain of flip-flops in cascade, with the output of one
flip-flop connected to the data input of the next flip-flop. All flip-flops receive common clock pulses, which
activate the shift of data from one stage to the next.
• Each clock pulse shifts the contents of the register one bit position to the right
Applications: Shift Registers
Applications: Shift Registers