8)

SEMICONDUCTOR MEMORIES
8.1 INTRODUCTION
As a matter of fact, a system which Chapter Outline
processes various
kinds digital data requires a facility to store the Introduction
unprocessed, partially processed and completely Memory organization and
processed data. A sub-system of such a digital operation
processing system which can store all the above Classification and characteristics
mentioned data is known as memory. In earlier of memories
times, the memory was of magnetic type. But now Classification based on principle.
a-days,semiconductor memories are available of of operation
various types and size. Classification based on physical
characteristics
8.1.1 Salient Features of Semiconductor Memory Classification based on mode of
The salient features of semiconductor memories access
may be listed as under : Classification based on
(i) Low cOst fabrication technology
(ii) Small size Internal organization of RAM
(ii) Better reliability (selection arrangement)
Random access memory (RAM)
(iv) High speed Static RAM (SRAM)
(v) It is quite easy to expand memory size. Dynamic RAM (DRAM) or dynamic
In present chapter, let us discuss the principle memory element
of operation and also limitations of various Memory decoding
semiconductor memory. Memory expansion (memory
banks)
8.2 MEMORY ORGANIZATION AND Read only memory (ROM)
OPERATION EEPROM (EZ PROM)
We already know that a flip-flop is NVRAM
single bit memory cell. Because of thisequivalent
fact, the
to a Flash memory
element of a basic
semiconductor memory is a flip-flop.
407
 array
binary stored
binary memory
are an in as 4-bit4096require word marks o
Design
AsNbits specified types
word Memory values memory. one2048, large 2007-08)(10
Logic chip an is having we three
DO store each
FFO 4-bit
locations. KNOW? YOU in thatthe store
1024,
if
and a Os) of bits)on binary is doneandor following
D store word devices chipcan
Electronics andsize depending data. to word 512,be words Exam.
to many one of memory location
memory
FF1 together0Word 1Word (1s The(number
levels
logic These 256,to
2Word M
Word stores
memory as each what
of of Sem. are
consists structure. to 128,
Digital grouped location referredfrom with each number
device. a arise There
Hyderabad,
FF2
Mernory wordvaries words of 64,
Al vary size and arequestion size.
Each
D Q are
locationshigher smaller
device.
FFs
0Location
1Location M
Location
(d)
binary
to store so
and we a length
used word M the chip
FF3 Four Therefore, in
since, in storing
if (JNTU,
locations
words Hence,perthewith memory
D Q (b) Fig. one To
8.1. required per
of
flip-tlops.
addition, 16 words
Now,memories
storing be bit bitsof chips lines.
FFO (a). N. ofconsists
capable
to 16 of of of Mx of 8. of Device a data
output
of
element FF1
together of
8.1 required
four In or word
number number ofnumber and number ofdiagram
figure (c). bit
capable is be memory4 that
memory
basic FF2
FF3
word require 8 storinga
8.1 chipshall 1, is Memory device:
grouped are bit, and are answer
in and a memory
memory values a
size cascading block
a
is of
&-bit
is shownflip-flopsare
location locationsthis word
(b) 4of there lines Nnum
FF shall
(FF)kind arean
flip-flop memory
FF4
FF5
8.1 number (d).
a
FFsstore thatused The of the
Flip-Flop
any
of
as we
figuretherefore,8.1 particular
the commonly common Diagramshowsinput
? by
inputs.
Control
(üi)
lines
Eight
to
eachonlyword,
eight eachfigureSize
Memory
8.2.1of
of
means words
formed input XN input are.
(a) number size Address
FF6 (c) 1 word,
Further,
or 4-bit
in astore
shown with
in a it the bit Block 8.2 M
there
0 shown if thethen The of an Data
Figure
FF7
i.e.,a 8-bit to memory, memory example, Also,16 be Types
(i) (ii) Also,
408 The then can
store to
bit,store as have 4
x word. puts
an on as it, 16 etc. size 3.2.2
to .
 twelth
havebinary
number dataoutput
address busand
lines
Ths
Vauvena
-
outputs
Data
409 lines)
(N-
the unidirectional.
data
deviceto
lines
in the or binary The data
readword. ofsetbi-directional
specied on
access inputs
words memoryaddress accessed.
be
will the same
1100 12 uponlocation.becanperare
address
device
with
Memory
brt inputs
Control to
MxNDts
ofmemory of is able input location
ofbits the
Depending location
N
and address
diagram4require is
location buses
locations be addresswritten.
orread lines. memory ) chips,
shall in output
Data as
known number as
data known
Block that. 12thdata address
we
we WiththeThe memory memory8.4. figure
in
M
8.2. Therefore.
means
then
decoder.
desired output
the isdatabus
inputs inputs
Data(N Fig. the are
(P-
lines) lines)
This12,o
usinglines selected
to of
andm0st
Address
M the equal
4. i.e..8.3. location
address
to select Input shown
address = 1111. figure 13
Location
12Location 15
Location signal
Control P thei.e., In aSuch
Theword-by
inputs
are input the as locations.
that P 1100, 1Location
0Location 2Location 14Location
ato direction.
data then outputs bus.
Ptheapplied available
lines, reading manner to in a in N, output.
as
address 0000 ofSelection sides
the new locations,
= depicted
A, is data
lines
lines
input Mpossible that
Data specify
for a M
fromA, is decoder output
onedataboth
8.3. noteinput
a
location.
datathese of Writing such
9P= A,
combinations datadata in
long. number 16 Ag as onlyas on
to
thein M= inputs chip Fig. address
to the the number wellarrows
of on used Ag A interesting of as
fact. known
Memories
Semiconductor
N-numberN-bit
wOrd
bus. lines flows
put memory
or of memory input
Data lines.Lines as
is DataInputs
Address
3. P are data onePaddress if
example.
address input
with
are 8.2. the data
lnputs
Data
2. stored lines tigure any difterent Address
practice,
P Output of also represe
The
each
with
Iword there required
stored matter
are as
knOWn These access
the quite the arethe
lines. data
There
be
the
reguirean on that
Here, of adjusted lines for
to
in
shown
slresdTo If location
As sixteen is Data Output used
ara also lines,
the form. It In
a
As
means
we bus. data 1S
ot 4. 1s itis
410
Digital Electronics and
5. Control Lines Logic
The control lines include the read/write
line and the chip select line (which acts as
Address bus P-lines Design
the enable input). The bi-directional bus is Memory
used as input data bus for some specific time chip
when input data is to be loaded into Bi-directional
memory data bus
(write operation). Also, it finds application N-lines
as output data bus for specific time when the
stored data is to be read (read
The bi-directional data bus operation).
and
saves N data lines.There is only one hence
R/W
(Read /Write)
-CS (chip selers,
line allotted tothe read and control Fig. 8.4. Memory chip with
It is denoted by R/W line in write operation. bi-directional data he
figure 8.4. If this line is at logic 1
place whereas for logic 0 on this line, level, then reading operation tal
acts as an output data bus and the write operation takes place. With R/W =1, the data hs
with RU W = 0, it acts as the
6. Input Chip input data bus.
Enable
Thechip select input is an DO YOU KNOW?
1. then only the chip active
is enabled and high input. When CS= The
take place. reading or writing will place (location) in the memory
7. Power device where any data value is
Supply Lines stored is
In addition to the
address, binary identified by another
control data lines, number referred to as an
required for the powerandsupply
are two more pins
8.3
thereaddress.
Each
and ground. a unique address. memory location has
CLASSIFICATION AND
CHARACTERISTICS OF
The memory devices may be
basis of classified on the basis of
MEMORIES
(i) classification various parameters. The
may be
Operating principle listed as under : parameters used ior
(iü) Physical characteristics
(iii) Mode of
access
(iv) Technology used for
8.4
fabrication process.
The CLASSIFICATION BASED ON
classification of memories based on OPERATING
the principle of PRINCIPLE
operation is shown in
Memories figure 8.3.
Sequential memories Read and
write memories
(RWM or RAM) Read only Content addressable
Shift
registers Charge coupled memories (ROM) memories (CAM)
devices (CCD)
Fig. 8.5. ROM
Memory classification based on PROM EPROM EAROM
8.4.1 Sequential principle of operation.
Memories (Sequential Access)
The examples of sequential
memories, the memory
Jocations memory are
magnetic
in a tape audiolvideo
are
writing from such memories is a organized
sequential process. sequence cassette. In the sequential
Hence, the(one after
time the
other). The reading
access a memory
required to
Semiconductor Mermories 411

locntion(for reading or writing) is different for different locations. The sequential memories may
further be classified into following two types :
1. Shift registers
2. Chargecoupled devices (CCD)
1. Shift Registers
The shift registers may be of two types, i.., static or dynamic. In the static memory, the memory
contents do not change with time as long as power is ON. In the dynamic memory, information is
stored in MOS capacitors. "The memory contents can change with time. Then. it is essential torefresh
such memories at regular intervals.
Salient Features of Dynamic Memories
Few salient features of dynamic memories may be described as under :
(i) They are simpler than the static memories
(i1) They are less expensive
(iüi) Require less power for operation
(iv) They have high packaging densities.
Due to all these salient features, the dynamic memories are widely used in digital systems. The
only drawback of dynamic memories is the additional circuitry for refreshing.
2. ChargeCoupled Devices (CCD)
The CCD are manufactured using MOS technology. The salient features of CCD are high density
and low cost.

8.4.2 Random Access Memory (RWM or RAM)

locations in
Randomn access memory is also known as read write memory (RWM). The memory
accessing any
this type of memory are organized in such a manner that the access time required for memories.
location remains the same. Actually, this is an advantage of using RAM over the sequential
dynamic RAM.
RAMs also may be further classified into two types namely the static RAM and
RAMs may be fabricated using either bipolar technology or unipolar technology.
8.4.3 Read Only Memories (ROM)
1. Basic Concepts
stored on them.
These memories are designed only for reading the information which is already
prerecorder cassettes.
The user cannot write any new information on them. These are similar to the
complicated
A manufacturer or someone else can write ROMs, but the writing process is much more
up tables.
as compared to that of a RAM. Also, ROM is used to store fixed informations such as look
instructions, fixed data etc. It is alsopossible to organize ROMs in such a manner that reading tim
required for any location remains the same.
2. Classification
The ROMs are further classified into three categories as under :
(i) Read-Only memory.
(i) Programmable Read Only Memory (PROM).
(i) Erasable and Programmable ROM (EPROM).
(i) Read-Only Memory
These memories in true sense are the read only memories, because they are programmed at the
time of manufacturing, The programming is ormulated as per the requirements of the user and it 1s

"The intelligence is proved not by easeof learning but by understanding what we learn.
-Joseph Whitney
 8.5.2 of
PROM simultaneously. (i) is
However,
aEAROM,
is (i) under
memories :
example,
information the which 8.5
8.5.1Figure operations (EAROM). ROM
all to stored. 8.4.4 Commonly (ii) ROM. once programmed. (1)cOstly the 412
The
UItraviolet the These AU be Location In (ii) non-erasable
(i) An
CLASSIFICATION It last
this Erasable
the Content that
The (b) (a) Erasable ASProgrammableA
is
EPROM locations
Locationsentered.
Location-by-location All erasable .6 is The after user and
EAROM, can ROM a erasable Erasing
Erasing the
a are inthe type, stored shows process
quartz RAM locations can special
performed makes usedname PROMs its can hence
contents by
the further is
fabrication.
Erasable As t
Locationhe a be or Accessible
get non-erasable information
memory memory the techniques
usingusing and program WNe in
.the an
which Simultaneously and RAM desired Non-erasable type programmable use suggests, are
lid memories
are a simultaneously stored.
example, be classification by of Programmable are manuacturing
cannot of
suitable
orcan erased CAM, of of electricity. Read
the and categorised
windowW
ogrammable BASED the
RAM.
the ultraviolet manufactured these
Erasable
memory cannot The is
figure
simultaneously. be erasing erasable conventionalMemories electrical r After
will Only change
in location CAM can that fothese
erased when memory.
information erasing ROMs only
on which, Memories
be
kind It programming,
locations be based can ROM Memories programmed
the Erasable
we operation
are erasable. in erased ON radiation ROMs for datathe
Memories tw o erased. voltage
using exp0se must the memories. The
ROM using a bulk ROMs.
ckage. contents
of PHYSICAL perform(CAM) using may without
ROM classes memory upon memories.
can
the examples be can erasable stored and
is As fo r be PROM
use Such
Memories
an erased the ultraviolet (PROM)
ultra performed be new association described be contents any the (number
EPROM as an in in erasing
We of erased physical erased ROMs
all CHARACTERISTICS data
programmer. A
canviolet first of non-erasable Erasableor
tothe location one is stored
erase Fig. erasing asand of are
rays th e automaticallybefore characteristics. operation known under chips after
locations by known
this 8.6. programmed
is
ultraviolet by one into fabrication.
entering Classification as is become in
ROMshown location and : them
characteristics. electrically known PROM millions). as Digital
in
of then Memories custom
when addition
by in radiation,. information. the permanently (i.e. Electronics
memory erasable the as again can
sin based These
new new EPROM, they be programmed
new
on
to alterable programmed
8.7. memory: intornta the and are ROMs and
information physical
it In non-volatileVolatle or read/write again.
The blank).fixed Logic
to contents
erased Also are
the this 0r
ROM in quite mask Design
h the only
 8.7 RAM, Access
8.6.2 Sequential
required
memory Random Access
8.6.1 or
Mode 8.information Memory(i) 8.5.3
changeMemory(ii) called theVolatile
6 types Non-Volatile the
in UV
Semiconductor
exposure period
Four Using using write
Darwbacks ultraviolet
(UMemori
V) es
rays
In The Random
access(ii) If electrical If (ii) (i)
technology
BipolarThe
(ii) (i) There Sequential
accessi)
CLASSIFICATION of are the as the Volatile erased
steps MOSeitherCLASSIFICATION ROM this access unless TheSelective
putlocations
erased. get
location to
seguential operation. examplesinformation volatile information will
examples MOS are EPROM in
to
technology and type, access even power EPROM erase
achievement bipolar means altered or the
technologyfollowing memory. Non-Volatile eraser erasing shouldlight
of
CAM. for we
various after all
There of 1s has
or
bipolar read can memories the non-volatile will e th
deliberately once switchedstored
switching through10
be
to
only MOS two for to
plan : (unipolar access
or locations manner
are BASED RAM be not
is store cells
BASED stored
using
technologies basic write have following in erasing.removed
prp0sefully, technology. 1s Memoriesa possible a at 15
any in off are in OFF,
memory
a time
1. the
the requires a ON
technology).fabrication ON shall
sequential which memory. thememory volatile minutes.
memory two MODE known then from and quartz
MOSFETs. The are FABRICATION be power to
a chip achieve. all
prepare TTL, same different. possible
memory as memory. the the
chip Note
locationsthewindow.
dynamic technologies location access is
supply.
OFnon-volatile memory lost socket
prayerfully, ECL amount does that
modes ACCESS
location All
to when and
RAM, and without Infact, not the the The
various is
used
TECHNOLOGY of of
RAM, time. access is memory. the datamemory, Window
proceed EPROM accessed read data. nals is same All
as going memory placed
ROM, under: Examples memory
: only Such
are datavalue general
positively, and sequentially. while inputs,
manipulated onthe KNOW? YOU DO Fig.
EPROMs locations. memories to
address 8.7.
EAROM memories bethe way.device
Willian
ArthurWard PROCESS of performing andstored UV
random address
pursue To EPROM
can Hence, the operate
to
Accessing (ROMs) can to is be write
are be control
persis access store appliedinput,
fabricated
fabricated the the hold accessed data
in
tenuy* time read of 413
are any all the
the sig tothe inthe
 Design 4-address
are wTe
Control
memory memory "? g0 it ofY
buffers
output location with
There
Write
(W) Read
(R) Dg a lo Here,cleared Weaver
G.Henry
Logic read, G1
adjust will showsterms
of used. or used. desired gate This lines,
and consists
ARRANGEMENT cell memory is
are we enable
Electronics decoder memory being disabled. output important
circuit the Then, the
It andare at will
8.8.line bit
1 input this
lines (1001) location.hence
are
the memory
Digital This few
figure
16 lines) on
(Data
output
lines) data
to buffers
0, available define
to output
inputs data 0.
input memory is selected
in 4
(SELECTION
a Location
0 Location
15 R=
G
have (Data Input
buffers the desired output gate us
shown andThe W=1and
between notthe Let
we input
gates. desired of gold.
Do
is conyersion, andoutputis cycle.
word. 10 the data at
chip it.
Fig.
8.8. separate
connected writing the enabled present replace of
RAM Memory
chip 1,
4-bitD
NOT the terms
memory 1Location Location
14 = The Cvcle write
select
CS Therefore,
OF two
for are 0110.originally in
linea D 2 2 arethatand make inputsWrite the
storing
D3 place t0 act
ORGANIZATION
4 Lod buffers for
x 16 3 D3 noted
buffers as location cannot
16 to
3 gates so We datathe waveforms
4 of buffers -os
Output taking=0110 state). is
a Forcapable be input which
inputs. the of silver,
of output
may AND memory Characteristics
addresses,
organization decoder under: the impedance
events data at waveforms.
to line
16 it two A data present the sof
one and
4 Here, 8.8.1 OperationA, Hence,
Write terms
INTERNAL each inputconsists of as A, the the the
16 CS. sequence into
output. is A, into that
tristate
(high data these in
internal
have
locations Ag Actually, select (0110)at Go.
adjust 1,
Waveforms thinks
who
One
Az 1001 1001 noted Timing 8.9
circuit gate may the
to Address
inputs data chip The word and
Figure
to
414 8.8 Thelines We = disable
location
D, reference
be
16 andlogic
and
D, the Grst8.8.2
 Forbe anddoesselected
415 alongthat datafrom
control writing
per
CPUs must
location.disabled
and
usedCPU thedata input of
X KNOW?
YOU
DO
andprovides
oftenmicroprocessor
addresses
and
the the
from
Reading ends. ends.
memory are
write
state)
data
impedance
the procedure:
are uses ends. buffers
either chip.
pulse the makes
devices or done
the
always
are
memory. pulse pulse selected
while thelines.
andstored input
1or0 reguiredgenerates
addressMemory
write
spective. write buffer
(high following
operation. enables
address
signals write a 1
a the
DH with be the after before of logic tristate
Valid
data after contents output
Therefore,
theThis
diagram. to
tow valid to the
address
Change
of value valid valid adjusted readOperationto
ty the enabled follow chip.
Valid
address timing value be the location
Typical must be be GË. into about =0.
wo valid time reading
be to the (W)
typical must must gate The haveto
cycle address must go all Read (CS)memory write
minimum buffers
Write thememory. data data for disables is
data. we
Infact, inputs This signaland
for chip,
8.9 which which which which essential input
Tristate thetheoperations. input followed the
lines. 1
Fig. pulse.
write (R)and memory of
Definitions
for in select =
is for for for
is readGo Thetheoutput address
(R)
0,or1 timedatatime (tp)time time operation with
(twptime enabled, be chip Read
(tyc) writingcycle (t) (tp) andgate the
of write time time
of of of the to apply
connection apply
apply
Memories
Semiconductor amount time of amountamount time OperationCS enables on steps
amount
8.8.3
Read from
time
Importance Write length
Minimum readthe
1 Write 0
(WR) input
Data for successive releaseup are available datawe we we
Address select
Chip pulse up operation, Procedure
(CS) cycle present
sec. hold
Minimum Minimum Minimum1.Definition This
Basically, buffers
the First,
Then,
Now,
Minimum set read
Write Data 0. allow
Write n200between
Write 120
nsec. Data logic locationTo i) (ii) (ii)
output
Few be
musttwc= (ii) (iii) (iv) (v)
read
at not Z.
2. (i)
 416
Digital Electronics and
8.8.4 Timing Characteristics of Read Cycle
1. Waveforms
Figure 8.10 illustrates the waveforms for the read operation.
RC

Address Valid address

Change of address

Chip select
(Cs) 0.
or.1

Read (RD)
0 0or1

-tRD LtoTD
too
-cx
Data output Tristate
Valid
data

Let us define some Fig. 8.10. Read cycle

timing
cycle timing diagrams important terms related with the diagram.
chip. You are aware shown in figre 8.10. Following read operation, with respect to th
functioning, that
i.e., it requires,basic element in any IC is above steps, one can read the data frc
2. Timing specifications hold up, setup, transistor. transistor has its oWn
Hence, for above read
propagation
delay time etc.
Read Operation : operation IC manufacturers provide
(i) Read cycle
It is the time (tRe) following timing specificatio
memory. Infact,minimum amount of valid time for
between the successivetypical value of tRO =200n sec.which address
In other mustitbe resent for reading data
(ii) Access time (t,) read operations. words. is the minimum time
It is reqt
at an maximum
output.
time gap between
valid address
Usually, tA
outputs must be ready beforeS tRC. Infact, present on address line and valid data avail
the typical value
is ready for of ta = 20 n sec. This
(iii) Read to output memory
valid time (t) next read means that thhe
This is the
data bus. Infact, maximum time-delay operation.
(iv) Read to output typical value of tRn =between the
70 n sec. beginning of read
active pulse and availability of v
This is the maximum time (t¡R
to active state (from
Hi-z time-delay betweenitsbeginning of read
(v) Chip select to output valid condition). Infact,
typical value pulse amd the Output buffers comi
time delay time (teco
=20 n
It is the maximum sec.
data at the data output. Infact, itsbetween beginning of chip
typical value of too = 70 select
n pulse and the: availability of val
sec.
niconductor Memories 417

Chip select to output active time (t)

It is the minimum time delay time between beginning of chip select pulse and output buffer
aing toactive state. Infact, typical value of tox = 20 n sec.
i) Output tristate from read (tom)
It is the maximum time delay between end of read pulse and output buffers going to Hi-z state.
fact, typical value of torp =60n sec.
ii) Data hold time (toHA)
It is the minimum time for which valid data is available at the data outputs after the address
d. Infact, typical value of toHA =50 n sec.
9 RANDOM ACCESS MEMORY (RAM)
Definition DO YOU KNOW?
e know that RAM is a memory that can be read as well as
rite. RAM is a volatile memory so it loses the stored data Most read-only memorios (ROMs)
have data entered one time, and
hen power is turned off from then on their contents do not
Classification of RAM change. This storage process is
There are two types of RAM as under: called programming. They do not
i) Static RAM lose their data when power is re
moved from the device.
(ii) Dynamic RAM.
(MDU, Rohtak, Sem. Exam. 2006-07) (10 marks)
3.10 STATIC RAM (SRAM)
tis possible to implement the staticRAM using the bipolar as well as MOS technology. It is possible
which
o store data as long as power is applied to the chip. Static RAM cells are basically flip-flops
can stay in agiven state (i.e., store a bit) as long as power to the circuit is not interrupted.
3.5 V
8.10.1 TTL RAM Cell
1. Circuit Diagram
Ro
Figure 8.11 illustrates the circuit
diagram of a simplified TTL RAM cell.
Here, multiple emitter transistors are
Used to form a flip-flop with the set and Set
-Reset
reset facility and also the facility for select E,
Ey F..
line connections. Actually, this cell is
capable of storing only 1 bit. Select line X
Select line Y
2. Working Operation Fig. 7.11. Bipolar RAM cell.
Here, Q and Qo are cross coupled,
1.e., collector of one is applied to the base of other. Because of such connection, only one transistor is
ON at any given instant. The Xand Yare the select lines that are useful in connecting the cell in a
matrix. A1is said to be stored in the cell if Q2 is OFF and Q, is ON. Whereas a 0is said to be stored
f Q, is ON and Q, is OFF. Notethat the transistors act as switches. If the set input is pulsed high,
then Q, is turned OFF. This raises the collector voltage of Q, to Vcc. Therefore, base voltage of 2
goes high and it goes into saturation. Thus, a 0 is stored. In a similar manner. when reset input l5
pulsed high, Q, is turned OFF, itscollector voltage goes to V and a 1l is stored in
number of such cells are connected in the matrix formn (rows and the cell. A
chip. columns) to form
 MOSFET
8 its When as bothlines the of In 8.11 Operation This Read 3. lines Defnition 8.10.2
1. 418
11.1
charge. charge
dynamic
MOSFETT;
Y=1,ON. cell
andinverters
a For
(ii) singleThe(i) closedthesedynamic
the are DYNAMIC will Usedarfoer igure
consistscapacitor. Salient the MOS
Hence, used Data ino
turns
In
control lines on connect read MOSFETs T,
ths switch RAM the
RAM, operation, and 8.12 Static
itFeatures as
of OFF column Dataline address having
Ycells shows
requires manner, and
are capacitor. the the Write, W samethe otherTo addressing T; T a
more bit and cell. RAM turned
Thiares RAM
and high, data data T,
dynmie sense we
T,
charges and The (DRAM) and and
memory very of the the T six Cell
Figure is line have
Dynamic logie a both
capacitor rowsense stored Tg the T,
SMall MOSFET are (Static
coll RAM thesignals. to to are ON. MOSFET
lbit l are data
OR apply cell.
capacitor.
and 8.13 in Fig. turned working
as
nren isRAM Memory
cell
pared retains
is low,
control
the
DYNAMIC output. T, T; Memory
fornnod storod. worksWhen shows a 8.12. connects When static
aS fornm logic
the resistances.as
Compared MOS
Thus, 1
X=
using Control This
to to static Select
line Y
RAM Element)
signal
(JNTU, the to
Y=1(High),
static MEMORY the
to only (Row) the RAM makes cell.
(Column)
signal
Control read memory
static Hyderabad, complement T
RAM two cell This
(R) D read, They
perRAM,
omponents. and Fig. ELEMENT input. the circuit
rea.
unitThis 8.13. or act
MOSFET
switch Sen. cell Digital
of
This as
Dynamic the Data
line addresssameY
write the consists
is
Exam, Read, R having
thecellsother To
addresssame
X data loads
menns having
thecellsother-To Electronics
One storedturns operation selected.
RAM 2006-07)(10 and for
on Data
out o two
of
that, MOSFET data data TË
MOSFETlt and
the is possible. When andcroSS
lines. Logic
Tea T3
DRAM CapacokStyorge marks) and" X COu
2 Whe=1,t6; Des
 threshold
voltage.
Operation
readclosed Read 2. ON. C,and MOSFET' capacitors
multivibrator
and s memory
one isvOu 1. charge. cell,after 8.11.2
8.11.3 Semiconductor
Memories
peration
(act Write 3. bit Definition will
igure we The
every
operation readFor C,has T,WeTËo
asFor switches). will zero iscan of see Dynamic This have Drawback charge
osed OFF.controlled isinformation C better few
write voltage
be access T, that 8.14 is to
operation,
R=1, and and but the use hold
s).
ration, will having Also, shows and milliseconds.
Data in The than here MOS
take capacitors
on TgCgthe Circuit main an by of
the To capacitor byarestore
Datlinae I data a it. other (0that wethe RAMadditional Dynamic the
W Xo sameotherplace. zero the drawback
If Further, controlled ordynamic need capacitor
cells line the of Diagram Therefore,
ata =1, W Y voltage
read facilities 1). Cell
Fig. T, address X=Y= C, C, status the four RAM
Memorycell having is isand input The circuitry
in
Y=1. 8.14. connected storage static of
MOSFETs MOS
1,= D acrOss
charged C, by basic
of a requires
hen Four 1. DRAM. alongwith
Therefore, of
if (R). Ythe of RAM. RAM
inputs. reading, for
efore, element
or transistors Refresh through it a toand cell. refreshing to
and 0 only a The cell.
instead be
VpD will
C,
voltage MOSFET The
refreshed the
MOSFETs take if writingdynamic of If
the MOS Tg will X= cell the DRAM
C Ta which ofyoç
D
and place compare
six. the
is dynamic be Y=1. madedynamic
and
dETs, the To T, MOS
charged
6 retrieved.
ToTs, is device
sameother if is Hence, applied. is
RAM generic canRandom
to Storage
higher
T, controlled addressing up
cell. I|Data
line 4cells the Te, it have
T Y is of MOS RAM
address T;, to
forced MOSFETs the with
Ta having data a than of cell termaccessKNOW? YOUDO
addresssame
X
having
thecellsotherTo Tg packaging Data data
T7; 10Dataout voltage RAM the
to takes
1 by are of only given
To, T output and threshold figure 8.can14 static
To OFF the also cell easily
are memory
T7and as
greater place write T to
15 T, line.
conduct state T2,
included. is
density RAM long
retained
the devices
stored
wil
voltage if
input T; as (RAM)
Thus, than and cell,
T, andbistable of
conduct (act is power in
T, The store this then and that is 419
the the and ON (W) T6 a
as is a
 Each SRAMl Cell IS d -P

1l. Circuit configuration of one MOSFET and a

flop. capacitor.
Less (only two)
2. Number of components per cell More More than SRAM
Less than DRAM
3. Memory cells/unit area
Not required Required
4. Refreshing
More Less
5. Cost More. Hence, these are
Access time Less. So these are faster
6. memories. slower memories.

BANKS)
8.12 MEMORY EXPANSION (i.e., MEMORY
(Anna University, Chennai, Sem. Exam, 2006-07)(10 marks)
chip isnot sufficient. Because of
In several applications, the capacity of the single available memory
This is known as expansion of memory.
this, we have to increase it by using more than one chips.
The memory expansion can be of following two types : DO YOU KNOW?
(i) Expanding the word size (increase in N).
(ii) Expanding the word capacity (increase in M). Static RAM (SRAM) uses storage
elements that are basically latch cir
8.12.1 Expanding the Word Size cuits. Once the data are stored, they
Here, we want a word size n which is greater than the will remain unchanged as long as
word size N of the available memory chip. As an example,power is applied to the chip.
conversion of 16 X 4 memory into a 16 x 8 memory requires
expansion of word size from 4 to 8. It is interesting to know that number of words M= 16 remans
constant. The next example explains the word size expansion process.
EXAMPLE 8.1. A 16 x 4 size memory is available. Expand its word size so as toobtain a 16 x 8 memory.
(RTU, Kota, Sem. Exam, 2007-08)(10 Marks)
Solution: (i) First, we decide number of memory chips.
Ifthe required word size is denoted by n and the available word size is denoted by N. then the number 01
ICs required is an integer given by,
Number of ICs, X 2 n/N.
Here n =8 and N=4, hence X = 2. We have to use 2 ICs, each with a capacity of 16 × 4.
Semiconductor Memories 421

connections
(ii) Then, we make
Since the number of locations does not change (16).
the number of
address lines will not change. It will be Ag
equalto44andthey will be common to both the memory Address Chip - 2
lines
Asthe word size issto be expanded, we will use the Ao D4
ICs.
ata lines of IC-2 as the MSB lines (D, De. D. D.) CS RD WR
8- bit data
whereas the datalines of IC-1 will be used as LSB lines (input or output)
D. D». D,. Do). Connect the read (RD) input of both Control
16 x 4

ICs together. It will now act as read (RD) input of the lines
overall memory. Same thing is true for the write (WR)
(CS) input. The CS RD WR
input, as well as the chip select8.15.
connections are as shown in figure Da
Chip - 1
8.12.2 Expanding The Word Capacity Do
Expanding word capacity means increasing
the value of M, keeping the word size (N)
unchanged. For example, if 16 x 4 chips are 16 x 4
available and we want to have a 32 x 4 memory. Fig. 8.15. A 16 x 8 memory using two
16 x4 memory chips
then we have to perform the word capacity
expansion. The following example illustrates the
word capacity expansion.
EXAMPLE 8.2. Obtain a 32 x 4 mnemory using 16 x 4 memnory chips.
Solution: i) Number of Memory Chips number of chips
using memory chips with M words each, the
To obtain amemory of capacity m words
required is given by
X2 mM
where X is an integer.
In this example, m=32 and M= 16 required.
Therefore, X = 2, i.e., 2 chips of capacity 16 x 4 are
(ii) Connections
in the following manner:
Thetwo 16 × 4 chips are connected means that out of the 5
lines of two chips individually. This
address
The address lines are connected to the LSB lines Ag A, A, An will be same for each chip and the MSB line
lines), the 4
address lines (we need 5 address
chip-2.
A, should be used to select chip-1 or
with A, =0, chip-1 should be selected
with A, =1, chip-2 should be selected. input/output lines of both the chips should be connected to each
data
As the word size is same (4 bit), the
as the D, line
other.
is connected to Do of chip-2 and the common D, line now works
"This means that D, of chip-1 made for D,, D, and D, lines.
the overall memory. Ina similar manner, the connections are also together.
of
connect the read input of each chip together and write inputs
"Then, we
diagram.
Figure 8. 16 shows the connection
Data D'3
input p
RD
RD
Chip-2
Chip-1
WR
WR CS-2
CS-1
Read (RD)
Write (WR)
A
Address A
lines

Fig. 8.16. A 32 x 4 size memory obtained using two 16 x 4 memory chips

 Desig 11l show Theareare
a manner,
write To
usest
charging
chips memory.
to Also chips. chips
Logic 0000 (DRAM) RD D,
for 8
allthe DO
YOU
KNOW?by 0Chip
?
A= menmory
and accessed = of all combined data
lines similar
2048/256 discharging
orthem.
ElectronicsAgA of CS
Do lines store
RAM
8
that In the
beAg
x chips
canFor 2048 use (RD) to RD
of
memory.
Digitallocations Dynamic
capacitors chips
selected.
is
chip a to means input memory
chip-2.
obtainrequireread WRD7
(WR)
This combined Chip
6 memory
The
16 of 8
to we other.
on. write LSB x
first locations
xrequired
chip.
access three
the the of
CS 256
eight
second chips, so diagram
the the the of of eight
the each
memory of
and to MSB outputs
inputs for
16 form Hence, using
Therefore,
and
8 to ... input and locations
the are x The connection RD} WR
256connected A
together
to 8 select chips.
D7
on chips
disabled read to A10.chips.
the Chip
7 memory
each together
performed using A,
selected. to andchip memory
memory the lines memory
is with are connected A,the one-to-the the CS Do size
memory as connected decoder
chip address
chips works lines all shows 8 of
is firstbe 8 associated to 8 x addresses
chip can theare address 3:8 × 2048
256 8 line 8 common 8.17256
1, require by
first= operation
×
lines are
all connected
together, a one eight 8.17.
A, many 2048 thischips 11 to Figure
of
addresses applied 8to linedecoder
theWith lines
D, and we need are applied Fig. the
obtain using 3
WR EXAMPLE
0, 1111,
How the locations,
A, chips. describes
data together we are Memory
Addresses
= all to then memory
A, or 8.3.memory To locations,
Ao Aj0 memory
to RD bi-directional
of
When A10 Ag Ag
0000
the
: lines
Solutionconnected 256 lines to are A7 D, RD WR
8.2
8 A Ao D
Ag decoder Address Table
422 = now, access
(WR) 2048 x Data
the eight
lines eight
2048 bus bus
A
 Semiconductor Memories 423

Table 8.2. Memory addresses for various chips

S.No. Memory chip number Address (Hex)
Chip - 0 000 OFF (256 locations)
Chip 1 100 1FF (Next 256 locations)
3 Chip 2 200 - 2FF (Next 256 locations)
4 Chip 3 300 3FF (Next 256 locations)
5. Chip 4 400 4FF(Next 256 locations)
6. Chip 5 500 - 5FF (Next 256 locations)
7. Chip 6 600- 6FF (Next 256 locations)
8. Chip 7 700 7FF (Next 256 locations)

8.13 READONLY MEMORY (ROM) (BPUT, Orissa, Sem. Exam., 2006-07)

We know that the information stored in aROMis permanent naure. It can be only read and cannot
be written. Following advantages make the ROM an important part of many digital systemsDen
: vob o
(i) Low cost
(i1) High speed
(ii) Flexibility in system design
(iv) ROM is a non-volatilememory.
8.13.1 Applications of Read Only Memory (ROM)
Few important applications of ROM may be listed as under :
(i) For implementation of combinational circuits.
(ii) For implementation of sequential circuits.
(iii) In character generation.
(iv) For look up tables.
(v) For storage purpose of microprocessor program.
(vi) It is suitabie for the LSI manufacturing process.
ROM applications can be described briefly as under :
Implementation of Combinational Circuits
Let us take an example of code converter say binary to XS-3code converter is to be implemented
Using a ROM. Table 8.3 shows the truth table relating binary and Excess-3 Code.
Table 8.3.

Binary XS -3
0000 0011
0001 0100
0010 0101
0011 0110
0100 0111
0 101 1000
0110 100 1
0111 10 10

Nothing is useless to the man of sense, he turns everything to -La Fountaine

account.
 424 Digital Electronics and Logic
Now, we store tlhe XS-3 numbers serially from location 0000to 0111 into the ROM. We
Design
binary number which is to be converted into XS-3, at the address input.As an example, if wegiveanthe
Ag Ay A, A=0101,then, we set the ROM into read mode. Therefore, on the data output ines
obtain the data of location 0101which would be 1000. Thus, we got the Excess-3equivalent of 0101
8.13.2 ROM Manufacturing
Various technologies used for manufacturing of ROM may.be listed as under :
(i) Bipolar Technology, and
(ii) MOS Technologý.
Bipolar ROMs are faster and they have higher driving capability whereas MOS ROMs
Jess area and consume less power. The improved MOS ROMs have improved speeds (typical require
equivalent to those of bipolar devices).
ROM

Bipolar ROM MOS ROMs

Mask Programmable ROM PROM Mask PROM EPROM

Programmable ROM
EEPROM
Fig. 8.18. Classification of ROM
8.13.3 ROM Programming
The process of entering information into a ROM is known as ROM
may be classífied basedon the programming process as described under: programming. The ROMs
) Mask programmable ROMs.
(i) Programmable RÒM (PROM).
(iii) Erasable programmable ROMs (EPROMs).
The important information regarding the ROMs is as given below :
ROM

Mask programmable ROM Programmable ROM Erasable programmable ROM

(i) In this, data pattern must
be programmed as a part
i) This device is electrically i) In this, memory data can be
of manufacturing prOcess. programmable. Here user written any number ot times.
can program the chip.
Normally PROM are 0TP
(one time programmable).
(ii) Not reprogrammed. (ü) Not reprogrammable. (ii) Chip can be erased by
exposing it to UV ray_ called
EPROM OR it can be
electrically erased referred as
EEPXOM (E' PROM).
(iii) Normally shifted for high (iii) Normally used for (iii) This is used when one wants
volume usage due to law production purp0se. to develop dhgital computer
cost. system.

Self-confidence is the first requisite to great undertakings. Samuel Johnson

 Semiconductor Memories 425

8.13.4 ROM Organization

[. Column
Row

,Doo Do1 Do2 Do3

A,o
1of 4 Di0 D12 D13
Decoder
DL
Ajo 2

D20 De1 Dz2 D23

4 bit
address Row drivers Da0 Da1 Dg2 Dgs
Diode matrix

Column
enable
Azo Column
1 of 4 sense
Decoder amplifiers
DA
Ago
Chip select,
(CS) O
Data output
Fig. 8.19. Illustration of a 16-bit ROM array
Basically, a ROM is an array of selectively unidirectional contacts. The contacts can be open or
closed selectively toprogram the required information into a ROM. Figure 8.19 shows a 16-bit ROM
array. It makes use of two 2-4 address, 16 locations and 1-data output.Therefore, this is a 16 x 1
ROM. The method of addressing is known as two dimensional, X- Y or coincident selection,
addressing. A unidirectional switch is included at the junction of every row and column. The lower
two address bits (A, A) are decoded by the decoder D. The outputs of this decoder are used to select
one out of the four rows. The high two address bits (Ag Ag) are decoded by the decoder Dy. The four
outputs of this decoder are used to select one out of the four column sense amplifiers.
Diode Matrix
Diode matrix is the heart of the ROM array shown in figure 8.20. It is Row 0
formed by connecting a diode and a switch between each row and column. Dos
As an example, let us consider figure 8.20 which illustrates diode Do:
Connected between row 0 and column 3.
The chip select (CS) input is utilized to enable the output. A ROM is Column 3
Programmed by selectively opening and closing the switches connected in
Series with the diodes. This has been explained below.
Fig. 8.20.
8.13.5 ROM Programming
lf switch of Doo is in closed position and the address input is 1100, then row Ois activated
through D,, and column 3through Dy. The sense amplifier of column 3is enabled. This yields output
 426 Digital Electronics
and Logic
=Logic 1if Cs =1. Thus, alogic 1is stored at the address 1100. On the
series witlh DÍ: is open,then a logic Ois stored at the address 1100.
other hand, if
the Desig
8.13.6 Use of Other Devices in Place of Diodes swithi
It is possibletoimplement ROMs by using the bipolar junction transistors or
of diodes. Figure 8.21(a) shows the
manner in which a BJT must be Vcc
Row A MOSFETs inr plars
connected and figure 8.21(b) shows how RowA
to use a MOSFET to implement a ROM.
The ROM implemented using transistors QAB
is known as a bipolar memory and that
implemented using MOSFETs is called QAB
as MOS memory. The fuse shown in
figure 8.21(a) is for programming. When
a l is to be stored, this fuse is kept
intact
and it is blown off when a 0 is to be stored. Column B
Column B
The base emitter junction of (a) Using BJT (b) Using MOSFET
transistor QAR 0s forward biased, hence, Fig. 8.21. Unidirectional switches
it works as a diode. In figure
8.21(b), a
source resistance RpsoN is very small andMOSFET
the
is used as a switch. When it is
ON, the drain ta
B to ground. MOSFET works as a closed switch connecting column
8.13.7 Few Important
Few important Characteristics of Memory
(i)
characteristics of memory may be described as under :
Memory capacity and its organization
(ü) Physical dimensions
(iii) Type of packaging
(iv) Power consumption
(v) Timing characteristics
(vi) Reliability
(vii) Cost.
8.13.8 Performance Comparison of RAM and ROM
Table 8.4
S. No.
1.
Parameter of
comparison RAM
Operations involved ROM
2. Type of storage Reading and writing
Reading only
3 Types Temporary
SRAM, DRAM Permanent
Application PROM, EPROM, EEPROM
8.13.9 IC 2764 (EPROM)
Calculators, computer Computers, microprocessor
1. Basic Concepts
IC 2764 is 8192x 8
onocity of this EPROM isEPROM. This means that it can store 8192
65536 bits or 64 K. The number of words of. size 8 bit each. So, the
need to use 12 address lines since
2Z = locations= 8192. To access the
the word size =8, eight bi-directional data8192. Hence, A to Aj, address lines are being used. Since.
electrically
input/output
the pin configuration of 1C 2764. Itt is a 28 pin
window
lines (Do to D) are used. Figure 8.22shows
ceramic frit Since itisan
UV erasable and
programmable EPROM, atransparentduallidinislineprovided
package.
in the package.
 427
Semiconductor Memories

28| Vcc
Vpp 1
27 P
A12 2 Pin No. Description
A
26| NC
25 Ap Ao- Aj2 Address lines
As 4
As5 24 Ag D, - D, Data IO lines

A46
23| A1
E Chip enable
Ag 7 22 G
M 2764
Az 8
21 Aso G Output enable
A 9 20 E
Program
19 D,
Ao 10
18 D6
Power supply
Do11
D 12 17| D5 Supply
Vcc
D2 13 16| D4
Vss Ground
Vss 14 2764
Fig. 8.23. Functions of various pins of IC
Fig. 8.22. Pin configuration of IC 2764
2. Read Operation to this,
the stored data, the chip enable E must be connected to ground. In addition
Just to read
connected to ground. Then, we apply the address of desired
the output enable G also should be achieve the corresponding data on the data
lines.
memory location on the address lines and
3. Programming Operation radiation
programming (writing) we have to erase the EPROM by exposing it to the UV
Before erasure,
for a sufficiently long duration of time. Afterstate. In Vcc Vpp
1
all the bits in 2764 will be in the logic EPROM
new
fact, same will be the condition of a
EPROM is
purchased from the market. The Ao
of only Os. As
programmed by selective programmingconnect
we have to the D, to D,
1n the programming mode, P IC2764
to TTL low
chip enable (E ) and program pin (P)
Then, E
and apply a voltage of 12.5 V to the Vpp pin.line Do
the data
apply the 8 bit data to be stored to G
to Dq. Apply the desired address to program
this data
at the required location. Vss
4. Logic Diagram Fig. 8.24. Logic diagram of IC 2764
Figure 8.24 shows the logic diagram of IC 2764.
8.14 EEPROM (E2 PROM)
The long form of EEPROM is electrically erasable PROM, These are very similar to EPROMS and

Bertrand Russell
The good life is one inspired by love and guided by knowledge.
 5. 3 S. camera,
No.8.16.1 low sections
tunnelling cannot
memories
4 2. 1 or andMEMORY
FLASH
It 8.16 failure.
suchNVRAM RAM contents
in is is
EEPROM. dataWhen RAM TheNVRAM
8.15 has
operating programming used memory very known
EPROM.period torepresents
erasing charge MOStheuse 428
a a as
Costcircuit
PROM
Requirement
remove
from toTime
Selective
erasing
Performance
embedded flash. of be special data in long very erasethale l
Technique data, This electrically
for EEPROM. is
is flash used are does can a
form is of
required into
temporary The volatile low chip Tepresents or 1
Parameterof voltages,
comparison utilized faster type is advantage
Another
and selective
Hence,
memory as time, the not be
EEPROM transferred density. is programming. It
use controllers, of transfer ofNVRAM as
a of greatest
monitor need powered, connected locations
shortwithin circuitry.
for Comparison to random than thisRAM. As
memory. era
for low erase its chip storage erasing.
erasing any soon and
erasing power name EEPROMs time
are
memory It advantage whereas
back NVRAM is compared
in its In
cellular the access is setting battery NVRAM
as
non-volatile It
organized is a in is the possible
absence is
to
isEEPROM, data
consumption non-volatile the to power of
exXpensive
LessPROM ltLong of contents. Flash typically circuit. not
Not
erased.get Exposure
memory thattakes ete.backup, the RAM. EEPROM is about10
is of event to
necessary
EPROMphones, works are essential
possible.
10 NVRAM. Recall fails, that
Memory. in eraseplace Thus, formed RAM. However,
to Important such in of 4
15 to
EPROM because memory ms. all like required ms byto
erase
and etc. and and order signal power is
min. ultraviolet
All block-by-block. the the a It that it
to a NVR.AMs erase a
remove EEPROMdurability. manner write RAM
AsRAM, by is
the
programand astored 0.
the tofailure. a a operating the
features A RAM which is contents soon special
special save combination for
locations new used is whereas drawback can all voltage A in
the the
the light used as formthe
are the be
that is
Typical data is to A the of type
technique of they Because topowered usually
working transfer store for RAM ultraviolet
erased memory as
a be at power when of ofBEPROM particular as lo w
expensive.
VeryPROM. Not Short
ms. 10 only
Fossible-A
particular
locationapplied. A flash can normal of
RAM EEPROM ofDigital
voltage application addressed the used signal are a locations.
essential continuously. charge.
can be byte of data the 1spowerstatic 20
memory called
speed. erased this operation parallely because reprogrammed
radiation Electronics
to
be EEPROM tostored reapplhed is memory
in
of level. store in used fails, RAM 1s
25
erased. 20 at
process, th e a It
to Fowler-Nordheim
areas very ,is Actually.
volts
remVe instantaneousy byte the special
to are Flash e data for
thevent itand however
erasing location.
transferred
and and
25 The information all will
conventional expensive can
are high level. the storing
into Logic
volts memoty erasng of EEPROM the EEPROM mode. presence be
ag save when used possible used
18 Tne flash power RAM. saved This Design
the and
to the the forThis is for of
 7. 6. 5. 4. 3. 2 1
registers
Few Shift classification The wordThere number memory memory
(11) The (iii) particular reliability The Better The are processed A A Write-once is
Read-only
commonly Compare crystalline either
on-volatile
Phase-change Non-volatile Cell
Semiconduct
Memoriores
(1) Sequential
memories (i) (v) (iüi) cost
Low (i) memory.
sub-system system permanent RDRAM: Inemployed
salient
Require "They classification Mode memory N-bit number It salient available
Operating are SUMMARY dark/non-reflective GLOSSARY In:
consists of shall is
are of
N-number for memories,
features long. words memory quite features In andwhich used with state.
less access devices
may of earlier
of of read-many memory
simpler coupled
Charge
devices
(CCD) be completely like computer read1ng, memory RAM
Data locations easy various such DRAM,
to
principle
of per of M processes technology
power be a refer These
ofFig. memories 16 chip x times, CD-ROM.
listed mayinputs of chip to of a a
than
dynamic data
locations N. is expand digital : writing,Read/write :single
for 8.25. be
semiconductortypes Non-volatile SDRAM.
to
technology, discs
memories
write are Hence,
capable and processed various An : if Memory :
operation the (RWM
RAM) or as the mask-programmalble
Memory Readand
classified areinput the
based under 64, number and
processing optical rewritable.are storage
static
memories memory memory alloy and Used :
alsolines. 128, and if of
the size. kinds memorywhich
on :known each storing data. memory an erasing
memories classification on 256, size of memories CD is in element.
the The bits Size. was extremely in
the system digital recordable DVD-RW
its retains
may location of
512, M that
principle basis as data of information.
amorphous
a per which
magnetic
be Memories
Data 1024,memorywords
word may which data read-only will
(idescribed
v) (ii) based (iv) of to can
speed dynamic fast data
characteristics
Physical(ii) be High(iv)Small
size
(ii)
with be requires disc is
and hold
They They of various bus. 2048,
stored store yary
ROM Technology
operation chip listed type. can not
on each can state The
DVD its even
store memory. usually
have are principle as parameters. 4096 one is from be if
is as But a tiny data
or + the
memories
(ROM) specified
put 4-bit word facility recorded Acronym RW
lessunder etc. memory under:
nowadays, all
RAM.reflective
evenpower
high Read
only isused on "pit"
expensive shown having the changed optical
ackaging operation : of PROM these word. above to
for The as on and when is
to store if turned
fabrication in lines The memory.16 N once the "nodiscs. the
bits semi-conductor memories
mentioned
once
figure parameters × the Rambusfor
commonly 4 using phase-change pit" power
EPROM word-by-word then in it A off.
densities. addressable
Content unprocessed, is area
8.25. it, As
phase-change
memories
(CAM) then your
programmed. is
process. it
used means an data of
turned
used the PC dynamic RAM. optical
EAROM example, alloy
is and
for with
values that size known partially
basis oit.
it isdiscalloy
of then ROM in
each this the if 429
of as it s are
of a is
 consists
particular
and number
words memory Ans.The Q.2. Ans. 430
o.1.
a erasing ItEAROM, of In following two
information The The
drawback
per Explainreliability
Better
(v) (iii) cost Write
Low (i) The write. DRAM. We ofathe The store An techniques
makes (b) (a)Programmable AsRead-Only
(ii)memory.
(i) (i) Due
(vi) (v) (iv) (ii) (ii) (i) Few (iii)cost given is the this (i) classes i) th e
of
shall
Low (i) know
DRAMcharge possible ROMs to
It salient SHORT
ItFor For In important
For Flexibility
For Following data Location-by-location
location All erasableerasable Erasing Erasable
Erasing
chip memory 16 is the type, name all
ischaracter that
state operation RAMlocations use
locationsare be about quite storage
suitable look
implementation
implementation as example, as for are theseof
salient cell, held the of dynamic
M of features (i.e., long to under programmable can suggests,
64, easy QUESTIONS up the and memory the using using erasing and further
chipx
locations appicationsadvantages in by
weimplement must desired be salient
256, Memory
N. purpose tables. as simultaneously
is CAM electrical
Hence, is to features forgeneration. systeminformation have the storeperformed
power stored.
ROM
:
Programmable
ultraviolet
electricity. Read
of be memories
classified
expand the capacitor memory is may these
512, eachcapable semiconductor to a erased are features,
if and size? LSI of of ofdesign use bit) erasable
is'The that
Only
1024. is the the a voltage be
microprocessor combinational
of sequential of make applied as non-erasable
location thenumber of memory manufacturing ROM stored an automatically static first information kind describedROMs
ROMradiation
size semiconductor WITH requires long examples locations Memory into is
2048, storing the additional erasable. ROM the the
of may to before memories. offorusing can three
can in as RAM additional
4096 a of size. memories circuits. ROM a the memory erasing be dynamic
memory bits ANSWER be power
to as
(EPROM). (PROM).
store M ROM of can
program. circuits.listed be chip.usingentering location memory.stored ultraviolet under erased categories
etc. words per
process. ancircuitry when be
speed
HighSmall
(iv)size(ii) refreshed to is
one important is erased in
chip word memory. may of Static
t he the in known :and refreshing.
circuitry for
memories
with asspeed
(iv)High(iü)
a by which
4-bit permanent for circuit bipolar new the "The
is vary be under: ROM
RAM
the erasing as
specified each refreshing after location one
as programmed
listed new non-erasable
erasable the under
word. part information
from is is by electrically are
word every cells as
as a of not information. erasable one stored is
The nature.
having
emory-to-memoy* asexample. under: non-volatile many
interrupted. are well and known : widely
commonly 16× the few memories
basically as is then information again Digital
4 digital charge.
milliseconds.
It MOS memory. memory as
then N can to alterable used
bits However, be th e EPROM. and
memory. be technology. can Electronics in
useu 1t systems This flip-flopsentered. new cannot again.
n only In further digital
means 1t, can
Therefore, is EAROM,
information ROM
then As read the in be be Also, The
values : which RAM systems. and
that an main It erased.
be erased
(EAROM),. commony
ofthis the and is categorised the Logc
size camuu drawbaci alongwth can
possible .As ROM
and
and the is
number contents
memo of stay CAN storeÀ annew usel
tor
 O2. State31. d0. 23. 0. 26. k0. 24. Z3. 2. 21. 20. 19. l8. 17. 10. l5. 14. 13. 12. 11. 10. 9. 8 7. 6 5. 4 3 2 1.
l. DRAM. the Ans. Q.5. more ms04.
Differentiate
State Determine
Explain () Expain Explain
Distinguish Write
()
Discuss WiDiscuss
th Write
Explain Draw
Differentiate Explain What Draw Ans. Q.3.
() Write With Write Differentiate Explain ExplainDifferentiate
Explain Explain
How Explain
Explain
Explain DRAM TheWrite (ii) Write
(()The (i) Semiconduct
Memoroires
memory Read-Only
AThe the
memory.i)TheWrite
and two a memory Static short neat a the is a can QUESTIONS REVIEW charge Hence, Erasable
in
working the short a short a
the various short-note
various four RAM, circuit
meant cell, the single
salient
hel p the with it you with the the the ROMs the
explainsalient brief and notes and circuit with we
between most how differences concept
classification
classification Drawback held
cell it
note of note between points between between logic
meaningdifferentiate between
circuit ROM
and requires
as bit classification are
EPROM used many Dynamic types clear types ROM by of a have and
features
in memory.
appropriate neat on diagram compared
by dynamic features further
on on on of ROM basic diagram neat Programmable
to following: circuit and of to the
brief. SRAM
store address and static volatile of
semiconductor of RAM static of block diagram use
and
dynami c between ROMs differentiation static
? static RAM. capacitor of very
clean MOS read-only of their What of classified
ferent of between of an
Dynamic to RAM of
memorylogic.
usingdevelopment
and
bipolar and diagram, static and and IC memories small of
EEPROM. memory bits MOS and diagram memories
the Mention additional static Dynamic
RAM and types. are 7481. ROMs?
DRAM. SRAM ROM
dynamic RAM. requires is
area
RAM.circuit non-volatile
a are RAM memories RAM RAM
dynamic dynamic formed ROM into
typesPROM their the sequential RAM
typeneededdiagram, explainmemories. between on Sketch IC itbased
s based RAM? as RAM.
and cell. types cell. 2716. circuitry (EPROM). three
cell. applications the RAM types. to per
comparedusing
of programs.
instead
read to DRAM. memories. MOS
the
(ROMs). Explain basis of
Explain its on on be unit categoriesunder
use for memories. EPROM Sketch access refreshed (i1)
(1) explain (ii) on ROM Pin-out. Explain their their for only
only TOr a working memory. area.
memory ofthe refreshing to
Programmable
of The each ROM, its 4 ?how memory
its physical
principle static two
ories. in and basis State as
SRAM the brief. parameters.
operation. Compare with after components,
memory operation information Pin-out.
of EPROM, EEPROM. of RAM.
thewhich working their diagram every
thein 4 and characteristics. of th e :
following parameters. between applications. RAM operation. charge. This Read
used has of few
of EEPROM. is wvorking means
one
to 1024 static
bipolar ? milliseconds. Only
them.stored This MOSFET
permanent
programs.
store in
and static of that, Memory
a MOS in is
small16.384 it. any the
the and
RAM RAM one Therefore,
main
computer DRAM a (PROM).
number cell. type drawback capacitor.
cell.
of alongwith consists
: of RAM.
431
bits. of of
a