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UNIT IV

Intel 8086 Microprocessor: Introduction-Intel 8086 Hardware – Pin description – External

memory Addressing – Bus cycles – Interrupt Processing. Addressing modes - Instruction
set – Assembler Directives.

2MARKS:

1. Discuss the function of instruction queue in 8086

2. What is the maximum memory size that can be addressed by 8086?
3. State the function of Bus interface unit(Nov 2019)
4. What are assembler directives? Name any two assembler directives(Nov 2019)
5. What is interrupt processing(Sep 2020)
6. List the addressing modes of 8086(Sep 2020)
11 Marks

1. With diagram describe the architecture of 8086(May 2019)

2. Give a brief note on memory addressing (May 2019)
3. Illustrate the pin description of 8086 with a neat diagram (Nov 2019)
4. Summarize the instruction set of 8086 microprocessor. (Nov 2019)
5. Discuss the addressing modes of 8086 microprocessor with suitable example (Sep 2020)
6. How will you process the interrupts in 8086 microprocessor (Sep 2020)

2 MARKS

1. Discuss the function of instruction queue in 8086.

In 8086, a 6 -byte instruction queue is presented at the Bus Interface Unit (BIU). It is used to
prefetch and store at the maximum of 6 bytes of instruction code from the memory. Due to this,
overlapping instruction fetch with instruction execution increases the processing speed.

2. What is the maximum memory size that can be addressed by 8086?

In 8086, an memory location is addressed by 20 bit address and the address bus is 20 bit address
and the address bus is 20 bits. So it can address up to one mega byte (2^20) of memory space.

3. State the function of Bus interface unit(Nov 2019)

(a) Fetch instructions from memory.
(b) Fetch data from memory and I/O ports.
(c) Write data to memory and I/O ports.

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(d) To communicate with outside world.

(e) Provide external bus operations and bus control signals.

4. What are assembler directives? Name any two assembler directives(Nov 2019)

An assembler is a program which translates an assembly language program into machine

language program. An assembly language program consists of two types of statements:
Instruction & Directives.

The general assembler directives are: ASSUME, EXTRN, GROUP, INCLUDE,

LABEL, MACRO, ORG, PTR, PROC, PUBLIC, RECORD, SEGMENT, STRUC,
EVEN, EQU, END, ENDM, ENDS, ENDP, DT, DQ , DD,DW, DB.
The ASSUME directive enables error-checking for register values. It is used to inform
the assembler the names of the logical segments, which are to be assigned to the different
segments used in an assembly language program.
SEGMENT is used to indicate the start of a logical segment. It defines a program segment
called name having segment attributes align (BYTE, WORD, DWORD), combine
(PUBLIC, STACK), use (USE16, USE32, FLAT), and class.
The ENDS statement indicates the end of the program.

5. What is interrupt processing(Sep 2020)

The interrupts of 8085 are INTR and NMI. The INTR is general mask able interrupt and
NMI is non-mask able interrupt.
An interrupt is a condition that halts the microprocessor temporarily to work on a different
task and then return to its previous task. Interrupt is an event or signal that request to
attention of CPU. This halt allows peripheral devices to access the microprocessor.
Whenever an interrupt occurs the processor completes the execution of the current
instruction and starts the execution of an Interrupt Service Routine (ISR) or Interrupt
Handler. ISR is a program that tells the processor what to do when the interrupt occurs.
After the execution of ISR, control returns back to the main routine where it was
interrupted.
6. List the addressing modes of 8086(Sep 2020)
Microprocessor - 8086 Addressing Modes
 Immediate addressing mode. ...
 Register addressing mode. ...
 Direct addressing mode. ...
 Register indirect addressing mode. ...
 Based addressing mode. ...
 Indexed addressing mode. ...
 Based-index addressing mode. ...
 Based indexed with displacement mode.

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11 Marks

1. With diagram describe the architecture of 8086(May 2019)

8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel
in 1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that provides up
to 1MB storage. It consists of powerful instruction set, which provides operations like
multiplication and division easily.
It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode
is suitable for system having multiple processors and Minimum mode is suitable for system
having a single processor.

Features of 8086

The most prominent features of a 8086 microprocessor are as follows −

 It has an instruction queue, which is capable of storing six instruction bytes from the
memory resulting in faster processing.
 It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus,
and 16-bit external data bus resulting in faster processing.
 It is available in 3 versions based on the frequency of operation −
o 8086 → 5MHz
o 8086-2 → 8MHz
o (c)8086-1 → 10 MHz
 It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves
performance.
 Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
 Execute stage executes these instructions.
 It has 256 vectored interrupts.
 It consists of 29,000 transistors.

Comparison between 8085 & 8086 Microprocessor

 Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.

 Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.
 Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of
memory.
 Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an instruction
queue.
 Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a
pipelined architecture.

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 I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's.
 Cost − The cost of 8085 is low whereas that of 8086 is high.

Architecture of 8086

The following diagram depicts the architecture of a 8086 Microprocessor

2. Give a brief note on memory addressing (May 2019)

The different ways in which a source operand is denoted in an instruction is known
as addressing modes. There are 8 different addressing modes in 8086 programming −

Immediate addressing mode

The addressing mode in which the data operand is a part of the instruction itself is known
as immediate addressing mode.
Example
MOV CX, 4929 H, ADD AX, 2387 H, MOV AL, FFH

Register addressing mode

It means that the register is the source of an operand for an instruction.

Example
MOV CX, AX ; copies the contents of the 16-bit AX register into
; the 16-bit CX register),
ADD BX, AX

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Direct addressing mode

The addressing mode in which the effective address of the memory location is written
directly in the instruction.
Example
MOV AX, [1592H], MOV AL, [0300H]

Register indirect addressing mode

This addressing mode allows data to be addressed at any memory location through an offset
address held in any of the following registers: BP, BX, DI & SI.
Example
MOV AX, [BX] ; Suppose the register BX contains 4895H, then the contents
; 4895H are moved to AX
ADD CX, {BX}

Based addressing mode

In this addressing mode, the offset address of the operand is given by the sum of contents of
the BX/BP registers and 8-bit/16-bit displacement.
Example
MOV DX, [BX+04], ADD CL, [BX+08]

Indexed addressing mode

In this addressing mode, the operands offset address is found by adding the contents of SI or
DI register and 8-bit/16-bit displacements.
Example
MOV BX, [SI+16], ADD AL, [DI+16]

Based-index addressing mode

In this addressing mode, the offset address of the operand is computed by summing the base
register to the contents of an Index register.
Example
ADD CX, [AX+SI], MOV AX, [AX+DI]

Based indexed with displacement mode

In this addressing mode, the operands offset is computed by adding the base register contents.
An Index registers contents and 8 or 16-bit displacement.
Example
MOV AX, [BX+DI+08], ADD CX, [BX+SI+16]

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3. Illustrate the pin description of 8086 with a neat diagram (Nov 2019)
Pin diagram of 8086 microprocessor is as given below:

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V
DC supply for its operation. The 8086 uses 20-line address bus. It has a 16-line data bus. The
20 lines of the address bus operate in multiplexed mode. The 16-low order address bus lines
have been multiplexed with data and 4 high-order address bus lines have been multiplexed
with status signals.
AD0-AD15 : Address/Data bus. These are low order address bus. They are multiplexed with
data. When AD lines are used to transmit memory address the symbol A is used instead ofAD,
for example A0-A15. When data are transmitted over AD lines the symbol D is used in place
of AD, for example D0-D7, D8-D15 or D0-D15.

A16-A19 : High order address bus. These are multiplexed with status signals.

S2, S1, S0 : Status pins. These pins are active during T4, T1 and T2 states and is returned to
passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus
controller for generating all the memory and I/O operation) access control signals. Any change
in S2, S1, S0 during T4 indicates the beginning of a bus cycle.

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A16/S3, A17/S4, A18/S5, A19/S6: The specified address lines are multiplexed with
corresponding status signals.

READY: This is the acknowledgement from the memory or slow device that they have
completed the data transfer. The signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the microprocessor. The signal is active
high(1).

INTR: Interrupt Request. This is triggered input. This is sampled during the last clock cycles
of each instruction for determining the availability of the request. If any interrupt request is
found pending, the processor enters the interrupt acknowledge cycle. This can be internally

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masked after resulting the interrupt enable flag. This signal is active high(1) and has been
synchronized internally.

NMI : Non mask able interrupt. This is an edge triggered input which results in a type II
interrupt. A subroutine is then vectored through an interrupt vector lookup table which is
located in the system memory. NMI is non-maskable internally by software. A transition made
from low(0) to high(1) initiates the interrupt at the end of the current instruction. This input has
been synchronized internally.

INTA: Interrupt acknowledges. It is active low (0) during T2, T3 and Tw of each interrupt
acknowledge cycle.

MN/MX’: Minimum/Maximum. This pin signal indicates what mode the processor will
operate in.

RQ’/GT1′, RQ’/GT0′: Request/Grant. These pins are used by local bus masters used to forc
the microprocessor to release the local bus at the end of the microprocessor’s current bus cycle.
Each of the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.
LOCK’: It’s an active low pin. It indicates that other system bus masters have not been
allowed to gain control of the system bus while LOCK’ is active low(0). The LOCK signal will
be active until the completion of the next instruction.

TEST’: This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will
continue, else the processor remains in an idle state. The input is internally synchronized
during each of the clock cycle on leading edge of the clock.

CLK: Clock Input. The clock input provides the basic timing for processing operation and bus
control activity. It’s an asymmetric square wave with a 33% duty cycle.

RESET: This pin requires the microprocessor to terminate its present activity immediately.
The signal must be active high(1) for at least four clock cycles.

Vcc : Power Supply( +5V D.C.)

GND: Ground

QS1, QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction
queue according to the table shown below

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DT/R: Data Transmit/Receive. This pin is required in minimum systems that want to use an
8286 or 8287 data bus transceiver. The direction of data flow is controlled through the
transceiver.

DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum
system which uses transceiver. DEN is active low(0) during each memory and input-output
access and for INTA cycles.

HOLD/HOLDA : HOLD indicates that another master has been requesting a local bus .This is
an active high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as
an acknowledgement in the middle of a T4 or T1 clock cycle.

ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into
the 8282 or 8283 address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE
signal is never floated, is always integer.

BHE’/S7 : Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most
significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use
BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal is available during
T2, T3 and T4.

RD’: This is used for read operation. It is an output signal. It is active when low .

4. Summarize the instruction set of 8086 microprocessor. (Nov 2019)

The 8086 microprocessor supports 8 types of instructions −

 Data Transfer Instructions

 Arithmetic Instructions
 Bit Manipulation Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions
Let us now discuss these instruction sets in detail.

Data Transfer Instructions

These instructions are used to transfer the data from the source operand to the destination
operand. Following are the list of instructions under this group −
Instruction to transfer a word
 MOV − Used to copy the byte or word from the provided source to the provided
destination.
 PPUSH − Used to put a word at the top of the stack.

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 POP − Used to get a word from the top of the stack to the provided location.
 PUSHA − Used to put all the registers into the stack.
 POPA − Used to get words from the stack to all registers.
 XCHG − Used to exchange the data from two locations.
 XLAT − Used to translate a byte in AL using a table in the memory.
Instructions for input and output port transfer
 IN − Used to read a byte or word from the provided port to the accumulator.
 OUT − Used to send out a byte or word from the accumulator to the provided port.
Instructions to transfer the address
 LEA − Used to load the address of operand into the provided register.
 LDS − Used to load DS register and other provided register from the memory
 LES − Used to load ES register and other provided register from the memory.
Instructions to transfer flag registers
 LAHF − Used to load AH with the low byte of the flag register.
 SAHF − Used to store AH register to low byte of the flag register.
 PUSHF − Used to copy the flag register at the top of the stack.
 POPF − Used to copy a word at the top of the stack to the flag register.

Arithmetic Instructions

These instructions are used to perform arithmetic operations like addition, subtraction,
multiplication, division, etc.
Following is the list of instructions under this group −
Instructions to perform addition
 ADD − Used to add the provided byte to byte/word to word.
 ADC − Used to add with carry.
 INC − Used to increment the provided byte/word by 1.
 AAA − Used to adjust ASCII after addition.
 DAA − Used to adjust the decimal after the addition/subtraction operation.
Instructions to perform subtraction
 SUB − Used to subtract the byte from byte/word from word.
 SBB − Used to perform subtraction with borrow.
 DEC − Used to decrement the provided byte/word by 1.
 NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.
 CMP − Used to compare 2 provided byte/word.
 AAS − Used to adjust ASCII codes after subtraction.
 DAS − Used to adjust decimal after subtraction.
Instruction to perform multiplication
 MUL − Used to multiply unsigned byte by byte/word by word.
 IMUL − Used to multiply signed byte by byte/word by word.

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 AAM − Used to adjust ASCII codes after multiplication.

Instructions to perform division
 DIV − Used to divide the unsigned word by byte or unsigned double word by word.
 IDIV − Used to divide the signed word by byte or signed double word by word.
 AAD − Used to adjust ASCII codes after division.
 CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower
byte.
 CWD − Used to fill the upper word of the double word with the sign bit of the lower
word.

Bit Manipulation Instructions

These instructions are used to perform operations where data bits are involved, i.e. operations
like logical, shift, etc.
Following is the list of instructions under this group −
Instructions to perform logical operation
 NOT − Used to invert each bit of a byte or word.
 AND − Used for adding each bit in a byte/word with the corresponding bit in another
byte/word.
 OR − Used to multiply each bit in a byte/word with the corresponding bit in another
byte/word.
 XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the
corresponding bit in another byte/word.
 TEST − Used to add operands to update flags, without affecting operands.

Instructions to perform shift operations

 SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
 SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
 SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into the
new MSB.
Instructions to perform rotate operations
 ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry
Flag [CF].
 ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry
Flag [CF].
 RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to
MSB.
 RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.

String Instructions

String is a group of bytes/words and their memory is always allocated in a sequential order.
Following is the list of instructions under this group −

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 REP − Used to repeat the given instruction till CX ≠ 0.

 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
 REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
 MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
 COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
 INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided
memory location.
 OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided
memory location to the I/O port.
 SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL
or string word with a word in AX.
 LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX.

Program Execution Transfer Instructions (Branch and Loop Instructions)

These instructions are used to transfer/branch the instructions during an execution. It includes
the following instructions −
Instructions to transfer the instruction during an execution without any condition −
 CALL − Used to call a procedure and save their return address to the stack.
 RET − Used to return from the procedure to the main program.
 JMP − Used to jump to the provided address to proceed to the next instruction.
Instructions to transfer the instruction during an execution with some conditions −
 JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
 JAE/JNB − Used to jump if above/not below instruction satisfies.
 JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
 JC − Used to jump if carry flag CF = 1
 JE/JZ − Used to jump if equal/zero flag ZF = 1
 JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
 JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
 JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
 JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
 JNC − Used to jump if no carry flag (CF = 0)
 JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
 JNO − Used to jump if no overflow flag OF = 0
 JNP/JPO − Used to jump if not parity/parity odd PF = 0
 JNS − Used to jump if not sign SF = 0
 JO − Used to jump if overflow flag OF = 1
 JP/JPE − Used to jump if parity/parity even PF = 1
 JS − Used to jump if sign flag SF = 1

Processor Control Instructions

These instructions are used to control the processor action by setting/resetting the flag values.
Following are the instructions under this group −
 STC − Used to set carry flag CF to 1
 CLC − Used to clear/reset carry flag CF to 0
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 CMC − Used to put complement at the state of carry flag CF.

 STD − Used to set the direction flag DF to 1
 CLD − Used to clear/reset the direction flag DF to 0
 STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
 CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.

Iteration Control Instructions

These instructions are used to execute the given instructions for number of times. Following is
the list of instructions under this group −
 LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
 LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0
 LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX
=0
 JCXZ − Used to jump to the provided address if CX = 0

Interrupt Instructions

These instructions are used to call the interrupt during program execution.
 INT − Used to interrupt the program during execution and calling service specified.
 INTO − Used to interrupt the program during execution if OF = 1
 IRET − Used to return from interrupt service to the main program

5. Discuss the addressing modes of 8086 microprocessor with suitable example (Sep
2020)
Prerequisite – Addressing modes, Addressing modes in 8085 microprocessor
The way of specifying data to be operated by an instruction is known as addressing modes.
This specifies that the given data is an immediate data or an address. It also specifies whether
the given operand is registered or register pair.
Types of addressing modes:
Register mode – In this type of addressing mode both the operands are registers.
Example:
MOV AX, BX
XOR AX, DX
ADD AL, BL
Immediate mode – In this type of addressing mode the source operand is a 8 bit or 16 bit data.
Destination operand can never be immediate data.
Example:
MOV AX, 2000
MOV CL, 0A
ADD AL, 45
AND AX, 0000

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Note that to initialize the value of segment register an register is required.

MOV AX, 2000
MOV CS, AX
Displacement or direct mode – In this type of addressing mode the effective address is
directly given in the instruction as displacement.
Example:
MOV AX, [DISP]
MOV AX, [0500]
Register indirect mode – In this addressing mode the effective address is in SI, DI or BX.
Example:
MOV AX, [DI]
ADD AL, [BX]
MOV AX, [SI]
Based indexed mode – In this the effective address is sum of base register and index register.
Base register: BX, BP
Index register: SI, DI
The physical memory address is calculated according to the base register.
Example:
MOV AL, [BP+SI]
MOV AX, [BX+DI]
Indexed mode – In this type of addressing mode the effective address is sum of index register
and displacement.
Example:
MOV AX, [SI+2000]
MOV AL, [DI+3000]
Based mode – In this the effective address is the sum of base register and displacement.
Example:
MOV AL, [BP+ 0100]
Based indexed displacement mode – In this type of addressing mode the effective address is
the sum of index register, base register and displacement.
Example:
MOV AL, [SI+BP+2000]
String mode – This addressing mode is related to string instructions. In this the value of SI
and DI are auto incremented and decremented depending upon the value of directional flag.
Example:
MOVS B
MOVS W

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Input/output mode – This addressing mode is related with input output operations.
Example:
IN A, 45
OUT A, 50
Relative mode –
In this the effective address is calculated with reference to instruction pointer.
Example:
JNZ 8 bit address
IP=IP+8 bit address

6. How will you process the interrupts in 8086 microprocessor (Sep 2020)
Interrupt is the method of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor. The microprocessor responds to that interrupt
with an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor
on how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts

Hardware interrupt is caused by any peripheral device by sending a signal through a specified
pin to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-mask able
interrupt and INTR is a mask able interrupt having lower priority. One more interrupt pin
associated is INTA called interrupt acknowledge.

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NMI
It is a single non-mask able interrupt pin (NMI) having higher priority than the maskable
interrupt request pin (INTR) and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value of the return
address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.

INTR
The INTR is a mask able interrupt because the microprocessor will be interrupted only if
interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear
interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled,
then the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice.
The first ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the
microprocessor receives the 8 bit, say X, from the programmable interrupt controller.
These actions are taken by the microprocessor −
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the return address are
pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0

Software Interrupts

Some instructions are inserted at the desired position into the program to create interrupts.
These interrupt instructions can be used to test the working of various interrupt handlers. It
includes −
INT- Interrupt instruction with type number
It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the
stack.
 IP is loaded from the contents of the word location ‘type number’ × 4
 CS is loaded from the contents of the next word location.

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 Interrupt Flag and Trap Flag are reset to 0

The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for
type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. −
 TYPE 0 interrupt represents division by zero situation.
 TYPE 1 interrupt represents single-step execution during the debugging of a program.
 TYPE 2 interrupt represents non-mask able NMI interrupt.
 TYPE 3 interrupt represents break-point interrupt.
 TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and
interrupts from 32 to Type 255 are available for hardware and software interrupts.
INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the
program so that when the processor reaches there, then it stops the normal execution of program
and follows the break-point procedure.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the
stack.
 IP is loaded from the contents of the word location 3×4 = 0000CH
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0

INTO - Interrupt on overflow instruction

It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As
the name suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow
flag is set to 1 and branches to the interrupt handler whose interrupt type number is 4. If the
overflow flag is reset then, the execution continues to the next instruction.
Its execution includes the following steps −
 Flag register values are pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the
stack.
 IP is loaded from the contents of word location 4×4 = 00010H
 CS is loaded from the contents of the next word location.
 Interrupt flag and Trap flag are reset to 0

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