Alu
Alu
// Company:
// Engineer:
//
// Create Date: 08.05.2021 12:39:16
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module alu( input [7:0] A,
input [7:0] B,
input alu_cl,
output reg [7:0] Result,
output reg zero);
always@(*)
begin
case(alu_cl)
1'b0:
begin
Result= A+B;
if(Result==0)
zero=1'b1;
else
zero=1'b0;
end
1'b1:
begin
Result= B;
if(Result==0)
zero=1'b1;
else
zero=1'b0;
end
default:
begin
Result=8'bx;
zero=1'bx;
end
endcase
end
endmodule