EC340 COA

Division

RISC-V Division
Four instructions:
◦ div, rem: signed divide, remainder
◦ divu, remu: unsigned divide, remainder

Overflow and division-by-zero don’t produce errors

◦ Just return defined results
◦ Faster for the common case of no error
Software must check the divisor to discover division by 0 as well as overflow.

COA DIVISION 2

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 EC340 COA

Division
quotient Check for 0 divisor
dividend
Long division approach
1001
◦ If divisor ≤ dividend bits
1000 1001010
◦ 1 bit in quotient, subtract
-1000
divisor ◦ Otherwise
10
101 ◦ 0 bit in quotient, bring down next dividend bit
1010 Restoring division
-1000
◦ Do the subtract, and if remainder goes < 0,
remainder 10
add divisor back

n-bit operands yield n-bit

quotient and remainder

COA DIVISION 3

Division Hardware
Initially divisor
in left half

Initially dividend

COA DIVISION 4

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 EC340 COA

Optimized Divider
Divisor M

Quotient Q

Remainder A

One cycle per partial-remainder subtraction

Looks a lot like a multiplier!
◦ Same hardware can be used for both

COA DIVISION 5

Restoring division
Dividend (n bits) = Divisor (n bits) x Quotient (n bits) + Remainder (n bits)
Steps
◦ Initial Remainder A  0, Quotient Q  Dividend, Divisor M  Divisor
◦ Repeat n times
◦ Shift A and Q one bit left
◦ Sub M from A and place result in A
◦ If sign of A is 1 (ie A<M) then q0  0 and add M to A (restore A) else q0  1

◦ When A-M is computed Carry out =1 if result is positive

COA DIVISION 6

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 EC340 COA

Example 8 /3 = 1000/0011 M=0011 -M=1101

Step A Q
Initial 0000 1000
Shift Left A|Q 0001 000-
Sub M 1110 000 -
Restore A set q0 = 0 0001 0000 bit3
Shift Left A|Q 0010 000-
Sub M 1111 000-
Restore A set q0 = 0 0010 0000 bit2
Shift Left A|Q 0100 000-
Sub M 0001 000-
Set q0 = 1 0001 0001 Bit1
Shift Left A|Q 0010 001-
Sub M 1111 001-
Restore A set q0 = 0 0010 0010 bit0
Remainder Quotient
COA DIVISION 7

Modifications
Non restoring division
Non performing division
Array Divider

COA DIVISION 8

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 EC340 COA

Non Restoring division

Dividend (n bits) = Divisor (n bits) x Quotient (n bits) + Remainder (n bits)
In restoring division
◦ After subtraction
◦ if A is +ve next step is Shift left A – M = 2A-M
◦ If A is –ve next step is A+M then Shift left A –M = 2(A+M)-M = 2A+M

Steps
◦ Initial Remainder A  0, Quotient Q  Dividend, Divisor M  Divisor
◦ Repeat n times
◦ If the sign of A is 0, shift A and Q left one bit position and subtract M from A; otherwise, shift A
and Q left and add M to A.
◦ Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.
◦ If the sign of A is 1, add M to A

COA DIVISION 9

Example Step
8 /3 = 1000/0011 M=0011 -M=1101
A Q
Initial 0000 1000
Shift Left A|Q 0001 000-
Sub M 1110 000 -
Set q0 = 0 1110 0000 bit3
Shift Left A|Q 1100 000-
Add M 1111 000-
Set q0 = 0 1111 0000 bit2
Shift Left A|Q 1110 000-
Add M 0001 000-
Set q0 = 1 0001 0001 Bit1
Shift Left A|Q 0010 001-
Sub M 1111 001-
Set q0 = 0 1111 0010 Bit0
Add M to Restore A 0010 0010
Remainder Quotient
COA DIVISION 10

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 EC340 COA

Exercise
Try restoring and non restoring algorithm for 13/4

COA DIVISION 11

Nonperforming division
Restoring division uses a temporary register (T)
Restoring division that stores A in a temporary register (T)
◦ In case A-M is –ve then A is restored from T

Restoring division that A-M in a temporary register (T)

◦ If A-M is +ve then T is written to A

Saves an addition but needs an extra register

COA DIVISION 12

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 EC340 COA

Signed division
Dividend Divisor Quotient Remainder
5 3 1 2
5 -3 -1 2
-5 3 -1 -2
-5 -3 1 -2

Dividend (z) = Divisor (d) x Quotient (q) + Remainder (s)

sign (s) = sign (z)
|s| < |d|

Divide using absolute values

Adjust sign of quotient and remainder as required

COA DIVISION 13

Array Divider - Restoring

Dividend – 6 bit
Divisor – 3bit
Quotient – 3 bit
Remainder – 3 bit

CS – Controlled subtractor
VA – Full adder
𝑠𝑖′ = 𝑠𝑖  di  ci qk=1
si qk=0 1. Subtraction
2. Evaluation of quotient bit qk
ci+1 = ci di + 𝑠ഥ𝑖 (ci + di)
3. Selection of new remainder (mux)
Delay = O(n2)

COA DIVISION 14

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 EC340 COA

Faster Division
Can’t use parallel hardware as in multiplier
◦ Subtraction is conditional on sign of remainder

Faster dividers (e.g. SRT division) generate multiple quotient bits per
step (prediction)
◦ Still require multiple steps
RISC-V has a single pair of 32-bit registers that are used both for multiply and
divide
Division is accelerated by predicting multiple quotient bits and then correcting
mispredictions later

COA DIVISION 16

Right Shift and Division

Left shift by i places multiplies an integer by 2i
Right shift divides by 2i?
◦ Only for unsigned integers

For signed integers

◦ Arithmetic right shift: replicate the sign bit
◦ e.g., –5 / 4
◦ 111110112 >> 2 = 111111102 = –2
◦ Rounds toward –∞
◦ 111110112 >>> 2 = 001111102 = +62

COA 17

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