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    Be Electronics and Computer Science Semester 3 2022 December Electronic Devices Rev 2019 C Scheme - PDF 10-31-24 11 33pm

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    zakimurudkar101

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    Be Electronics and Computer Science Semester 3 2022 December Electronic Devices Rev 2019 C Scheme - PDF 10-31-24 11 33pm

    Uploaded by

    zakimurudkar101
    6 views1 page

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    Be Electronics and Computer Science Semester 3 2022 December Electronic Devices Rev 2019 c Scheme.pdf 10-31-24 11 33pm

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    © All Rights Reserved
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    6 views1 page

    Be Electronics and Computer Science Semester 3 2022 December Electronic Devices Rev 2019 C Scheme - PDF 10-31-24 11 33pm

    Uploaded by

    zakimurudkar101

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    Givee the answers for given pdf

    I can provide a summary of the questions and topics covered in the PDF. Here
    is an outline of the questions and their respective topics based on the document:
    1. Attempt any FOUR [20 Marks]
    • a. Describe the pinch-off condition in JFET with a neat labeled
    diagram.
    • b. Write a short note on memristors, including suitable neat
    sketches.
    • c. Describe the operation of the capacitor (C) filter with appropri-
    ate waveforms and a neat sketch.
    • d. Explain the concept of DC load line & Q – Point in bipolar
    junction transistor (BJT).
    • e. Draw the output waveform for a given circuit with a 20V peak-
    to-peak input signal.
    2. a. Describe the working of a bridge type full wave rectifier with a neat
    sketch. Draw output voltage waveforms and mention the expression for
    DC or average output voltage (Vdc) [10 Marks].
    • b. Explain the Zener diode as a voltage regulator with neat sketches
    for varying load resistance and varying DC supply voltage [10 Marks].
    3. a. Explain how a PN junction is formed with a neat diagram [10 Marks].
    • b. Explain the construction, working, and VI characteristics of n-
    channel JFET with neat diagrams [10 Marks].
    4. a. Draw a circuit diagram of a common source (CS) E-MOSFET amplifier
    and derive the equations for voltage gain (Av), input resistance (Ri), and
    output resistance (Ro) [10 Marks].
    • b. Perform small signal (AC) analysis using the hybrid-� model for
    a small signal amplifier in common emitter (CE) BJT configuration
    using voltage divider biasing [10 Marks].
    5. a. Write a short note on solar cells describing their structure, working,
    and V-I characteristics, along with real-life applications [10 Marks].
    • b. Draw a circuit diagram and explain the operation of different
    biasing circuits used for E-MOSFET [10 Marks].
    6. a. Explain the construction and working principle of a Single Electron
    Transistor [10 Marks].
    • b. Draw all the different biasing circuits of BJT and derive the
    expression of the stability factor (SI) for the voltage divider biasing
    circuit [10 Marks].
    If you need specific answers to any of these questions, please let me know which
    ones you would like to focus on, and I can provide inferred answers based on
    typical knowledge in electronics.
    References: p.1, p.1, p.2, p.2

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