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Lecture 11p3

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29 views11 pages

Lecture 11p3

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sabrinahema110
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EEE 411/ECE411/CSE460

– VLSI DESIGN
Dr. Touhidur Rahman
Professor,
Dept. of EEE, Brac University
[email protected]
Static Power

■ Static power is consumed even when chip is quiescent.


– Leakage draws power from nominally OFF devices
– Ratioed circuits burn power in fight between ON transistors
■ Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
– Subthreshold leakage
– Gate leakage
– Junction leakage
– Contention current
Subthreshold Leakage
■ For Vds > 50 mV Typical values in 65 nm
Ioff = 100 nA/μm @ Vt = 0.3 V
Ioff = 10 nA/μm @ Vt = 0.4 V
𝐼 𝐼 10 Ioff = 1 nA/μm @ Vt = 0.5 V
η = DIBL (Drain-Induced Barrier
Lowering) Coefficient = 0.1
■ Ioff = leakage at Vgs = 0, Vds = VDD kγ = Body Effect Coefficient = 0.1
S = Subthreshold Slope = 100 mV/decade
Stack Effect
■ Series OFF transistors have less leakage
– Vx > 0, so N2 has negative Vgs
– Leakage through 2-stack reduces ~10x
– Leakage through 3-stack reduces further
Leakage Control

■ Leakage and delay trade off


– Aim for low leakage in sleep and low delay in active mode
■ To reduce leakage:
– Increase Vt: multiple Vt
■ Use low Vt only in critical circuits
– Increase Vs: stack effect
■ Input vector control in sleep
– Decrease Vb
■ Reverse body bias in sleep
■ Or forward body bias in active mode
Gate Leakage

■ Extremely strong function of tox and Vgs


– Negligible for older processes
– Approaches subthreshold leakage at 65 nm and below in some processes
■ An order of magnitude less for pMOS than nMOS
■ Control leakage in the process using tox > 10.5 Å
– High-k gate dielectrics help
– Some processes provide multiple tox
■ e.g. thicker oxide for 3.3 V I/O transistors
■ Control leakage in circuits by limiting VDD
Junction Leakage

■ From reverse-biased p-n junctions


– Between diffusion and substrate or well
■ Ordinary diode leakage is negligible
■ Band-to-band tunneling (BTBT) can be significant
– Especially in high-Vt transistors where other leakage is small
– Worst at Vdb = VDD
■ Gate-induced drain leakage (GIDL) exacerbates
– Worst for Vgd = -VDD (or more negative)
Static Power Example
■ Revisit power estimation for 1 billion transistor chip:
■ 1 billion transistor chip
– 50M logic transistors - Average width: 12 λ
– 950M memory transistors - Average width: 4 λ
– 1.0 V 65 nm process
– λ=25nm
■ Estimate static power consumption
– Subthreshold leakage
■ Normal Vt: 100 nA/μm
■ High Vt: 10 nA/μm
■ High Vt used in all memories and in 95% of
logic gates
■ 50% OFF & 50% ON
– Gate leakage 5 nA/μm
– Junction leakage negligible
Solution
Power Gating
■ Turn OFF power to blocks when they are idle to save leakage
– Use virtual VDD (VDDV)
– Gate outputs to prevent
invalid logic levels to next block

■ Voltage drop across sleep transistor degrades performance


during normal operation
– Size the transistor wide enough to minimize impact
■ Switching wide sleep transistor costs dynamic power
– Only justified when circuit sleeps long enough
THANK YOU

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