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SV Updated Syllabus

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25 views1 page

SV Updated Syllabus

Uploaded by

sainath reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SYSTEM VERILOG

S.NO TOPICS
Introduction of System Verilog, Self-checking testbench, why we are moving from verilog to SV and eventually UVM. Difference
1 between Testcase and Testbench, Self checking TB in pure verilog, Drawbacks of verilog. Architecture of SV Environment
2 Data Types of th SV,Enum,user defined data type
3 Fixed array,packed array and unpacked array
4 Dynamic array and Associative array
5 Array manipulation methods
6 Introduction to Class, Control flow statement
7 Procedural Statements and Flow Control(unique if,priority if,loops)
8 Process(fork-join,fork-join_any,fork-join_none,disable fork,wait fork)
9 Functions and task
10 Randomization,class inheritance
11 Data Hiding and Polymorphism,Pure virtual method
12 Parameterized class,type def class
13 shallow copy, deep copy, static casting and dynamic casting
14 Inter Process Communication (semaphore,mailbox,events)
15 Interface,virtual Interface,modports and clocking blocks
16 Program Block and Regions of sv
17 Constraints block,inside operator,weighted distribution ,implication and if-else
18 Inline constraints,function in constraints,soft contraints,unique constraints
19 Bi-directional constraints,Solve Before,Random System method
20 Practice Constraints
21 Practice Constraints
22 Coverage, Code coverage, functional coverage, Automatic/implicit bins, explicit bins
23 bins for transitions, cross coverage, coverage options
24 Practice Coverage
25 Practice Coverage
26 Assertions,SVA Buliding blocks,Implication operator
27 Repetition operator,Built in methods
28 Practice Assertions
29 Practice Assertions, Packages
30 Develop Environment (MUX 2x1)
31 Develop Environment (MUX 2x1)
32 Develop Environment (MUX 2x1)
33 Develop Environment (RAM)
34 Develop Environment (RAM)

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