Multi-level Logic:

Combinatorial Circuits

Becker/Molitor, Chapter 8.1

Univ.-Prof. Dr. Jan Reineke

Universität des Saarlandes

Circuits System Architecture, Jan Reineke 1

 Roadmap: Computer architecture

1. Combinatorial circuits:
Boolean Algebra/Functions/Expressions
2. Combinatorial Circuits in Chisel

6:0
Control
Unit
PCSrc
ResultSrc
MemWrite
3. Number representations
ALUControl2:

4. Arithmetic Circuits:
op
14:12 0
funct3 ALUSrc
30
funct75 ImmSrc1:0

Addition, Multiplication, ALU

Zero RegWrite

CLK CLK
CLK
19:15 WE3 SrcA Zero WE
0 PCNext PC Instr A1 RD1 0
A RD ReadData
ALU

1 ALUResult
A RD 1

5. Sequential circuits: Flip-Flops, Registers,

Instruction 24:20
A2 RD2 0 SrcB Data
Memory 11:7
A3 1 Memory
Register WriteData
WD3 WD

SRAM, Moore and Mealy automata

File

PCTarget

6. Sequential Circuits in Chisel

+

ImmExt
31:7
Extend
PCPlus4
+

Result
4

7. Instruction Set Architecture

8. Microarchitecture

9. Performance: RISC vs. CISC, Pipelining,

Memory Hierarchy
 Roadmap: Computer architecture

1. Combinatorial circuits:
Boolean Algebra/Functions/Expressions
2. Combinatorial Circuits in Chisel

6:0
Control
Unit
PCSrc
ResultSrc
MemWrite
3. Number representations
ALUControl2:

4. Arithmetic Circuits:
op
14:12 0
funct3 ALUSrc
30
funct75 ImmSrc1:0

Addition, Multiplication, ALU

Zero RegWrite

CLK CLK
CLK
19:15 WE3 SrcA Zero WE
0 PCNext PC Instr A1 RD1 0
A RD ReadData
ALU

1 ALUResult
A RD 1

5. Sequential circuits: Flip-Flops, Registers,

Instruction 24:20
A2 RD2 0 SrcB Data
Memory 11:7
A3 1 Memory
Register WriteData
WD3 WD

SRAM, Moore and Mealy automata

File

PCTarget

6. Sequential Circuits in Chisel

+

ImmExt
31:7
Extend
PCPlus4
+

Result
4

7. Instruction Set Architecture

8. Microarchitecture

9. Performance: RISC vs. CISC, Pipelining,

Memory Hierarchy
 Recap: Boolean Calculus

Boolean expressions
ib e
e s cr
d
can be
Boolean functions converted
im into each
p le
me other
mo nt
Boolean algebra d el
Rules for the manipulation
of Boolean functions Circuits
Boolean calculus 4
 Contruction of Boolean expressions
from truth tables
1. Consider all rows for which the
function is 1.
x1 x2 x3 s
0 0 0 0
2. Construct the minterm for the 0 0 1 0
valuation of x1, x2 und x3 in the 0 1 0 0
row as follows: 0 1 1 1
– if xi is 1 Þ xi 1 0 0 0
– if xi is 0 Þ xi’ 1 0 1 1
1 1 0 1
3. Combine all minterms by a 1 1 1 1
disjunction

Boolean Calculus System Architecture, Jan Reineke 5

 Special Boolean expressions:
Polynomials
• For a valuation a Î Bn we call
$
%!
𝑚 𝛼 = $ 𝑥! with 𝑥!" ≔ 𝑥! and 𝑥!# ≔ 𝑥! ′
!"#
the minterm associated with a.
• A disjunction of pairwise different monomials
is called polynomial.
If all monomials in a polynomial are minterms,
then the polynomial is complete.

Boolean Calculus System Architecture, Jan Reineke 6

 Canonical disjunctive normal form
$
%!
& 𝑚(𝛼) = & $ 𝑥!
%∈'((*) %∈'((*) !"#
is called canonical disjunctive normal form (CDNF) of f.

• The CDNF of f is unique

up to the order of the literals in the minterms and the order
of the minterms in the polynomial.
• There are other “two-level” canonical normal forms,
e.g., the canonical conjunctive normal form.
Boolean Calculus System Architecture, Jan Reineke 7
 Plan for Today
Wanted:
• Practical implementation of Boolean expressions
• Cheaper representations of Boolean functions that
need not be based on Boolean polynomials
– There are Boolean functions whose best representations
via Boolean polynomials are very expensive…

Approach:
• Find implementations for simple Boolean functions
• Compose these to implement more complex functions
à leads to hierarchical models

Circuits System Architecture, Jan Reineke 8

 Examples of simple Boolean functions...

i2 i1 AND2 i2 i1 OR2 i NOT

0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
also:
i1 i1 i1 i1
i2 i2 i2

i2 i1 NAND2 i2 i1 NOR2 i2 i1 XOR2

0 0 1 0 0 1 0 0 0
0 1 1 0 1 0 0 1 1
1 0 1 1 0 0 1 0 1
1 1 0 1 1 0 1 1 0
i1 i1 i1
i2 i2 i2
Circuits 9
Short excursion: Transistors
p-type transistor n-type transistor
sink sink

source source

• A transistor can be seen as a voltage-controlled switch:

– Gate g controls the conductivity between source and sink
• n-type transistor:
– transmits, if gate is 1
– disconnects, if gate is 0
• p-type transistor:
– transmits, if gate is 0
– disconnects, if gate is 1 10
 Short excursion: MOS transistors
• CMOS = Complementary Metal Oxide Semiconductor
• CMOS uses n-type as well as
“complementary” p-type transistors

Circuits System Architecture, Jan Reineke 11

 Short excursion: CMOS inverter (1/3)

5 V = logical 1

p-type transistor

[0 V, 5 V]

n-type transistor

0 V = logical 0

Circuits System Architecture, Jan Reineke 12

 Short excursion: CMOS inverter (2/3)

5 V = logical 1

p-type transistor
disconnects

5 V = logical 1 0 V = logical 0

transmits
n-type transistor

0 V = logical 0

Circuits System Architecture, Jan Reineke 13

 Short excursion: CMOS inverter (3/3)

5 V = logical 1

p-type transistor
transmits

0 V = logical 0 5 V = logical 1

disconnects
n-type transistor

0 V = logical 0

Circuits System Architecture, Jan Reineke 14

 Short excursion: CMOS NAND

Output is 0 iff
there is a transmitting path from 0 to the output,
i.e., iff both n-type transistors transmit,
a = b = 1,
then NAND(a, b) = 0

Output is 1 iff
there is a transmitting path from 1 to the output,
i.e., iff one of the p-type transistors transmits,
a = 0 or b = 0,
then NAND(a, b) = 1

Circuits System Architecture, Jan Reineke 15

 Implementation of Boolean functions

• In this way, implementations of all required

basic operations are designed.

These comprise the cells of a cell library.

• More complex functions:

“Composition” of these basic operations

Circuits System Architecture, Jan Reineke 16

 Implementation of Boolean functions:
Example of a Boolean function f Î B8, 2

Questions:
1. How to model circuits
mathematically? nt ax
Sy

2. Which Boolean function is

computed by a given circuit?
• Concrete simulation
• Symbolic simulation s
ntic
ema
S

Circuits System Architecture, Jan Reineke 17

 Modeling circuits

Intuitively:
A circuit is a directed graph with some
additional properties.

Circuits System Architecture, Jan Reineke 18

 Modeling circuits (1/3)

• A cell library BIB Í Bn contains basic operations

corresponding to basic gates
• A 5-tuple C = (Xn, G, type, IN, Ym) is called circuit
with n inputs and m outputs (for library BIB) iff
– Xn = (x1, ..., xn) is a finite sequence of inputs.
– G = (V, E) is a directed acyclic graph (DAG) with
{0, 1} ∪ {x1, ..., xn} Í V and E Í V x V.
– The set I = V \ ({0, 1} ∪ (x1, ..., xn)) is called the
set of gates.

Circuits System Architecture, Jan Reineke 19

 Modeling circuits (2/3)

• The mapping type : I → BIB assigns a cell type

type(v) ∊ BIB to each gate v ∊ I.
• For each gate v ∊ I with type(v) ∊ Bk
we have indeg(v) = k.
For v ∊ V \ I = {0, 1} ∪ {x1, ..., xn} we have indeg(v) = 0.

Circuits System Architecture, Jan Reineke 20

 Modeling circuits (3/3)

• The mapping IN : I → V* determines the order

of the incoming edges, i.e., if indeg(v) = k then
IN(v) = (v1, ..., vk) with ∀1≤i≤k: (vi, v) ∊ E.
• The sequence Yn = (y1, ..., yn) designates the
nodes yi ∊ V as the circuit’s outputs.

Circuits System Architecture, Jan Reineke 21

Example circuit
Inputs:
x1 x2 x3 x4 x5 x6 x7 x8 X = (x1, x2, x3, x4, x5, x6, x7, x8)
g1 g2 g3 Outputs:
Y = (g7, g8)
Gates:
g4 g5 g6 I = {g1, g2, g3, g4, g5, g6, g7, g8}
Edges of the graph:
g7 g8
E = {(x1,g7), (x2,g1), (x3,g1), (x4,g2)
y1 = g7 y2 = g8 (x5,g2), (x6,g3), (x7,g3), (x8,g5),
(x8,g6), (g1,g4), (g2,g4), …}
Types of gates: Order of the incoming edges:
type(g1) = type(g4) = XOR2 IN(g1)=(x2, x3)
type(g2) = type(g6) = AND2 ... IN(g4)=(g1, g2) ... 22
 Semantics of circuits (1/3)
• Given a circuit C = (Xn, G, typ, IN, Ym) for the
cell library BIB.
• What function does the circuit compute?
 Semantics of circuits (2/3)
• Given a circuit C = (Xn, G, typ, IN, Ym) for the
cell library BIB.
• Let a = (a1, …, an) ∊ Bn be an input valuation.
• A valuation FC,a : V → {0, 1} for all nodes v ∊ V is given
via the following definitions:
– FC,a(xi) = ai ∀1£ i £ n
– FC,a(0) = 0, FC,a(1) = 1
– If v ∊ I with
type(v) = g ∊ Bk and IN(v) = (v1, …, vk),
then
FC,a(v) := g(FC,a(v1), …, FC,a(vk)).
Why is FC,a(v) Because the underlying
well-defined? graph G is acyclic!
 Semantics of circuits (3/3)
• Then (FC,a(y1), …, FC,a(ym)) is the output valuation of
the circuit under the input valuation a = (a1, …, an).
• The computation of FC,a under the input valuation a
is called simulation of C under valuation a.

Circuits System Architecture, Jan Reineke 25

 Example: Simulation

a= 1 0 0 0 0 0 0 0

g1 g2 g3
0 0 0

g4 g5 g6
0 0 0
g7 g8

1 0

Circuits System Architecture, Jan Reineke 26

 Which Boolean function does a
circuit compute?
Definition:
The function computed at a node v
y(v) : Bn → B
is defined as
y(v)(a) := FC,a(v)
for an arbitrary a ∊ Bn.

Definition:
The function computed by circuit C is
fC := (y(y1), ..., y(ym))
Circuits System Architecture, Jan Reineke 27
 Symbolic simulation
• Symbolic simulation does not simulate a circuit for fixed
Boolean inputs. Rather it simulates the circuit on
Boolean variables.

• In this way it determines the Boolean expression

representing the Boolean function computed by a circuit

Circuits System Architecture, Jan Reineke 28

 Example: Symbolic simulation

x1 x2 x3 x4 x5 x6 x7 x8

x2⊗ x3 x4 ∧ x5 x6 ∨ x7

(x2 ⊗ x3) ⊗ (x4 ∧ x5)

x8’ ∧ x4 ∧ x5 x8 ∧ (x6 ∨ x7)

x1 ∨ (x2 ⊗ x3) ⊗ (x4 ∧ x5) (x8’ ∧ x4 ∧ x5) ∨

(x8 ∧ (x6 ∨ x7))

Circuits System Architecture, Jan Reineke 29

 Brainstorming: Cost and Speed

What are reasonable measures of

(a) Cost and
(b) Speed x x x
1 2x x 3 4 5 x6 x7 x8

of circuits?

y1 y2
Circuits 30
 Cost of circuits

Definition (Cost):
The hardware cost C(C) of a circuit C is its
number of gates|I| = |V \ ({0, 1} ∪ (x1, ..., xn))|.

Remark:
• Circuits are defined based on a cell library BIB
à Cost depends on the choice of the library.
• If not stated otherwise, in the following we will use the
standard library STD:
STD := {NOT, AND, OR, EXOR, NAND, NOR}
Circuits 31
 Speed of a circuit
Definition (Depth):
The depth(C) of a circuit C is the
maximal number of gates on a path from an
arbitrary input xi to an arbitrary output yj of C.

Remark:
• Depth is only a reasonable indicators of a circuit’s
speed if the switching speed of each gate in the library
is approximately the same.

Circuits System Architecture, Jan Reineke 32

 Example: Cost and depth of circuits

x1 x2 x3 x4 x5 x6 x7 x8

Cost: 8

Depth: 3

y1 y2

Circuits System Architecture, Jan Reineke 33

 Hierarchical circuits

In hierarchical circuits,
subcircuits are represented by symbols.

The corresponding (“flat”) circuit is obtained by

replacing the symbols by their defining subcircuits.

Circuits System Architecture, Jan Reineke 34

 Example Hierarchical circuits

x1 EXOR
x2
EXOR

x3

x1
x2 EXOR

EXOR
x3
Circuits 35
 Circuits vs Boolean functions

Every circuit computes a Boolean function.

But can every Boolean function be computed by

a circuit?

Circuits System Architecture, Jan Reineke 36

 Circuits vs Boolean functions

Theorem:
Let f Î Bn,m.
Then there is a circuit that computes f.

Reminder:
Lemma:
For every Boolean function f Î Bn,1 there
is a Boolean expression that describes f.
Circuits System Architecture, Jan Reineke 37
 Circuits vs Boolean expressions

Lemma:
For every Boolean expression e Î BE(Xn)
there is a circuit C = (Xn, G, typ, IN, Ym),
such that y(e) = fC.

Proof:
By induction over the structure of the Boolean expression.

Circuits System Architecture, Jan Reineke 38

 Recapitulation: Boolean expressions
Definition:
The set BE(Xn) of fully parenthesized Boolean
expressions over Xn is the smallest subset of A*,
inductively defined as follows:
• The elements 0 and 1 are Boolean expressions
• The variables x1, ..., xn are Boolean expressions
• Let g and h be Boolean expressions. Then so is
their Disjunction (g + h),
their Conjunction (g × h),
and their Negation (~g).

Circuits System Architecture, Jan Reineke 39

 Circuits vs Boolean functions

Theorem:
Let f Î Bn,m.
Then there is a circuit that computes f.
Proof:
Case 1: f Î Bn= Bn,1. $e Î BE(Xn), that computes f.
The theorem then directly follows from the previous lemma.

Case 2: f Î Bn,m, m ≥ 2.
Interpret f : Bn,m = Bn ® Bm as a sequence of functions (f1, ..., fm) with fi : Bn® B.

Construct a circuit for each fi.

Compose the circuits (see the following illustration).

Circuits 40
 Construction of a circuit for a Boolean
function from Bn,m.

x1 x2 ... xn

... ...
C1 C2 .... Cm

f1 f2 ... fm

Circuits System Architecture, Jan Reineke 41

 Example: Generalized EXOR
Given:
Function exor16 ∊ B16 with
!"

𝑒𝑥𝑜𝑟!" 𝑥! , … , 𝑥!" = , 𝑥# mod 2 = 1 if number of xi with xi = 1 is odd

#$!

Wanted:
Circuit implementation for exor16.

Assumption: exor2 is an element of our cell library.

Observations:
1. exor16 can be constructed from several ⊗ = exor2.
2. ⊗ is an associative operation!

Circuits System Architecture, Jan Reineke 42

 Generalized EXOR

Implementation of exor4:
x1 x2 x3 x4

Depth: 3
Cost: 3

Can we do better?
(((𝑥1 ⊗ 𝑥2) ⊗ 𝑥3) ⊗ 𝑥4) Idea: Make use of associativity:
𝑥1 ⊗ 𝑥2 ⊗ 𝑥3 ⊗ 𝑥4 = ((𝑥1 ⊗ 𝑥2) ⊗ (𝑥3 ⊗ 𝑥4))

Circuits System Architecture, Jan Reineke 43

 Generalized EXOR

Better implementation of exor4:

x1 x2 x3 x4

Depth: 2
Cost: 3

((𝑥1 ⊗ 𝑥2) ⊗ (𝑥3 ⊗ 𝑥4))

Circuits System Architecture, Jan Reineke 44

 Generalized EXOR

Better implementation of exor8:

x1 x2 x3 x4 x5 x6 x7 x8

Depth: 3
Cost: 7

(((𝑥1 ⊗ 𝑥2) ⊗ (𝑥3 ⊗ 𝑥4)) ⊗ (((𝑥5 ⊗ 𝑥6) ⊗ (𝑥7 ⊗ 𝑥8))

Circuits System Architecture, Jan Reineke 45

 Generalized EXOR

Better implementation of exor16:

x1x2 x3 x4 x5x6 x7x8 x9x10 x11x12 x13x14 x15x16

Depth: 4
Cost: 15

Circuits
How do cost and depth depend on n for exorn? 46
 Recursive construction of
generalized EXOR
Implementation of exor2n:
x1 … xn xn+1 … x2n
… … depth(exor2n) = depth(exorn)+1
Exorn Exorn depth(exor1) = 0
→ depth(exorn) = log2 n

C(exor2n) = 2·C(exorn)+1
C(exor1) = 0
→ C(exorn) = n-1

Circuits 47
 Efficient implementation of
arbitrary associative operations
Lemma:
The function x1 ◦ x2 … ◦ xn can be implemented
using ◦ gates with 2 inputs in a circuit of
depth ⌈log2 n⌉.

Proof by induction over n.

Circuits 48
 Two-level normal form of EXOR16
Question: How large is the smallest Boolean
polynomial of exor16?
Answer: 215 monomials with 16 literals each!

Question: How large it the smallest Boolean

polynomial for exorn?
Answer : 2n-1 monomials with n literals each!
Exponentially higher cost than
Circuits
the multi-level implementation! 49
 Cost of the implementation of
Boolean expressions via circuits
Define the cost C(E) of a Boolean expression E to
be the number of operations in the expression.
Theorem:
For every Boolean expression e Î BE(Xn)
there is a circuit C = (Xn, G, typ, IN, Ym),
such that y(e) = fC and C(C) ≤ C(E).
Follows from proof of earlier lemma.

Reusing subcircuits can sometimes help reduce

the cost.
Circuits System Architecture, Jan Reineke 50
Cost of the implementation of
Boolean functions via circuits
Theorem:
For every f Î Bn there is a circuit C implementing f,
s.t. C(C) ≤ n2n+1-1 and depth(C) ≤ n+ ⌈ log2 n ⌉ +1.

Proof sketch:
(Cost:) A function f Î Bn has at most 2n minterms.
Every minterm can be implemented using 2n-1 gates.
The disjunction of all minterms can be implemented using
at most 2n-1 gates.

(Depth:) Every minterm can be implemented in depth ⌈log2 n⌉+1.

The disjunction can be implemented in depth n (= log2 2n). 51
 Summary

Circuits implement arbitrary

Boolean functions from Bn,m.

Optimal Boolean polynomials can be much

larger than corresponding multi-level circuits:
exponential differences are possible!

Circuits System Architecture, Jan Reineke 53

 Outlook

There are algorithms to compute

optimal multi-level circuits
• harder than computing minimal polynomials
• mostly heuristics, i.e., not guaranteed to be optimal
• not covered in this course
• Here: Circuits for special functions,
in particular arithmetic

Circuits System Architecture, Jan Reineke 54