Name : _________________ Date : _________

Course : ________________ Grade: ________

Laboratory Experiment #3
TRANSISTOR DIGITAL LOGIC GATES

Performance Objectives
A. Identify and demonstrate the operation of a transistor digital logic NAND gate,
and develop a truth table of logic functions.
B. Identify and demonstrate the operation of a transistor digital logic NOR gate, and
develop a truth table of logic functions.

Theory
Basic Concepts
1. NAND means NOT AND.
2. NOR means NOT OR.
3. A NAND function can be performed using an AND gate and inverter.
4. A NOR function can be performed using an OR gate and inverter.
5. An amplifier used specifically to invert the logic signal is referred to as a NOT
circuit.

Introductory Information

NAND and NOR gates are two more logic gates used in digital circuits. NAND is an
abbreviation for NOT AND, and NOR stands for NOT OR. The purpose of a NAND gate
is to provide an output that logically represents NOT AND when all input gates
conditions are satisfied. In like manner, a NOR gate provides an output that logically
represents NOT OR when one or all input gate conditions are satisfied. More simply,
NAND and NOR gates are like AND and OR gates except their outputs are inverted
(logic states reversed) and are NOT the normal AND or OR outputs. This can be
accomplished electrically by applying the normal output of an AND or OR gate to a
transistor inverter stage, which inverts the signal and performs a NOT function.
Figure 3.1 shows two typical circuits used for performing the NAND and NOR functions.
In (a) the output of AND gate CR1, CR2 and R1 is used to drive the base of common
emitter amplifier Q1. Transistor Q1 is a NOT circuit because, if you will recall, the output
of common emitter amplifier is 180 degrees out of phase with, or goes in the opposite
direction from, the input. Thus (a) is a NAND gate. The inputs are applied to A and B of
the AND gate and the output C is taken from the collector of the NOT circuit Q1. When
+5Vdc is applied to both inputs A and B diodes CR1 and CR2 are reverse biased and
the +5Vdc supply voltage appears at their common anode connection. This +5Vdc
serves as forward bias for Q1 causing it to conduct. The output at C is very close to
zero volts in this case and represents the inverse of inputs A and B, the logic equation
for the NAND function is C= A and B small horizontal bar (-) is placed over the inverted
signal or term to indicate inversion. The logic symbol for a NAND gate is the same as
for an AND gate except that a small circle appears at the output to indicate inversion.
The NOR gate is shown in (b) of Figure 3.1. The output of OR gate CR1, CR2 and R1 is
used to drive the base of common emitter amplifier Q1. Again, Q1 is used as a NOT
circuit. The inputs are applied to A and B of the OR gate and the output C is taken from
the collector of NOT circuit Q1. Then +5Vdc is applied to either or both inputs A or B,
diodes CR1 and CR2 are forward biased and conduct. A +5Vdc drop is produced
across R1, forward biasing Q1 and causing it to conduct. The output of C is close to
zero volts and represents the inverse of inputs A or B. The logic equation for the OR
function is C = A OR B. the logic symbol is the same as for an OR gate except a small
circle is used at the output to show inversion.

Figure 3.1

Equipment And Materials

Power Source (5Vdc)
Electronic VOM
Digital Logic Trainer
Jumper wires
CR1 - CR3 - Silicon Diode, 1N4004 (3 pcs)
Q1 - NPN Transistor, 2N2219A or 2N222A (2 pcs)
R1 - 1kΩ, 1W
R2, R3 - 4.7kΩ, 1W
S1 - SPDT, Component Module
 S2 - DPDT, Component Module
LED - LED Module

Procedure

Objective A. Identify and demonstrate the operation of a transistor digital logic NAND
gate, and develop a truth table of logic functions.
□ 1. a) Examine the circuit shown in Figure 3.2. This is essentially the same circuit
shown in Figure 3.1
(a) with the addition of switches S1 and S2, diode CR3 and the oscilloscope. S1 and S2
are used to change the gate conditions of inputs A and B. Note that the 0 position of S1
and S2 represents 0 volts and the 1 position represents +5 volts. Diode CR3 insures
that Q1 cuts off. The oscilloscope is used to monitor the output voltage at C for the
various gating conditions. What identifies this circuit as a transistor digital logic NAND
gate?
if both inputs are hign the NAND gate will resul to a low output
______________________________________________________________________
______________________________________________________________________

Diodes CR1 and CR2 and resistor R1 form an AND gate and transistor Q1 performs a
NOT function. Inspection of the circuit shows that it will provide a zero volt output only
when both inputs are +5Vdc. This satisfies the logic equation for a NAND gate (C = A
AND B).

Figure 3.2

□ b) Connect the circuit as shown in Figure 3.2.

□ c) Adjust the power supply voltage to 5Vdc
□ d) Set switches S1 and S2 to the 0 position. Record in Table 3.1 the output voltage
monitored on the VOM.
□ e) Set S1 and S2 to each combination of positions listed in Table 3.1 and record the
output voltage for each combination.
□ f) Look at the results of Table 3.1.
 S1 S2 OUTPUT
POSITION POSITION VOLTAGE (Vdc)
0 0 6.01V
0 1 6.01V
1 0
6.01V
1 1 0.053V

Table 28-1

Which combinations of switch settings resulted in an output voltage approximately equal

to the 5Vdc supply voltage?
position 00, 01, 10
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______________________________________________________________________

Is the output voltage close to zero volts for the remaining switch combinations?
______________________________________________________________________
yes

Expected Output: The output voltage is approximately five volts when either or both S1
or S2 are set to the 0 position. The output voltage is close to zero volts when both S1
and S2 are set to the 1 position.

□ g) Assume zero volts represents logic state 0 and +5 volts represents logic state 1 in
your circuit. Write the logic equation for the transistor digital logic NAND gate from the
results of Table 3.1. Remember, a NAND gate provides the logic state from the AND
when all input gating conditions are satisfied simultaneously. Use A and B as the inputs,
and C as the output.

Your logic equation should be A AND B = C.

□ h) Reduce the power supply voltage to zero.
□ 2.a) Now you will verify your logic equation using a light emitting diode (LED) as a
digital logic readout. Connect the circuit shown in Figure 3.3. All components associated
with LED CR4 are permanently mounted on the Component Module. These
components include diver transistor Q2 and current limiting resistors R3 and R4.

Figure 3.3
□ b) Adjust the power supply voltage to 5Vdc.
□ c) Repeat the switch settings of Table 3.1. The LED will go out when driver transistor
Q2 is reverse biased by the zero volt output of the NAND gate. This should occur only
when the input gate conditions are satisfied.

□ d) Which combination of switch settings cause the LED to go out?

position 11
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Does this verify the NAND gate logic equation C = A AND B?

____________________________________________________________________
no

The LED should go out only when both S1 and S2 are in the 1 position, verifying the
logic equation.
□ e) Refer to Table 3.2. Assume the 0 and 1 positions of S1 and S2 represent logic 0
and logic, respectively, and that a logic 0 is indicated when the LED is off and a logic 1
is obtained when the LED is on. Complete the truth table for your transistor digital logic
NAND gate for the various input to conditions listed. If necessary, use the test circuit to
assist you or to confirm your results.

Your truth table will be identical to Table 3.1, except the zero voltage level will be logic 0
and the five volt levels will be logic1.

INPUT OUTPUT
A B C
0 0 1
0 1 1
1 0 1
1 1 0
Table 3.2

f) Reduce the power supply voltage to zero.

Objective B. identify and demonstrate the operation of a transistor digital logic NOR
gate, and develop a truth table of logic functions.
3. a) examine the circuit shown in Figure 3.4. This is essentially the same circuit shown
in Figure 3.1
(b) With the addition of S1 and S2 and the VOM. S1 and S2 and the VOM ---- for the
same purpose as in Procedures 1 and 2. Resistor R3 is a base current limiting resistor
or Q1. What identifies this circuit as a transistor digital logic NOR gate?
______________________________________________________________________
NOR gate produces a high output only when both inputs are low.
______________________________________________________________________

Inspection of the circuit shows that it will provide a zero volt output when either or both
inputs are +5Vdc, satisfying the logic equation for a NOR gate (C = A OR B). the diodes
and resistor comprise an OR gate, and transistor q1 is a NOT circuit, which together
form a NOR circuit.
 Figure 3.4

□ b) Connect the circuit as shown inFigure 3.4

□ c) Adjust the power supply voltage to 5Vdc.
□ d) Set S1 and S2 to the 0 position. Record in Table 3.3 the output voltage indicated
on the VOM

S1 S2 OUTPUT
POSITION POSITION VOLTAGE (Vdc)
0 0 6V

0 1 0.18V
1 0 0.19V
1 1 0.18V

Table 3.3

□ e) Set S1 and S2 to each combination of switch positions listed in Table 3.3. Record
the output voltage for each combination.
□ f) Look at the results of the Table 3.3. Which combination of switch settings resulted
in an output voltage approximately equal to the 5Vdc supply voltage?
Is the output voltage zero for the remaining switch combinations?

Expected output: The output voltage should be approximately five volts when both S1
and S2 are set to the 0 position.The output voltage will be zero when either or both
switches are set to the 1 position.

□ g) From the results of your measurements, write the logic equation for the transistor
digital logic NOR gate. Assume zero volts is logic 0 and +volts is logic 1. Remember, a
NOR gate provides an inverted OR output when a logic 1 occurs on any or all input
terminals. Use A and B as the inputs, and C as the output.
A OR B = C
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______________________________________________________________________
Your logic equation should be A OR B = C.
□ h) Reduce the power supply voltage to zero.
□ 4. a) Now you will verify your logic equation using the LED as a readout. Connect the
circuit shown in Figure 3.5

Figure 3.5

□ b) Adjust the power supply voltage t 5Vdc.

□ c) Repeat the switch settings of Table 3.3. The LED will go out when the input gate
conditions satisfy the logic equation.
□ d) Which combinations of switch setting cause the LED to go out?
0,0 0,1 1,0
______________________________________________________________________

Does this verify the NOR gate logic equation C = A OR B?

NO
______________________________________________________________________

The LED will go out when either or both S1 or S2 are in the 1 position, verifying the logic
equation.
□ e) Refer to Table 3.4. Complete the truth table of logic functions for the transistor
digital logic NOR gate. Confirm your results using the test circuit if necessary.

Expected Output : The truth table should indicate a logic 0 output for a logic 1 on either
or both A and B inputs. The only time a logic 1 output is obtained is when both A and B
are logic 0.
□ f) Reduce the power supply voltage to zero.

INPUT OUTPUT
A B C
0 0 1
0 1 0
1 0 0

1 1 0

Table 3.4
Checked by

________________________________
(Printed name and Signature of Instructor)

Date Checked : __________________