. Digital Logic Design .

Addis Ababa University

ADDIS ABABA INSTITUTE OF TECHNOLOGY
SCHOOL OF INFORMATION TECHNOLOGY AND
ENGINEERING
Department of Software Engineering

Digital Logic Design Assignment

PREPARED BY: -
1) Thomas Habtamu ID ATE/1375/12
2) Yonas Buzuayehu ID ATE/6357/12
3) Sefesilasse Hailu Ejigu ID ATE/7785/12
4) Tafese Gechera ID ATE/7404/12
5) Tamrat Demek mulat ID ATE/9737/12
6) Minasie Simon IDATE/0818/12

Submitted to: Mr. Aderaw

Date: May 2023

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Digital Sistem And Binary System
 Digital:- Concerned with the interconnection among digital components and modules
 Best Digital System example is General Purpose Computer
 Logic Design:-Deals with the basic concepts and tools used to design digital hardware consisting of logic
circuits
 Circuits to perform arithmetic operations (+, -, x, ÷)
 Digital Signal: Decimal values are difficult to represent in electrical systems. It is easier to use two
voltage values than ten.
 Digital Signals have two basic states:
1 (logic “high”, or H, or “on”)
0 (logic “low”, or L, or “off”)
 Digital values are in a binary format. Binary means 2 states.
 A good example of binary is a light (only on or off)
Binary Numbers Systems
 An information variable represented by physical quantity. V(t)

 For digital systems, the variable takes on discrete values.

 Two level, or binary values are the most prevalent values. Logic 1

 Binary values are represented abstractly by:

undefine
 Digits 0 and 1
 Words (symbols) False (F) and True (T) Logic 0 t
 Words (symbols) Low (L) and High (H)
 And words On and Off Binary Digital Signal

 Binary values are represented by values or ranges of values of physical quantities.

Decimal Number System
 Base (also called radix) = 10 :-10 digits { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }
 Digit Position: Integer & fraction
 Digit Weight:-Weight = (Base) Position
 Magnitude:-Sum of “Digit x Weight”
 Formal Notation
Octal Number System
 Base = 8:- 8 digits { 0, 1, 2, 3, 4, 5, 6, 7 }

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 Weights:-Weight = (Base) Position
 Magnitude Sum of “Digit x Weight”
 Formal Notation
Binary Number System
 Base = 2 :- 2 digits { 0, 1 }, called binary digits or “bits”
 Weights:-Weight = (Base) Position
 Magnitude:- Sum of “Bit x Weight”
 Formal Notation:- Groups of bits 4 bits = Nibble 8 bits = Byte

Hexadecimal Number System

 Base = 16 :- 16 digits { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F }
 Weights:- Weight = (Base) Position
 Magnitude:- Sum of “Digit x Weight”
 Formal Notation

Addition: Decimal Addition 1 1 Carry

5 5
+ 5 5
1 1 0 = Ten >= Base Subtract a base
Binary Addition
Column Addition
1 1 1 1 1 1
1 1 1 1 1 1 =63
+ 1 0 1 1 1 =23
1 0 1 0 1 0 0 =84
Binary Subtraction:- Borrow a “Base” when needed
1 2
0 2 2 0 0 2 =(10)2
1 0 0 1 1 0 1 =77
- 1 0 1 1 1 =23
0 1 1 0 1 1 0 =54
Binary Multiplication
Bit By bit 1 0 1 1 1
X 1 0 1 0
0 0 0 0 0
1 0 1 1 1
0 0 0 0 0
1 0 1 1 1

1 1 1 0 0 1 1 0
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Number Base Conversions
Evaluate Magnitude
Octal
(Base 8)

Evaluate Magnitude
Decimal
(Base 10) Binary
(Base 2)

Evaluate Magnitude
Hexadecimal
(Base 16)
Decimal (integer) to Binary Conversion
 Divide the number by the ‘Base’ (=2)
 Take the remainder (either 0 or 1) as a coefficient
 Take the quotient and repeat the division
Example: (13)10 Quotient Reminder Coefficient
13/2 = 6 1 a0=1
6/2= 3 0 a1=1
3/2= 1 1 a2=1
½= 0 1 a3=1
Ans: (13)10 = (a3 a2 a1 a0)2 =(1101)2
Decimal (Fraction) to Binary Conversion
 Multiply the number by the ‘Base’ (=2)
 Take the integer (either 0 or 1) as a coefficient
 Take the result fraction and repeat the division
Example: (0.625)10 Integer Fraction Coefficient
0.625 *2= 1 .25 a-1=1
0.25 *2= 0 .5 a-2=0
0.5 *2= 1 0 a-3=1
Ans: (0625)10 =(0. a-1a-2 a-3)2 = (0.101)2
Decimal to Octal Conversion
Example1: (175)10 Quotient Remainder Coefficient
175/8 = 21 7 a0=7
21/8 = 2 5 a1=1
2/8 = 0 2 a2=2
Example2: (0.3125)10 Integer Fraction Coefficient
03125 *8= 2 .5 a-1=2
0.5 *8= 4 .0 a-2=4
Ans: (0.3125)10 = (0. a-1a-2 a-3) = (0.24)8

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Binary- Octal Conversion
8 = 23
Each Group of 3 bits represents an octal digit
Example: (10110.01)2 to (26.2)8
Binary-Hexadecimal Conversion
16 =24
Each Group of 4 bits represents a hexadecimal digit
Example: (10110.01)2 to (16.4)16

Complements
 There are two types of complements for each base-r system: the radix complement and diminished
radix complement.
 Diminished Radix Complement - (r-1)’s Complement
o Given a number N in base r having n digits, the (r–1)’s complement of N is defined as:
(rn –1) – N
 Example for 6-digit decimal numbers:
 9’s complement is (rn – 1)–N = (106–1)–N = 999999–N
 9’s complement of 546700 is 999999–546700 = 453299
 Example for 7-digit binary numbers:
 1’s complement is (rn – 1) – N = (27–1)–N = 1111111–N
 1’s complement of 1011000 is 1111111–1011000 = 0100111
 Observation:
 Subtraction from (rn – 1) will never require a borrow
 Diminished radix complement can be computed digit-by-digit
 For binary: 1 – 0 = 1 and 1 – 1 = 0
 1’s Complement (Diminished Radix Complement)
 All ‘0’s become ‘1’s
 All ‘1’s become ‘0’s
Example (10110000)2
 (01001111)2
If you add a number and its 1’s complement …
10110000
+ 01001111
11111111
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 Radix Complement
The r's complement of an n-digit number N in base r is defined as
rn – N for N ≠ 0 and as 0 for N = 0. Comparing with the (r  1) 's complement, we note that the r's
complement is obtained by adding 1 to the (r  1) 's complement, since rn – N = [(rn  1) – N] + 1.
Example: Base -10
The 10's complement of 012398 is 987602
The 10's complement of 246700 is 753300
Example: Base -2
The 2's complement of 1101100 is 0010100
The 2's complement of 0110111 is 1001001
 2’s Complement (Radix Complement)
– Take 1’s complement then add 1
– Toggle all bits to the left of the first ‘1’ from the right
Example:
Number: 10110000
1’s Comp.: 01001111
+ 1
01010000
 Subtraction of unsigned numbers can also be done by means of the (r  1)'s complement. Remember that the (r
 1) 's complement is one less then the r's complement.
 Example :

Signed Binary Numbers

 To represent negative integers, we need a notation for negative values.
 It is customary to represent the sign with a bit placed in the leftmost position of the number since
binary digits.
 The convention is to make the sign bit 0 for positive and 1 for negative.
Example:

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Signed Binary Numbers
Decimal Signed -2’s Signed -1’s Signed
Complement Complement Magnitude
+7 0111 0111 0111
+6 0110 0110 0110
+5 0101 0101 0101
+4 0100 0100 0100
+3 0011 0011 0011
+2 0010 0010 0010
+1 0001 0001 0001
+0 0000 0000 0000
-0 - 1111 1000
-1 1111 1110 1001
-2 1110 1101 1010
-3 1101 1100 1011
-4 1100 1011 1100
-5 1011 1010 1101
-6 1010 1001 1110
-7 1001 1000 1111
Binary Cods -8 1000 - -
Digital data is represented, stored and transmitted as groups of binary digits also known as binary code.
 Weighted codes: In weighted codes, each digit is assigned a specific weight according to its position.
 Non-weighted codes: In non-weighted codes are not appositionally weighted.
 Reflective codes: A code is reflective when the code is self-complementing. In other words, when the code
for 9 is the complement the code for 0, 8 for 1, 7 for 2, 6 for 3 and 5 for 4.
 Sequential codes: In sequential codes, each succeeding 'code is one binary number greater than its preceding
code.
 Alphanumeric codes: Codes used to represent numbers, alphabetic characters, symbols
 Error defecting and correcting codes: Codes which allow error detection and correction are called error
detecting and' correcting codes.
BCD Code
 A number with k decimal digits will require 4k bits in BCD.
 Decimal 396 is represented in BCD with 12bits as 0011 1001 0110, with each group of 4 bits
representing one decimal digit.
 A decimal number in BCD is the same as its equivalent binary number only when the number is
between 0 and 9.
 The binary combinations 1010 through 1111 are not used and have no meaning in BCD.
Example: Consider decimal 185 and its corresponding value in BCD and binary:
(185)10 = (0001 1000 0101)BCD = (10111001)2

BCD Addition

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Gray Code
– The advantage is that only bit in the code group changes in going from one number to the next.
• Error detection.
• Representation of analog data.
• Low power design.

ASCII Character codes and Properties

 American Standard Code for Information Interchange (Refer to Table 1.7)
 A popular code used to represent information sent as character-based data.
 It uses 7-bits to represent:
– 94 Graphic printing characters.
– 34 Non-printing characters.
 Some non-printing characters are used for text format (e.g. BS = Backspace, CR = carriage return).
 Other non-printing characters are used for record marking and flow control (e.g. STX and ETX start
and end text areas).
 ASCII has some interesting properties:
– Digits 0 to 9 span Hexadecimal values 3016 to 3916
– Upper case A-Z span 4116 to 5A16
– Lower case a-z span 6116 to 7A16
Lower to upper case translation (and vice versa) occurs by flipping bit 6.
Error-Detecting Code
– To detect errors in data communication and processing, an eighth bit is sometimes added to the ASCII
character to indicate its parity.
– A parity bit is an extra bit included with a message to make the total number of 1's either even or odd.
Example: Consider the following two characters and their even and odd parity:
With even parity with odd parity
ASCIIA = 1000001 = 65 01000001 11000001
ASCII T= 1010100 = 82
[
11010100 01010100

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– Redundancy (e.g. extra information), in the form of extra bits, can be incorporated into binary code words to
detect and correct errors.
– A simple form of redundancy is parity, an extra bit appended onto the code word to make the number of 1’s
odd or even. Parity can detect all single-bit errors and some multiple-bit errors.
– A code word has even parity if the number of 1’s in the code word is even.
– A code word has odd parity if the number of 1’s in the code word is odd.
Example: Message A: 10001001 1 (even parity)
Message B: 10001001 0 (odd parity)
Binary Storage and Registers
 Registers
 A binary cell is a device that possesses two stable states and is capable of storing one of the two
states.
 A register is a group of binary cells. A register with n cells can store any discrete quantity of
information that contains n bits.
 A binary cell n cells 2n possible states
 Two stable state
 Store one bit of information
 Examples: flip-flop circuits, ferrite cores, capacitor
 A register
– A group of binary cells
– AX in x86 CPU
 Register Transfer
– A transfer of the information stored in one register to another.
– One of the major operations in digital system.
– An example in next slides.
A Digital Computer Example

Input: Keyboard, Output:

Mouse, Modem, CRT, LCD, Modem,
Microphone Speakers
Synchronous or
Asynchronous?

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Transfer of information

 The other major component of a digital system

– Circuit elements to manipulate individual bits of information
– Load-store machine
LD R1;
LD R2;
ADD R3, R2, R1;
SD R3;

Binary Logic
– Binary logic consists of binary variables and a set of logical operations.
– The variables are designated by letters of the alphabet, such as A, B, C, x, y, z, etc, with each variable having
two and only two distinct possible values: 1 and 0,
– Three basic logical operations: AND, OR, and NOT.
1. AND: This Operation is represented by a dot or by the absence of an operator. Ex: x . y = z or xy =z is read “x
AND y is equal to z”, The logical operation AND is interpreted to mean that z = 1 if only x = 1 and y = 1;
otherwise z = 0. (Note: x,y and z are binary variables and can be equal either to 1 or 0, and nothing else.)
2. OR: This operation is represented by a plua sign. Example, x + y = z is read “x Or y is equal to z”, meaning
that z= 1 if x = 1 or y =1 or if both x =1 and y = 1. If both x = 0 and y = 0, then z = 0.
3. NOT: This operation is represented by a prime (sometimes by an overbar). Example: x’ = z (or x = z) is read
‘not x is equal to z’, meaning that z is what z is not.
Truth tables, Boolean expresions and logic gets
AND OR NOT

z=x•y=xy z=x+y z = x = x’
x x z
y z y x z
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Universal Gate
 NAND and NOR Gates are called Universal Gates because AND, OR and NOT gates can be implemented
&created by using these gates.
NAND Gate Implementations NOR Gate Implementations

Binary Logic
Logic gates

Graphic Symbols and Input-Output Signals for Logic

Boolean Algebra
Boolean Algebra: George Boole(English mathematician), 1854
 Invented by George Boole in 1854
 An algebraic structure defined by a set B = {0, 1}, together with two binary operators (+ and ·) and a unary
operator ( )
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“An Investigation of the Laws of Thought, on Which Are Founded the Mathematical Theories of Logic and
Probabilities”
Boolean algebra
{(1,0), Var, (NOT, AND, OR), Thms}
 Mathematical tool to expression and analyze digital (logic) circuits
 Clude Shannon, the first to apply Boole’s work, 1938
– “A Symbolic Analysis of Relay and Switching Circuits” at MIT
Basic Functions
Boolean functions: NOT, AND, OR,
Exclusive OR(XOR) : odd function exclusive NOR(XNOR) : even function(equivalence)

Basic functions
 AND Z=X  Y or Z=XY
Z=1 if and only if X=1 and Y=1, otherwise Z=0
 OR Z=X + Y
Z=1 if X=1 or if Y=1, or both X=1and Y=1. Z=0 if and only if X=0 and Y=0
 NOT Z=X or
Z=1 if X=0, Z=0 if X=1

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Boolean Operations and Expressions
Boolean Addition
– Logical OR operation
Ex 4-1) Determine the values of A, B, C, and D that make the sum term A+B’+C+D’
Sol) all literals must be ‘0’ for the sum term to be ‘0’
A+B’+C+D’=0+1’+0+1’=0 A=0, B=1, C=0, and D=1
Boolean Multiplication
– Logical AND operation
Ex 4-2) Determine the values of A, B, C, and D for AB’CD’=1
Sol) all literals must be ‘1’ for the product term to be ‘1’
AB’CD’=10’10’=1 A=1, B=0, C=1, and D=0

Laws of Boolean Algebra

Commutative Law: the order of literals does not matter
A+B=B+A AB = BA

Associative Law: the grouping of literals does not matter

A + (B + C) = (A + B) + C =A+B+C) A(BC) = (AB)C =ABC)

 Distributive Law : A(B + C) = AB + AC (A+B)(C+D) = AC + AD + BC + BD

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Rules of Boolean Algebra
 A+0=A In math if you add 0 you have changed nothing in Boolean Algebra ORing with 0 changes nothing
 A•0=0 In math if 0 is multiplied with anything you get 0. If you AND anything with 0 you get 0
 A•1 =A ANDing anything with 1 will yield the anything
 A+A = A ORing with itself will give the same result
 A+A’=1 Either A or A’ must be 1 so A + A’ =1
 A•A = A ANDing with itself will give the same result
 A•A’ =0 In digital Logic 1’ =0 and 0’ =1, so AA’=0 since one of the inputs must be 0.
 A = (A’)’ If you not something twice you are back to the beginning
 A + A’B = A + B
If A is 1 the output is 1 If A is 0 the output is B
 A + AB = A
 (A + B)(A + C) = A + BC
DeMorgan’s Theorem
F(A,A, , + , 1,0) = F(A, A, + , ,0,1)
(A • B)’ = A’ + B’ and (A + B)’ = A’ • B’
DeMorgan’s theorem will help to simplify digital circuits using NORs and NANDs his theorem states

Boolean Analysis of Logic Circuits

Constructing a Truth Table for a Logic Circuit
– Convert the expression into the min-terms containing all the input literals
– Get the numbers from the min-terms
– Putting ‘1’s in the rows corresponding to the min-terms and ‘0’s in the remains
Ex) A(B+CD)=AB(C+C’) (D+D’) +A(B+B’)CD =ABC(D+D’) +ABC’(D+D’) +ABCD+AB’CD
=ABCD+ABCD’+ABC’D+ABC’D’ +ABCD+AB’CD =ABCD+ABCD’+ABC’D+ABC’D’ +AB’CD
=m11+m12+m13+m14+m15=(11,12,13,14,15)
A(B+CD) = m11+m12+m13+m14+m15 =(11,12,13,14,15)
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Standard Forms of Boolean Expressions
 The Sum-of-Products(SOP) Form Ex) AB+ABC, ABC+CDE+B’CD’
 The Product-of-Sums(POS) Form Ex) (A+B)(A+B+C), (A+B+C)(C+D+E)(B’+C+D’)
 Principle of Duality : SOP  POS
 Domain of a Boolean Expression : The set of variables contained in the expression
Ex) A’B+AB’C : the domain is {A, B, C}
 Standard SOP Form (Canonical SOP Form)
 For all the missing variables, apply (x+x’)=1 to the AND terms of the expression
 List all the min-terms in forms of the complete set of variables in ascending order
Ex : Convert the following expression into standard SOP form: AB’C+A’B’+ABC’D
Sol) domain={A,B,C,D}, AB’C(D’+D)+A’B’(C’+C)(D’+D)+ABC’D
=AB’CD’+AB’CD+A’B’C’D’+A’B’C’D+A’B’CD’+A’B’CD+ABC’D
=1010+1011+0000+0001+0010+0011+1101 =0+1+2+3+10+11+13 = (0,1,2,3,10,11,13)
Standard POS Form (Canonical POS Form)
– For all the missing variables, apply (x’x)=0 to the OR terms of the expression
– List all the max-terms in forms of the complete set of variables in ascending order
Ex : Convert the following expression into standard POS form: A+B’+C)(B’+C+D’)(A+B’+C’+D)
Sol) domain={A,B,C,D}, (A+B’+C)(B’+C+D’)(A+B’+C’+D)
=(A+B’+C+D’D)(A’A+B’+C+D’)(A+B’+C’+D)
=(A+B’+C+D’)(A+B’+C+D)(A’+B’+C+D’)(A+B’+C+D’)(A+B’+C’+D)=(0100) )(0101)(0110)(1101)= (4,5,6,13)

Converting Standard SOP to Standard POS

Step 1. Evaluate each product term in the SOP expression. Determine the binary numbers that represent the
product terms
Step 2. Determine all of the binary numbers not included in the evaluation in Step 1
Step 3. Write in equivalent sum term for each binary number Step 2 and expression in POS form
Ex: Convert the following SOP to POS
Sol) SOP= A’B’C’+A’BC’+A’BC+AB’C+ABC=0+2+3+5+7 =(0,2,3,5,7)
POS=(1)(4)(6) = (1, 4, 6) (=(A+B+C’)(A’+B+C)(A’+B’+C))

SOP and POS Observations

– Canonical Forms (Sum-of-minterms, Product-of-Maxterms), or other standard forms (SOP, POS) differ in complexity
– Boolean algebra can be used to manipulate equations into simpler forms
– Simpler equations lead to simpler implementations.

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Karnaugh Map:- Simplification methods
– Boolean algebra(algebraic method)
– Karnaugh map(map method))
– Quine-McCluskey(tabular method)
– Three- and Four-input Kanaugh maps XY+XY=X(Y+Y)=X

Karnaugh Map (K- Map) Steps

1. Sketch a Karnaugh map grid for the given problem.in power of 2N Squares
2. Fill in the 1’s and 0’s from the truth table of sop or pos Boolean function
3. Circle groups of 1’s.
 Circle the largest groups of 2, 4, 8, etc. first.
 Minimize the number of circles but make sure that every 1 is in a circle.
4. Write an equation using these circles.
Example) F(X,Y,Z)=m(0,2,4,6) = XZ+XZ  =Z(X+X)=Z

Four-Variable K-Map: 16 minterms : m0 ~ m15

Rectangle group
– 2-squares(minterms) : 3-literals product term
– 4-squares : 2-literals product term
– 8-squares : 1-literals product term
– 16-squares : logic 1

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F(W, X,Y,Z)=m(0,2,7,8,9,10,11) = WX’ + X’Z’ + W’XYZ

Ex: Minimize the following expression

AB’C+A’BC+A’B’C+A’B’C’+AB’C’
Sol: B’+A’C
Ex: Minimize the following expression
B’C’D’+A’BC’D’+ABC’D’+A’B’CD+AB’CD+A’B’CD’+A’BCD’ +ABCD’+AB’CD’
Sol) D’+B’C

Don’t Care Conditions

• it really does not matter since they will never occur(its output is either ‘0’ or ‘1’)
• The don’t care terms can be used to advantage on the Karnaugh map

Ex K- Map for POS (B+C+D)(A+B+C’+D)(A’+B+C+D’)(A+B’+C+D)(A’+B’+C+D)

Sol) (B+C+D) = (A’A+B+C+D) = (A’+B+C+D)(A+B+C+D)
(1+0+0+0)(0+0+0+0)(0+0+1+0)
(1+0+0+1)(0+1+0+0)(1+1+0+0)
F=(C+D)(A’+B+C)(A+B+D)

Converting Between POS and SOP Using the K-map

Ex ) (A’+B’+C+D)(A+B’+C+D)(A+B+C+D’)(A+B+C’+D’) (A’+B+C+D’)(A+B+C’+D)

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Quine-McCluskey - Tabular Method

 Step 1 − Arrange the given min terms in an ascending order and make the groups based on the number of ones
present in their binary representations. - ‘n+1’ groups
 Step 2 − Compare the min terms present in successive groups. If there is a change in only one-bit position,
then take the pair of those two min terms. Place this symbol ‘_’ in the differed bit position and keep the
remaining bits as it is.
 Step 3 − Repeat step2 with newly formed terms till we get all prime implicates.
 Step 4 − Formulate the prime implicate table. It consists of set of rows and columns. Place ‘1’ in the cells
corresponding to the min terms that are covered in each prime implicate.
 Step 5 − Find the essential prime implicates by observing each column. Those essential prime implicates will
be part of the simplified Boolean function.
 Step 6 − Reduce the prime implicate table by removing the row of each essential prime implicate and the
columns corresponding to the min terms that are covered in that essential prime implicate. Repeat step 5 for
Reduced prime implicate table. Stop this process when all min terms of given Boolean function are over.

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Digital Circuits: Digital circuits are two types

1. Combinational circuit consists of logic gates whose outputs at any time are determined directly from the
present combination of inputs without regard to previous inputs.
2. Sequential Circuit employ memory elements in addition to logic gates. Their outputs are a function of the
inputs and the state of the memory elements.
Combinational Logic
 Logic circuits for digital systems may be combinational or sequential.
 A combinational circuit consists of input variables, logic gates, and output variables.

 Hence, a combinational circuit can be described by:

 A truth table that lists the output values for each combination of the input variables, or
 m Boolean functions, one for each output variable.
Combinational vs. Sequential Circuits
 Combinational circuits are memory-less. Thus, the output value depends ONLY on the current input values.
 Sequential circuits consist of combinational logic as well as memory elements (used to store certain circuit
states). Outputs depend on BOTH current input values and previous input values (kept in the storage
elements).

Design Procedure
 Given a problem statement:
● Determine the number of inputs and outputs

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● Derive the truth table
● Simplify the Boolean expression for each output
● Produce the required circuit
Half Adder : A combinational circuit that performs the addition of two bits is called a half adder, We need
two input and outputs
x y C S

0 0 0 0

0 1 0 1

1 0 0 1
The truth table for the half adder is listed below 1 1 1 0

S(x,y) = x’y + xy’ C(x,y) = xy

Full Adder:
One that performs the addition of three bits (two significant bits and a previous carry) is a full adder.
yxz cs
000 00
001 01
010 01
011 10
100 01
101 10
110 10
111 11
S = x’y’z + x’yz’ + xy’z’ + xyz C = xy + xz + yz
 Alternative formulae using algebraic manipulation:
C = X.Y + X.Z + Y.Z
= X.Y + (X + Y).Z
= X.Y + ((X XOR Y) + X.Y).Z
= X.Y + (X XOR Y).Z + X.Y.Z
= X.Y + (X XOR Y).Z
S = X'.Y'.Z + X'.Y.Z' + X.Y'.Z' + X.Y.Z
= X‘. (Y'.Z + Y.Z') + X. (Y'.Z' + Y.Z)
= X'. (Y XOR Z) + X. (Y XOR Z)' Full adder using two half adder
= X XOR (Y XOR Z) or (X XOR Y) XOR Z

Parallel Binary Adders

 Parallel Adder is a digital circuit that produces the arithmetic sum of 2 binary numbers.
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 Constructed with full adders connected in cascade, with output carry from each full adder connected to the
input carry of next full adder in the chain.
 The carries are connected in a chain through the full adders.
 Two methods to handle carries in parallel adder
1. Ripple carry: carry out of each FA is connected to the carry input of next FA
2. Carry Look ahead: it anticipates the output carry of each stage, and based on the input bits of each stage,
produces the output carry by either carry generation or carry propagation.
Carry generation: output carry is produced internally by the FA.carry is generated only when both input bits
are 1s.the generated carry C is expressed as the AND function of two input bits A and B so C=AB.
Carry propagation: occurs when the i/p carry is rippled to become the o/p carry.an i/p carry may be propagated
by the full adder when either or both of the i/p bits are 1s.the propagated carry Cp is expressed as the OR
function of the i/p bits ie Cp=A+B
Bit Parallel Adder
LSB of two binary numbers are represented by A1 and B1.The next higher bit are A2 and B2. The resulting 1 2
and CO, in which the CO becomes MSB.
The carry output CO of each adder is connected as the carry input of the next higher order.

Four Bit Parallel Adders

• An n-bit adder requires n full adders with each output connected to the input carry of the next higher-order full
adder.
The carry output of each adder is connected to the carry input of next adder called as internal carries.

The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a Carry In (labeled C0) and a
Carry Out (labeled C4).

 74283 Four-bit binary adder

 7483 is an older chip that is functionally identical to the 74283, but the pins are laid out differently
Cascading Parallel Adders

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When we connect the outputs from one circuit to the inputs of another identical circuit to expand the number
of bits being operated on, we say that the circuits are cascaded together.
For example, you can cascade two 4-bit parallel adders to add two 8-bit numbers. To do this, connect the
lower-order adder’s Carry Out to the higher-order adder’s Carry In.

Binary Subtraction
• The subtraction A-B can be performed by taking the 2's complement of B and adding to A.
• The 2's complement of B can be obtained by complementing B and adding one to the result.
A-B = A + 2C(B) = A + 1C(B) + 1
= A + B’ + 1

Adder/Substractor
 Design requires:
(i) XOR gates:
(ii) S connected to carry-in.

• When S=0, the circuit performs A + B. The carry in is 0, and the XOR gates simply pass B untouched.
• When S=1, the carry into the least significant bit (LSB) is 1, and B is complemented (1’s complement) prior to the
addition; hence, the circuit adds to A the 1’s complement of B plus 1 (from the carry into the LSB).
Magnitude Comparator:
A magnitude comparator is a combinational circuit that compares two numbers, A and B, and then determines
their relative magnitudes.
A>B A=B A<B

Problem: Design a magnitude comparator that compares 2 4-bit numbers A and B and determines whether:
A > B, or A = B, or A < B
Inputs
First n-bit number A and Second n-bit number B
Outputs: 3 output signals (GT, EQ, LT), where: GT = 1 IFF A > B EQ = 1 IFF A = B LT = 1 IFF A < B

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Exactly One of these 3 outputs equals 1, while the other 2 outputs are 0`s.
Solution:
Inputs: 8-bits (A ⇒ 4-bits, B ⇒ 4-bits).A and B are two 4-bit numbers. Let A = A3A2A1A0, and Let B = B3B2B1B0.
Design of the EQ
 Define Xi = Ai xnor Bi = Ai Bi + Ai’ Bi’
Xi = 1 IFF Ai = Bi ∀ i =0, 1, 2 and 3
Xi = 0 IFF Ai ≠ Bi
 Therefore the condition for A = B or EQ=1 IFF
A3= B3 → (X3 = 1), and A2= B2 → (X2 = 1), and A1= B1 → (X1 = 1), and A0= B0 → (X0 = 1).
 Thus, EQ=1 IFF X3 X2 X1 X0 = 1. In other words, EQ = X3 X2 X1 X0
Designing GT and LT:
 GT = 1 if A > B:
If A3 > B3 3= 1 and B3 = 0 If A3 = B3 and A2 > B2
If A3 = B3 and A2 = B2 and A1 > A1
If A3 = B3 and A2 = B2 and A1 = B1 and A0 > B0
 Therefore,
GT = A3B3‘+ X3 A2 B2‘+ X3 X2 A1 B1‘+ X3 X2 X1A0 B0‘
Similarly, LT = A3’B3 + X3 A2‘B2 + X3 X2 A1’B1 + X3 X2 X1A0’ B0
Decoder: A decoder is a logic circuit that accepts a set of inputs that represents a binary number and activates
only the output that corresponds to the input number.
• A decoder has ------ N nputs and 2N outputs
• Exactly one output will be active for each combination of the inputs.

 Each of these input combinations only one of the M outputs will be active HIGH (1), all the other outputs are
LOW (0).
 An AND gate can be used as the basic decoding element because it produces a HIGH output only when all
inputs are HIGH.
 If an active-LOW output (74138, one of the output will low and the rest will be high) is required for each
decoded number, the entire decoder can be implemented with NAND gates Inverters

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 If an active-HIGH output (74139, one of the output will high and the rest will be low) is required for each
decoded number, the entire decoder can be implemented with AND gates Inverters
Decoder example: 2-to-4-Line Decoder

3. line to 8 line decoder (active-HIGH)

• It can be called a 3-line-to- 8-line decoder, because it has three input lines and eight output lines.
• It could also be called a binary-octal decoder or converters because it takes a three bit binary input code and
activates the one of the eight outputs corresponding to that code. It is also referred to as a 1-of-8 decoder,
because only 1 of the 8 outputs is activated at one time.

Application example
 A simplified computer I/O port system with a port address decoder with only four address lines shown.

• Computer must communicate with a variety of external devices called peripherals by sending and/or receiving
data through what is known as input/output (I/O) ports
• Each I/O port has a number, called an address, which uniquely identifies it. When the computer wants to
communicate with a particular device, it issues the appropriate address code for the I/O port to which that

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particular device is connected. The binary port address is decoded and appropriate decoder output is activated to
enable the I/O port
• Binary data are transferred within the computer on a data bus, which is a set of parallel lines
BCD -to- Decimal decoders
• The BCD- to-decimal decoder converts each BCD code into one of Ten Positional decimal digit indications. It is
frequently referred as a 4-line -to- 10 line decoder
• The method of implementation is that only ten decoding gates are required because the BCD code represents
only the ten decimal digits 0 through 9.
• Each of these decoding functions is implemented with NAND gates to provide active -LOW outputs. If an
active HIGH output is required, AND gates are used for decoding.

BCD to 7-Segment Display Decoder

1. Used to convert a BCD or a binary code into a 7 segment code used to operate a 7 segment LED display.
2. It generally has 4 input lines and 7 output lines. Here we design a simple display decoder circuit using logic
gates
Encoder
 Encoders typically have 2N inputs and N outputs.
 These are called 2N–to–N encoders.
 Encoders can also be devised to encode various symbols and alphabetic characters.
 The process of converting from familiar symbols or numbers to a coded format is called encoding.

8 to-3 encoder Implementation

 Octal-to-Binary
 An octal to binary encoder has 23 = 8 input lines D0 to D7 and 3 output lines Y0 to Y2. Below is the

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Truth table for an octal to binary encoder.

From the truth table, the outputs can be expressed by following Boolean Function. Y0 = D1 + D3 + D5 + D7
Y1 = D2 + D3 + D6 + D7
Y2 = D4 + D5 + D6 + D7
Note: Above Boolean functions are formed by ORing all the input lines for which output is 1. For instance Y0 is 1
for D1, D3, D5, D7 input lines. The encoder can therefore be implemented with OR gates whose inputs are
determined directly from truth table as shown in the image below:

Decimal – BCD encoder

• Encoder will produce a BCD output corresponding to the highest-order decimal digit input that is active and will
ignore any other lower order active inputs.

From the truth table, the outputs can be expressed by following Boolean Function.
Note: Below Boolean functions are formed by ORing all the input lines for which output is 1. For instance A0 is 1
for 1,3,5,7 or 9 input lines.
A0 = 1+3+5+7+9
A1 = 2+3+6+7
A2 = 4+5+6+7
A3 = 8+9
The decimal to bcd encoder can therefore be implemented with OR gates whose inputs are determined directly
from truth table as shown in the image below.

Multiplexer
 A multiplexer or mux is a device that selects one of several analog or digital input signals and forwards the
selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which
input line to send to the output.”
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 The select lines determine which input is connected to the output.
 MUX Types
2-to-1 (1 select line)
4-to-1 (2 select lines)
8-to-1 (3 select lines)
16-to-1 (4 select lines) 4to-1 Multiplexer (MUX)

The Boolean expression for this 4-to-1 Multiplexer above with inputs D0 to D3 and data select lines A, B is given as:
Y = A’B’D0 + A’B D1 + AB’D2 + ABD3
DE multiplexer
• A DEMUX is a digital switch with a single input (source) and a multiple outputs (destinations).
• The select lines determine which output the input is connected to.
• DEMUX Types
• 1-to-2 (1 select line)
• 1-to-4 (2 select lines)
• 1-to-8 (3 select lines)
• 1-to-16 (4 select lines)
1to-4 De-Multiplexer (DEMUX)
Parity Bit Generator
 The most common error detection code used is the parity bit.
 A parity bit is an extra bit included with a binary message to make the total number of 1's either odd or even.
 A parity bit added to n-bit code produces (n+1)-bit code with an odd (or even) count of 1s
 Odd Parity bit: count of 1s in (n+1)-bit code is odd
 So use an even function to generate the odd parity bit
 Even Parity bit: count of 1s in (n+1)-bit code is even
 So use an odd function to generate the even parity bit
 To check for odd parity
 Use an even function to check the (n+1)-bit code
 To check for even parity
 Use an odd function to check the (n+1)-bit code
Even Parity Generators and Checkers for 3-bit codes
 An even parity bit could be added to n-bit code to produce an n + 1 bit code:
 Use an odd function to produce codes with even parity
 Use odd function circuit to check code words with even parity
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Example: n = 3. Generate even parity code words of length 4 with an odd function circuit (parity generator):
The design procedure is made simple by writing the truth table for the circuit.

 Operation: (X,Y,Z) = (0,0,1) gives (X,Y,Z,P) = (0,0,1,1) and E = 0.If Y changes from 0 to 1 between generator
and checker, then E = 1 indicates an error.
Odd Parity Generators and Checkers
 Similarly, an odd parity bit could be added to n-bit code to produce an n + 1 bit code
Message Odd Checker
• Use an even function to produce codes with odd parity Parity Bit
X Generator
Y C
• Use even function circuit to check code words with odd parity Z
P
0 0 0 1 0
This function can be implemented using XOR and XNOR gates, shown in fig. 0 0 1 0 0
0 1 0 0 0
Similarly the checker circuit can be designed using XOR and XNOR gates, 0 1 1 1 0
where 1 0 0 0 0
1 0 1 1 0
1 1 0 1 0
1 1 1 0 0

PLA [Programmable Logic Array]

 Combination of a programmable AND array followed by a programmable OR array.
This layout allows for a large number of logic functions to be synthesized in the sum of products (and sometimes
product of sums) canonical forms

Example: Design a PLA to realize the following logic functions f0 (A'.B'+ A. C')
f1 (A. C'+ B) f2 (A'.B'+ B. C’) f3 (B+ AC)

Example: Design a PLA to realise the following three logic functions f1 (A, B, C, D, E) =
A'.B'.D' + B'.C.D' + A'.B.C.D.E'

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f2 (A, B, C, D, E) = A'.B.E + B'.C.D'.E
f3 (A, B, C, D, E) = A'.B'.D' + B'.C'.D'.E + A'.B.C.D

SEQUENTIAL LOGIC CIRCUITS

Sequential circuits are constructed using combinational logic and a number of memory elements
with some or all of the memory outputs fed back into the combinational logic forming a feedback
path or loop.
Sequential circuit = Combinational logic + Memory Elements
There are two types of sequential circuits:
 synchronous: outputs change only at specific time
 asynchronous: outputs change at any time
A state variable in a sequential circuit represents the single-bit variable Q stored in a memory element in circuit.
– Each memory element may be in state 0 or state 1 depending on the current value stored in the memory
element.
The State of A sequential Circuit:
– The collection of all state variables (memory element stored values) that at any time contain all the information
about the past necessary to account for the circuit’s future behavior.
– A sequential circuit that contains n memory elements could be in one of a maximum of 2n states at any given
time depending on the stored values in the memory elements.
– Sequential Circuit State transition: A change in the stored values in memory elements thus changing the
sequential circuit from one state to another.
Clock Signals & Synchronous Sequential Circuits
• A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed
intervals.
 Clock cycle time or clock period: The time interval between two consecutive rising or falling edges of the clock.

Synchronous Sequential Circuits: Sequential circuits that have a clock signal as one of its inputs:
– All state transitions in such circuits occur only when the clock value is either 0 or 1 or happen at the rising or
falling edges of the clock depending on the type of memory elements used in the circuit.

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Sequential Circuit Memory Elements: Latches, Flip-Flops
• Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two
inputs/outputs, designed using individual logic gates and feedback loops.
• Latches: – The output of a latch depends on its current inputs and on its previous inputs and its change of state can
happen at any time when its inputs change.
• Flip-Flop: – The output of a flip-flop also depends on current and previous input but the change in output (change
of state or state transition) occurs at specific times determined by a clock input.
S-R Latch: An S-R (set-reset) latch can be built using two NOR gates forming a feedback loop.
• The output of the S-R latch depends on current as well as previous inputs or state, and its state (value stored) can
change as soon as its inputs change.
 When Q is HIGH, the latch is in SET state.
 When Q is LOW, the latch is in RESET state.
SR Flip flop
 Since the S-R latch is responsive to its inputs at all times an enable line C is used to disable or enable state
transitions.
 Behaves similar to a regular S-R latch when enable C=1

S = 0, R = 0; this is the normal resting state of the circuit and it has no effect of the output states. Q and Q’
Will remain in whatever state they were in prior to the occurrence of this input condition. It works in HOLD (no
change) mode operation. • S = 0, R = 1; this will reset Q to 0, it works in RESET mode operation.
S = 1, R = 0; this will set Q to 1, it works in SET mode operation.
S = 1, R = 1; this condition tries to set and reset the NOR gate latch at the same time, and it produces Q = ¯ = 0.
This is an unexpected condition and are not used.
Since the two outputs should be inverse of each other. If the inputs are returned to 1 simultaneously, the
Output states are unpredictable. This input condition should not be used and when circuits are constructed, the
design should make this condition SET=RESET = 1 never arises.
Clocked SR Flip Flop
Additional clock input is added to change the SR flip-flop from an element used in asynchronous sequential
circuits to one, which can be used in synchronous circuits.

Clocked SR Flip Flop Circuit with PRESET and CLEAR

 Some flip-flops have asynchronous preset Pr and clear Cl signals.
 Output changes once these signals change, however the input signals must wait for a change in clock to
change the output

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JK Flip Flop : Another types of Flip flop is JK flip flop.

 It differs from the RS flip flops when J=K=1 condition is not indeterminate but it is defined to give
a very useful changeover (toggle) action.
 Toggle means that Q and Q ¯ will switch to their opposite states.
 The JK Flip flop has clock input Cp and two control inputs J and K.
 Operation of Jk Flip Flop is completely described by truth table

JK Flip Flop with preset and clear : This flip flop can also have other inputs called Preset (or SET) and clear
that can be used for setting the flip Flop to 1 or resetting it to 0 by applying the appropriate signal to the Preset
and Clear inputs. These inputs can change the state of the flip flop regardless of synchronous inputs or the clock.

T Flip Flop: The T flip flop has only the Toggle and Hold Operation. If Toggle mode operation. The output
will toggle from 1 to 0 or vice versa.

D Flip Flop
 Also Known as Data Flip flop
 Can be constructed from RS Flip Flop or JK Flip flop by addition of an inverter.
 Inverter is connected so that the R input is always the inverse of S (or J input is always complementary of
K).
 The D flip flop will act as a storage element for a single binary digit (Bit).

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EDGE TRIGGERED FLIP FLOP
 Edge triggered flip-flop changes only when the clock C changes
 The three basic types are introduced here: S-R, J-K and D.
Edge-triggered S-R flip-flop : The basic operation is illustrated below, along with the truth table for this type
of flip-flop. The operation and truth table for a negative edge-triggered flip-flop are the same as those for a
positive except that the falling edge of the clock pulse is the triggering edge.

Edge-triggered J-K flip-flop: The J-K flip-flop works very similar to S-R flip-flop. The only difference is that
this flip-flop has NO invalid state. The outputs toggle (change to the opposite state) when both J and K inputs
are HIGH.
Edge-triggered D flip-flop: The operations of a D flip-flop is much simpler. It has only one input addition to
the clock. It is very
Useful when a single data bit (0 or 1) is to be stored. If there is a HIGH on the D input when a clock pulse
is applied, the flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the
flip-flop RESETs and stores a 0. The truth table below summarize the operations of the positive edge-triggered
D flip-flop. As before, the negative edge-triggered flip-flop works the same except that the falling edge of the
clock pulse is the triggering edge.
MASTER-SLAVE FLIP FLOP
 Is designed using two separate flip flops. Out of these, one acts as the master and the other as a slave. The figure
of a master-slave J-K flip flop is shown below.

From the above figure you can see that both the J-K flip flops are presented in a series connection. The output of
the master J-K flip flop is fed to the input of the slave J-K flip flop. The output of the slave J-K flip flop is given
as a feedback to the input of the master J-K flip flop. The clock pulse [Clk] is given to the master J-K flip flop
and it is sent through a NOT Gate and thus inverted before passing it to the slave J-K flip flop.

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