Module 1 – Introduction to 8086

101003/CS500D
Microprocessors and Microcontrollers
Syllabus

● 8086 microprocessor – Architecture and signals,

● Physical Memory organization, Minimum and maximum mode of 8086 system

and timings.

● Comparison of 8086 and 8088.

● Machine language Instruction format.

Course Outcomes

● CO1: Illustrate the architecture, modes of operation and addressing

modes of microprocessors.
● CO2: Develop 8086 assembly language programs.
● CO3: Demonstrate interrupts, its handling and programming in 8086.
● CO4: Illustrate how different peripherals (8255,8254,8257) and memory are
interfaced with microprocessors.
● CO5: Outline features of microcontrollers and develop low level programs.
Microprocessors
Microcontrollers
Microprocessors and Microcontrollers
Microprocessor Microcontroller

Silicon-based IC with only a central processing Mini computer with a CPU

unit.
RAM, ROM, serial ports, timers, and IO
Don’t have RAM, ROM, IO pins, timers, and peripherals all embedded on a single chip.
other peripherals on the chip - Added
Designed to perform application specific tasks
externally to make them functional.
that require a certain degree of control.
Designed for general purpose applications
such as logical operations in computer
system
Evolution of Microprocessors
4004 8080 8086

First 4 bit Microprocessor 8 bit Microprocessor First 16 bit Microprocessor

1971 1972 1974 1975 1978

8008 8085

First 8 bit Microprocessor 8 bit Microprocessor

Microprocessor

● The microprocessor is a programmable device that takes in numbers,

performs on them arithmetic or logical operations according to the
program stored in memory and then produces other numbers as a result.

● Programmable Device: Works based on instructions

● Input Devices: The data and instructions comes through input devices
● Numbers: Microprocessor understands only binary numbers (1s and 0s)
Microprocessor

● Arithmetic and Logic Operations: Arithmetic operations like add, subtract and
logical operations like AND, OR, XOR etc.
● Memory: collection of storage devices where information is kept while not in
current use.
● Produces: For the user to see the result of the execution of the program, the
results must be presented in a human readable form , through output devices.
Microprocessor Based System
Fetch-Deode and Execute cycle

● To execute a program, the microprocessor fetches each instruction,

● decodes it,
● & executes it.
● This sequence is continued until all instructions are performed.
 ● 8-bit general purpose
processor

8085
● Capable of addressing 64 k of
memory (216 )

Microprocessor ● Has 40 pins

● Requires +5 v power supply
● Can operate with 3 MHz clock
 ● First 16-bit processor
● 16-bit external data bus

8086
● 20 bit address bus (1 MB)
● More powerful instruction set
Microprocessor ● 3 Clock frequency - 5, 8 and
10 MHz
● 40 Pin IC
 ● 16 bit Registers

8086 ○ General Purpose

Registers

Register Organization ○ Special Purpose Registers

Register Organization of 8086
General Data Registers

● AX, BX, CX and DX

● AX → 16 bit accumulator
○ AL - Lower 8 bits, AH - Higher 8 bits
○ Most important GPR
● BX
○ Offset storage for physical address in certain
addressing modes
● CX
○ Default counter for string and loop operations
● DX
○ Implicit operand or destination
Segment Registers
● 1 MB of Memory
○ 16 logical segments of 64 KB
● 4 Segment Registers
● Code Segment Register
○ Addressing a memory location in CS
○ CS → Executable program is stored
● Data Segment Register
○ Points to DS → Data is stored
● Extra Segment Register
○ Also contains Data
● Stack Segment Register
○ Store Stack data - temporarily store important data
Pointers and Index Registers

● Pointers contain offsets within particular segments.

○ Instruction Pointer → Offset for CS
○ Base Pointer → Offset for DS
○ Stack Pointer → Offset for SS
● Index Registers
○ General Purpose Registers
○ Or offset storage
○ Source Index → Offset of Source data in DS
○ Destination Index → Offset of Destination data in ES
○ Useful for string manipulations
Flag Register

● Indicates the results of computations

● Contains flag bits to control CPU operations

 ● 16 bit ALU
● 16 bit registers (14 numbers)

8086 ● Segmented Memory

addressing capability
Architecture ● Rich instruction set
● Powerful interrupt structure
● Fetched Instruction queue
 8086 ● Divided into 2 parts
● Bus Interface Unit (BIU)
Architecture ● Execution Unit (EU)
Bus Interface Unit
• Contains the circuit for physical address calculations

• And a pre-decoding instruction byte queue (6 bytes long)

• Handles all transactions of data and addresses on the buses for the execution unit:
• sends out addresses
• fetches instructions from memory
• reads data from ports and memory
• writes data to ports and memory
Bus Interface Unit

• BIU contains
• 6 byte instruction queue
• Segment Registers
• Instruction Pointer (IP)
• Address conversion mechanism (adder)
Instruction Queue

• Implement pipeline architecture.

• Permits pre-fetch of up to six bytes of instruction code.
• Overlapped fetch and execution cycles.
• When EU is busy executing , the BIU is free to look ahead in the program by pre-fetching the next
sequential instruction.
• FIFO structure.
• Instructions from queue are taken out for decoding sequentially and queue arranged accordingly.
• When the decoded instruction is executed by EU the BIU pre-fetches the next instruction and forms
a pipeline.
Segmented Memory

• The complete physically available memory (1 MB) may be divided into a number of logical
segments.
• A segment is a 64 KB block of memory
• The 16 bit contents of the segment registers in the BIU actually point to the starting location of a
particular segment.
• Complete physical address of 20 bits generated using segment and offset register (each16 bit long)
• Physical Address = Segment Address + Offset Address
• Segment Register → Segment Address
• Offset Register → Offset Address
• Performed by the address conversion mechanism (adder)
Address Calculation
● Segment Address = 1000H

● Offset Address = 0020H

● The calculation of the actual address is done as follows.

1. Left shift the 16-bit address present in the segment register by 4-bits
0001 0000 0000 0000 (0000)

2. Add the 16-bit offset address to this shifted base address

0001 0000 0000 0000 0000
+ 0000 0000 0010 0000
0001 0000 0000 0010 0000

So the actual address turns out to be 10020H.

Segmented Memory

• The address of segments may be assigned as 0000H to F000H respectively.

• The offset address values are from 0000H to FFFFH so that the physical address range from
00000H to FFFFFH.
• These are called as non-overlapping segments.
• If a segment starts before the 64kbytes locations of another segment, then these 2 segments are
called as overlapping segments.
• Locations lying in the overlapped area may be address by the same physical address generated
from 2 different sets of segment and offset address.
Non overlapping Segments Overlapping Segments
Execution Unit
• Decodes instructions fetched by the BIU (Decoding circuit)

• Generate control signals (Timing and control unit)

• Gives instructions to ALU for execution (16 bit ALU )

• Contains the register set of 8086 except the segment registers and IP

• 16 bit flag register reflects the result of execution by ALU

• May pass the results to BIU for storing in memory

Flag Register
• 16 bit flag register – divided into 2 parts.

• Condition Code or Status Flags

o Lower byte of Flag register along with the overflow flag

o Reflects the results of operations performed by the ALU

• Machine Control Flags

o Higher byte of the Flag register

o Contains Direction Flag (D), Interrupt Flag (I) and Trap Flag (T)
Flag Purpose

Carry (CF) Holds the carry after addition or the borrow after subtraction. Also indicates
some error conditions, as dictated by some programs and procedures

Parity (PF) PF = 0; odd parity, PF = 1;even parity . Set to 1 if the lower byte of result
has even number of 1s

Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after subtraction
between bit positions 3 and 4 of the result

Zero (ZF) Shows the result of the arithmetic or logic operation. Z = 1; result is zero.
Z = 0; otherwise

Sign (SF) Holds the sign of the result after an arithmetic/logic instruction execution.
S = 1; negative, S = 0; positive

Overflow (OF) Overflow occurs when signed numbers are added or subtracted. An
overflow indicates the result has exceeded the capacity of the machine
Flag Purpose

Trap (TF) A control flag.

Enables the trapping through an on-chip debugging feature.
Interrupt (IF) A control flag.
Controls the operation of the INTR (interrupt request) I = 0; INTR pin
disabled. I = 1; INTR pin enabled.
Direction (DF) A control flag.
It selects either the increment or decrement mode for DI and /or SI
registers during the string instructions.
D = 0; Autoincrementing Mode D = 1; Autodecrementing mode
X Not Used
 ● 8086 - 16 bit CPU
● Available in 3 clock rates -
5,8 and 10 MHz
● Packaged in a 40 pin dual in
8086 line package

Operating Configurations ● 2 Operating configurations:

○ Single Processor or Minimum
Mode

○ Multiprocessor or Maximum
Mode
Pin Configuration of 8086
 ● 8086 Signals can be
categorised into 3 groups:

○ Having common functions in

8086 Signals minimum

mode.
and maximum

○ Having special functions in

minimum mode.

○ Having special functions in

maximum mode.
Common for both minimum and maximum modes
Address/Data lines Address/Status lines
● AD15- AD0 ● A19 - A16 / S6 - S3
● Time multiplexed address and data ● Time multiplexed address and status
lines. lines
● 16 bit Address → T1 clock state.
● 4 bit address - T1 clock state.
● 16 bit Data → T2 , T3 , T4 and Tw clock
states. ● Status signals → T2 , T3 , T4 and Tw clock
states.
● Tw → wait state

● S4 and S3 indicate which segment

● Active high signals. register is currently used for memory
access
Bus High Enable/Status Read
● BHE/S7 ● RD

● Used to indicate the transfer of ● When low indicates that the

data using higher order data bus processor is performing a memory
D15- D8. or I/O read operation.

● BHE signal is low during T1. ● Active low signal.

● Status information is available

during T2 , T3 and T4 .
READY Interrupt Request
● Acknowledgement signal from I/O ● INTR Interrupt request signal
devices that data ready to be
● Sampled during the last clock cycle
transferred.
of each instruction to determine
● It is an active high signal. the availability of the request.

● When it is high, it indicates that the ● If any interrupt request is pending

device is ready to transfer data. the processor enters the interrupt
acknowledge cycle.
● When it is low, it indicates wait
state.
● Level triggered input and also an
active high signal.
TEST Non-maskable Interrupt
● TEST ● NMI
● When it is low the execution ● Edge triggered
continues.
● Not maskable internally by
● When this signal is high, then the software.
processor remains in IDLE state.
Clock Input RESET
● CLK ● Used to restart the execution.

● Provides timing to the processor ● It causes the processor to

for operations. immediately terminate its present
activity.
● Asymmetric square wave with 33%
duty cycle. ● This signal must be active high for
at least 4 clock cycles to RESET the
● Frequency is different for different
microprocessor.
versions, i.e. 5MHz, 8MHz and
10MHz. ● Execution restarts when the RESET
returns to low
VCC
MN/MX
● +5V Power supply for the operation
of the internal circuit ● The logic level indicates what mode
the processor is to operate in.

● When it is high, it works in the

GND
minimum mode.
● Ground for the internal circuit ● When low, it works in maximum
mode.
Functions for minimum mode operation of 8086

Address Latch Enable Data Enable

● ALE. ● DEN.

● Indicates the availability of a valid ● Indicates the availability of valid

address on the address/data lines. data over the address/data lines.

● Active high signal

Data Transmit/Receive Memory/IO
● DT/ R ● M/I/O

● Decides the direction of data flow ● Used to distinguish between

through the transreceiver. memory and I/O operations.

● When it is high, data is transmitted ● When it is low, it indicates I/O

out operation.

● When it is low, the processor is ● When it is high indicates the

receiving data. memory operation.
Interrupt Acknowledge Hold/Hold Acknowledge
● INTA ● HOLD/HLDA
● When it is low it means that the ● HOLD Indicates to the processor
processor has accepted the that external devices are
interrupt. requesting to access the
address/data buses.
WRITE
● HLDA acknowledges the HOLD
● WR signal

● Used to denote a memory or IO

write operation.
Functions for maximum mode operation of 8086
Queue Status - QS1, QS0
● Provide the status of instruction queue.

QS1 QS0 Indication

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty queue

1 1 Subsequent byte from the queue

Status Lines - S2, S1, S0
● Status signals that reflect the type of operation being carried out by the processor.

S2 S1 S0 Indication

0 0 0 Interrupt Acknowledge

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode Fetch

1 0 1 Memory Read

1 1 0 Memory Write

1 1 1 Passive
LOCK Request/Grant Signals
● When low indicates to the other ● RQ / GT0, RQ / GT1
processors not to ask the CPU to
leave the system bus.
● Request/Grant signals used by the
● Activated using the LOCK prefix on
other processors requesting the
any instruction
CPU to release the system bus.

● When the signal is received by CPU,

then it sends acknowledgment.

● RQ / GT0 has higher priority than

RQ / GT1
 ● 1 MB of memory organized
as:
8086 ○ Odd Bank (512 Kbytes)

Physical Memory Organization

○ Even Bank (512 Kbytes)
Memory Organization of 8086

• There are 20 address lines in the 8086 microprocessor.

• This gives 220 different memory locations.
• Hence the total size is 220 Bytes which is equal to 1MB.
• Each memory location is Byte Addressable, i.e. one byte of data can be stored at every single
location.
• The 8086 microprocessor an easily handle up to 16 bits of data at a time through its 16 data lines.
• So, to organize the memory efficiently, the entire memory in 8086 is divided into two memory
banks:
• Odd bank and the Even bank.
kB kB
Memory Organization of 8086

• The byte-wide storage locations are assigned consecutive addresses over the range from 00000H
to FFFFFH.
• Data bytes associated with an even address (00000, 00002 etc.) reside in the even bank and those
with the odd address (00001, 00003 etc.) reside in the odd bank.
• Address bits A1 through A19 select the storage location that is to be accessed.
• They are applied to both banks in parallel.
• A0 and BHE are used as bank-select signals.
• Each of the memory bank provides half of the 8086’s 16 bit data bus.
Note : To access odd addressed word two bus cycles are required.
 ● 2 Operating configurations:

8086 ○ Single Processor or Minimum

Mode

Operating Modes ○ Multiprocessor or Maximum

Mode
Minimum Mode
● 8086 operates in minimum mode by strapping its MN/MX pin to logic 1.

● All the control signals are given out by the microprocessor chip itself.

● There is a single microprocessor in the minimum mode system.

● The remaining components in the system are latches, transreceivers, clock

generator, memory and I/O devices.
● Latches are generally buffered output D-type flip-flops.

● They are used for separating the valid address from the multiplexed address/data
signals and are controlled by the ALE signal generated by 8086.

● Transreceivers are the bidirectional buffers and some times they are called as data
amplifiers required to separate the valid data from the time multiplexed
address/data signals.

● They are controlled by two signals namely, DEN and DT/R.

● The DEN signal indicates that valid data is available on the data bus, while DT/R
indicates the direction of data, i.e. from or to the processor.
8086 Minimum Mode Diagram
Timing Diagram
● The working of the minimum mode can be better described in terms of the timing
diagram.

● The opcode fetch and read cycles are similar.

● Hence the timing diagram can be categorized in two parts:

o first is the timing diagram for read cycle.

o second is the timing diagram for write cycle.

Read Cycle Timing Diagram for Minimum Mode
● The read cycle begins in T1 with the assertion of address latch enable (ALE) signal
and also M / IO signal.

● During the negative going edge of this signal, the valid address is latched on the
local bus.

● At T2, the address is removed from the local bus and is sent to the output.

● The bus is then tristated.

● The read (RD) control signal is also activated in T2.

● The read (RD) signal causes the addressed device to enable its data bus
drivers.

● After RD goes low, the valid data is available on the data bus.

● The addressed device will drive the READY line high.

● When the processor returns the read signal to high level, the addressed
device will again tri state its bus drivers.
Write Cycle Timing Diagram for Minimum Mode
● A write cycle also begins with the assertion of ALE and the emission of the
address.

● The M/IO signal is again asserted to indicate a memory or I/O operation.

● In T2, after sending the address in T1, the processor sends the data to be
written to the addressed location.

● The data remains on the bus until middle of T4 state.

● The WR becomes active at the beginning of T2 (unlike RD is somewhat

delayed in T2 to provide time for floating).
● The M/IO, RD and WR signals indicate the type of data transfer as
specified in table below.
Maximum Mode
● 8086 operates in maximum mode by strapping its MN/MX pin to ground.

● In this mode, the processor derives the status signal S2, S1, S0.

● Another chip called bus controller derives the control signal using this status
information .

● In the maximum mode, there may be more than one microprocessor in the system
configuration.
8086 Maximum Mode Diagram
● The components in the system are same as in the minimum mode
system.

● The basic function of the bus controller chip IC8288, is to derive control
signals like:

● ○RD and WR ( for memory and I/O devices),

● ○DEN, DT/R, ALE etc. using the information by the processor on the status lines.

● The bus controller chip 8288 has input lines S2, S1, S0 and CLK.

● These inputs to 8288 are driven by CPU.

● It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWTC, IORC, IOWC
and AIOWC.
● IORC, IOWC are I/O read command and I/O write command signals respectively .

● These signals enable an IO interface to read or write the data from or to the
address port.

● The MRDC, MWTC are memory read command and memory write command
signals respectively and may be used as memory read or write signals.

● All these command signals instructs the memory to accept or send data from or to
the bus.

● For both write command signals, the advanced signals namely AIOWC and AMWTC
are available.

● They also serve the same purpose but are activated one clock cycle earlier than
IOWC and MWTC respectively
 ● Variant of the Intel 8086

8088 ● Introduced on June 1, 1979

● 8088 has an eight-bit external
Microprocessor data bus instead of the 16-bit
bus of the 8086.
8088 Microprocessor

• 16-bit registers.
• One megabyte address range like 8086.
• According to Intel documentation, the 8086 and 8088 have the same execution unit
(EU)—only the bus interface unit (BIU) is different.
• The 8088 was targeted at economical systems.
• Allows the use of an eight-bit data path and eight-bit support and peripheral chips.
• It could use all the support chips of the 8080, an 8-bit CPU and predecessor of the
8086 (like the DMA-controller, interrupt controller, etc.).
 8086 ● Example:
ADD AX, BX
Machine Language
Instruction Format
OPCODE DESTINATION SOURCE
OPERAND OPERAND
General Instruction Format for 8086

• An instruction can be coded with 1 to 6 bytes

OPCODE D W MOD REG R/M

General Instruction Format for 8086

• Byte 1 contains three kinds of information:

▪ Opcode field (6 bits): Specifies the operation (add, subtract, move)
▪ Register Direction Bit (D bit): Tells the register operand in REG field in byte 2 is source or
destination operand
• 1→ destination

• 0 →source

▪ Data Size Bit (W bit): Specifies whether the operation will be performed on 8-bit or 16-bit
data
• 0 →8 bits

• 1→ 16 bits
General Instruction Format for 8086

• Byte 2 has three fields:

▪ Mode field (MOD)
▪ Register field (REG) used to identify the register for the first operand
▪ Register/Memory field (R/M field)
General Instruction Format for 8086

▪ Register field (REG field)

General Instruction Format for 8086

▪ 2-bit MOD field and 3-bit R/M field together specify the second operand

MOD Field encoding

General Instruction Format for 8086

▪ 2-bit MOD field and 3-bit R/M field together specify the second operand

R/M Field encoding

General Instruction Format for 8086
• Example:
• MOV BL, AL → (88C316)
• Opcode for MOV = 100010

• D = 0 (AL source operand)

• W bit = 0 (8-bits)

• Therefore byte 1 is 100010002 = 8816

• MOD = 11 (register mode)

• REG = 000 (code for AL)

• R/M = 011 (destination is BL)

• Therefore Byte 2 is 110000112 = C316

General Instruction Format for 8086
• Example:
• ADD AX, [SI] → (030416)
• Opcode for ADD = 000000

• D = 1 (AX destination operand)

• W bit = 1 (16-bits)

• Therefore byte 1 is 000000112 = 0316

• MOD = 00 (memory mode with no displacement)

• REG = 000 (code for AX)

• R/M = 100 (destination is SI)

• Therefore Byte 2 is 000001002 = 0416

General Instruction Format for 8086
• Example:
• ADD [BX] [DI] + 1234h, AX → (0181341216)
• Opcode for ADD = 000000

• D = 0 (AX destination operand)

• W bit = 1 (16-bits)

• Therefore byte 1 is 000000012 = 0116

• MOD = 10 (memory mode with 16 bit displacement)

• REG = 000 (code for AX)

• R/M = 001 (destination is BX + DI)

• Therefore Byte 2 is 100000012 = 8116